1 /**************************************************************************//**
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2 * @file system_LPC17xx.c
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3 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
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4 * for the NXP LPC17xx Device Series
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6 * @date 07. October 2009
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9 * Copyright (C) 2009 ARM Limited. All rights reserved.
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12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
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13 * processor based microcontrollers. This file can be freely distributed
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14 * within development tools that are supporting such ARM based processors.
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17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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23 ******************************************************************************/
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27 #include "LPC17xx.h"
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30 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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33 /*--------------------- Clock Configuration ----------------------------------
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35 // <e> Clock Configuration
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36 // <h> System Controls and Status Register (SCS)
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37 // <o1.4> OSCRANGE: Main Oscillator Range Select
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38 // <0=> 1 MHz to 20 MHz
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39 // <1=> 15 MHz to 24 MHz
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40 // <e1.5> OSCEN: Main Oscillator Enable
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44 // <h> Clock Source Select Register (CLKSRCSEL)
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45 // <o2.0..1> CLKSRC: PLL Clock Source Selection
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46 // <0=> Internal RC oscillator
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47 // <1=> Main oscillator
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48 // <2=> RTC oscillator
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51 // <e3> PLL0 Configuration (Main PLL)
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52 // <h> PLL0 Configuration Register (PLL0CFG)
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53 // <i> F_cco0 = (2 * M * F_in) / N
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54 // <i> F_in must be in the range of 32 kHz to 50 MHz
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55 // <i> F_cco0 must be in the range of 275 MHz to 550 MHz
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56 // <o4.0..14> MSEL: PLL Multiplier Selection
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59 // <o4.16..23> NSEL: PLL Divider Selection
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65 // <e5> PLL1 Configuration (USB PLL)
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66 // <h> PLL1 Configuration Register (PLL1CFG)
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67 // <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
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68 // <i> F_cco1 = F_osc * M * 2 * P
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69 // <i> F_cco1 must be in the range of 156 MHz to 320 MHz
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70 // <o6.0..4> MSEL: PLL Multiplier Selection
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72 // <i> M Value (for USB maximum value is 4)
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73 // <o6.5..6> PSEL: PLL Divider Selection
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82 // <h> CPU Clock Configuration Register (CCLKCFG)
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83 // <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
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87 // <h> USB Clock Configuration Register (USBCLKCFG)
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88 // <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
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90 // <i> Divide is USBSEL + 1
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93 // <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
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94 // <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
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95 // <0=> Pclk = Cclk / 4
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97 // <2=> Pclk = Cclk / 2
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98 // <3=> Pclk = Hclk / 8
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99 // <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
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100 // <0=> Pclk = Cclk / 4
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101 // <1=> Pclk = Cclk
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102 // <2=> Pclk = Cclk / 2
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103 // <3=> Pclk = Hclk / 8
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104 // <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
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105 // <0=> Pclk = Cclk / 4
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106 // <1=> Pclk = Cclk
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107 // <2=> Pclk = Cclk / 2
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108 // <3=> Pclk = Hclk / 8
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109 // <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
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110 // <0=> Pclk = Cclk / 4
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111 // <1=> Pclk = Cclk
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112 // <2=> Pclk = Cclk / 2
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113 // <3=> Pclk = Hclk / 8
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114 // <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
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115 // <0=> Pclk = Cclk / 4
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116 // <1=> Pclk = Cclk
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117 // <2=> Pclk = Cclk / 2
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118 // <3=> Pclk = Hclk / 8
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119 // <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
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120 // <0=> Pclk = Cclk / 4
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121 // <1=> Pclk = Cclk
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122 // <2=> Pclk = Cclk / 2
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123 // <3=> Pclk = Hclk / 8
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124 // <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
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125 // <0=> Pclk = Cclk / 4
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126 // <1=> Pclk = Cclk
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127 // <2=> Pclk = Cclk / 2
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128 // <3=> Pclk = Hclk / 8
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129 // <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
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130 // <0=> Pclk = Cclk / 4
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131 // <1=> Pclk = Cclk
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132 // <2=> Pclk = Cclk / 2
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133 // <3=> Pclk = Hclk / 8
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134 // <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
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135 // <0=> Pclk = Cclk / 4
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136 // <1=> Pclk = Cclk
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137 // <2=> Pclk = Cclk / 2
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138 // <3=> Pclk = Hclk / 8
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139 // <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
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140 // <0=> Pclk = Cclk / 4
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141 // <1=> Pclk = Cclk
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142 // <2=> Pclk = Cclk / 2
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143 // <3=> Pclk = Hclk / 8
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144 // <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
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145 // <0=> Pclk = Cclk / 4
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146 // <1=> Pclk = Cclk
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147 // <2=> Pclk = Cclk / 2
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148 // <3=> Pclk = Hclk / 8
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149 // <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
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150 // <0=> Pclk = Cclk / 4
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151 // <1=> Pclk = Cclk
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152 // <2=> Pclk = Cclk / 2
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153 // <3=> Pclk = Hclk / 6
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154 // <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
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155 // <0=> Pclk = Cclk / 4
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156 // <1=> Pclk = Cclk
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157 // <2=> Pclk = Cclk / 2
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158 // <3=> Pclk = Hclk / 6
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159 // <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
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160 // <0=> Pclk = Cclk / 4
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161 // <1=> Pclk = Cclk
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162 // <2=> Pclk = Cclk / 2
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163 // <3=> Pclk = Hclk / 6
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166 // <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
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167 // <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
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168 // <0=> Pclk = Cclk / 4
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169 // <1=> Pclk = Cclk
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170 // <2=> Pclk = Cclk / 2
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171 // <3=> Pclk = Hclk / 8
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172 // <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
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173 // <0=> Pclk = Cclk / 4
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174 // <1=> Pclk = Cclk
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175 // <2=> Pclk = Cclk / 2
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176 // <3=> Pclk = Hclk / 8
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177 // <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
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178 // <0=> Pclk = Cclk / 4
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179 // <1=> Pclk = Cclk
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180 // <2=> Pclk = Cclk / 2
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181 // <3=> Pclk = Hclk / 8
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182 // <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
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183 // <0=> Pclk = Cclk / 4
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184 // <1=> Pclk = Cclk
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185 // <2=> Pclk = Cclk / 2
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186 // <3=> Pclk = Hclk / 8
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187 // <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
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188 // <0=> Pclk = Cclk / 4
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189 // <1=> Pclk = Cclk
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190 // <2=> Pclk = Cclk / 2
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191 // <3=> Pclk = Hclk / 8
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192 // <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
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193 // <0=> Pclk = Cclk / 4
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194 // <1=> Pclk = Cclk
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195 // <2=> Pclk = Cclk / 2
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196 // <3=> Pclk = Hclk / 8
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197 // <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
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198 // <0=> Pclk = Cclk / 4
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199 // <1=> Pclk = Cclk
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200 // <2=> Pclk = Cclk / 2
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201 // <3=> Pclk = Hclk / 8
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202 // <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
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203 // <0=> Pclk = Cclk / 4
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204 // <1=> Pclk = Cclk
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205 // <2=> Pclk = Cclk / 2
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206 // <3=> Pclk = Hclk / 8
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207 // <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
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208 // <0=> Pclk = Cclk / 4
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209 // <1=> Pclk = Cclk
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210 // <2=> Pclk = Cclk / 2
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211 // <3=> Pclk = Hclk / 8
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212 // <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
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213 // <0=> Pclk = Cclk / 4
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214 // <1=> Pclk = Cclk
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215 // <2=> Pclk = Cclk / 2
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216 // <3=> Pclk = Hclk / 8
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217 // <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
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218 // <0=> Pclk = Cclk / 4
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219 // <1=> Pclk = Cclk
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220 // <2=> Pclk = Cclk / 2
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221 // <3=> Pclk = Hclk / 8
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222 // <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
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223 // <0=> Pclk = Cclk / 4
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224 // <1=> Pclk = Cclk
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225 // <2=> Pclk = Cclk / 2
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226 // <3=> Pclk = Hclk / 8
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227 // <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
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228 // <0=> Pclk = Cclk / 4
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229 // <1=> Pclk = Cclk
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230 // <2=> Pclk = Cclk / 2
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231 // <3=> Pclk = Hclk / 8
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232 // <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
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233 // <0=> Pclk = Cclk / 4
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234 // <1=> Pclk = Cclk
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235 // <2=> Pclk = Cclk / 2
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236 // <3=> Pclk = Hclk / 8
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239 // <h> Power Control for Peripherals Register (PCONP)
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240 // <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
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241 // <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
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242 // <o11.3> PCUART0: UART 0 power/clock enable
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243 // <o11.4> PCUART1: UART 1 power/clock enable
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244 // <o11.6> PCPWM1: PWM 1 power/clock enable
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245 // <o11.7> PCI2C0: I2C interface 0 power/clock enable
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246 // <o11.8> PCSPI: SPI interface power/clock enable
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247 // <o11.9> PCRTC: RTC power/clock enable
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248 // <o11.10> PCSSP1: SSP interface 1 power/clock enable
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249 // <o11.12> PCAD: A/D converter power/clock enable
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250 // <o11.13> PCCAN1: CAN controller 1 power/clock enable
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251 // <o11.14> PCCAN2: CAN controller 2 power/clock enable
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252 // <o11.15> PCGPIO: GPIOs power/clock enable
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253 // <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
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254 // <o11.17> PCMC: Motor control PWM power/clock enable
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255 // <o11.18> PCQEI: Quadrature encoder interface power/clock enable
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256 // <o11.19> PCI2C1: I2C interface 1 power/clock enable
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257 // <o11.21> PCSSP0: SSP interface 0 power/clock enable
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258 // <o11.22> PCTIM2: Timer 2 power/clock enable
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259 // <o11.23> PCTIM3: Timer 3 power/clock enable
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260 // <o11.24> PCUART2: UART 2 power/clock enable
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261 // <o11.25> PCUART3: UART 3 power/clock enable
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262 // <o11.26> PCI2C2: I2C interface 2 power/clock enable
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263 // <o11.27> PCI2S: I2S interface power/clock enable
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264 // <o11.29> PCGPDMA: GP DMA function power/clock enable
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265 // <o11.30> PCENET: Ethernet block power/clock enable
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266 // <o11.31> PCUSB: USB interface power/clock enable
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269 // <h> Clock Output Configuration Register (CLKOUTCFG)
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270 // <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
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272 // <1=> Main oscillator
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273 // <2=> Internal RC oscillator
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275 // <4=> RTC oscillator
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276 // <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
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278 // <o12.8> CLKOUT_EN: CLKOUT enable control
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283 #define CLOCK_SETUP 1
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284 #define SCS_Val 0x00000020
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285 #define CLKSRCSEL_Val 0x00000001
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286 #define PLL0_SETUP 1
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287 #define PLL0CFG_Val 0x00050063
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288 #define PLL1_SETUP 1
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289 #define PLL1CFG_Val 0x00000023
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290 #define CCLKCFG_Val 0x00000003
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291 #define USBCLKCFG_Val 0x00000000
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292 #define PCLKSEL0_Val 0x00000000
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293 #define PCLKSEL1_Val 0x00000000
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294 #define PCONP_Val 0x042887DE
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295 #define CLKOUTCFG_Val 0x00000000
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298 /*--------------------- Flash Accelerator Configuration ----------------------
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300 // <e> Flash Accelerator Configuration
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301 // <o1.0..11> Reserved
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302 // <o1.12..15> FLASHTIM: Flash Access Time
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303 // <0=> 1 CPU clock (for CPU clock up to 20 MHz)
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304 // <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
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305 // <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
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306 // <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
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307 // <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
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308 // <5=> 6 CPU clocks (for any CPU clock)
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311 #define FLASH_SETUP 1
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312 #define FLASHCFG_Val 0x0000303A
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315 //-------- <<< end of configuration section >>> ------------------------------
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318 /*----------------------------------------------------------------------------
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319 Check the register settings
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320 *----------------------------------------------------------------------------*/
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321 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
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322 #define CHECK_RSVD(val, mask) (val & mask)
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324 /* Clock Configuration -------------------------------------------------------*/
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325 #if (CHECK_RSVD((SCS_Val), ~0x00000030))
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326 #error "SCS: Invalid values of reserved bits!"
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329 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
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330 #error "CLKSRCSEL: Value out of range!"
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333 #if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
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334 #error "PLL0CFG: Invalid values of reserved bits!"
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337 #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
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338 #error "PLL1CFG: Invalid values of reserved bits!"
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341 #if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
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342 #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
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345 #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
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346 #error "USBCLKCFG: Invalid values of reserved bits!"
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349 #if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
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350 #error "PCLKSEL0: Invalid values of reserved bits!"
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353 #if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
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354 #error "PCLKSEL1: Invalid values of reserved bits!"
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357 #if (CHECK_RSVD((PCONP_Val), 0x10100821))
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358 #error "PCONP: Invalid values of reserved bits!"
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361 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
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362 #error "CLKOUTCFG: Invalid values of reserved bits!"
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365 /* Flash Accelerator Configuration -------------------------------------------*/
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366 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
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367 #error "FLASHCFG: Invalid values of reserved bits!"
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371 /*----------------------------------------------------------------------------
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373 *----------------------------------------------------------------------------*/
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375 /*----------------------------------------------------------------------------
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377 *----------------------------------------------------------------------------*/
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378 #define XTAL (12000000UL) /* Oscillator frequency */
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379 #define OSC_CLK ( XTAL) /* Main oscillator frequency */
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380 #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
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381 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
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384 /* F_cco0 = (2 * M * F_in) / N */
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385 #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
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386 #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
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387 #define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)
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388 #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
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390 /* Determine core clock frequency according to settings */
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392 #if ((CLKSRCSEL_Val & 0x03) == 1)
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393 #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
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394 #elif ((CLKSRCSEL_Val & 0x03) == 2)
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395 #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
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397 #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
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400 #if ((CLKSRCSEL_Val & 0x03) == 1)
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401 #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
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402 #elif ((CLKSRCSEL_Val & 0x03) == 2)
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403 #define __CORE_CLK (RTC_CLK / __CCLK_DIV)
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405 #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
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410 /*----------------------------------------------------------------------------
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411 Clock Variable definitions
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412 *----------------------------------------------------------------------------*/
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413 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
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416 /*----------------------------------------------------------------------------
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418 *----------------------------------------------------------------------------*/
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419 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
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421 /* Determine clock frequency according to clock register values */
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422 if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
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423 switch (LPC_SC->CLKSRCSEL & 0x03) {
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424 case 0: /* Int. RC oscillator => PLL0 */
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425 case 3: /* Reserved, default to Int. RC */
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426 SystemCoreClock = (IRC_OSC *
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427 ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
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428 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
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429 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
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431 case 1: /* Main oscillator => PLL0 */
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432 SystemCoreClock = (OSC_CLK *
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433 ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
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434 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
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435 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
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437 case 2: /* RTC oscillator => PLL0 */
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438 SystemCoreClock = (RTC_CLK *
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439 ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
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440 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
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441 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
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445 switch (LPC_SC->CLKSRCSEL & 0x03) {
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446 case 0: /* Int. RC oscillator => PLL0 */
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447 case 3: /* Reserved, default to Int. RC */
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448 SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
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450 case 1: /* Main oscillator => PLL0 */
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451 SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
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453 case 2: /* RTC oscillator => PLL0 */
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454 SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
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460 /* Exported types --------------------------------------------------------------*/
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461 /* Exported constants --------------------------------------------------------*/
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462 //extern unsigned long _sidata; /* start address for the initialization values of the .data section. defined in linker script */
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463 //extern unsigned long _sdata; /* start address for the .data section. defined in linker script */
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464 //extern unsigned long _edata; /* end address for the .data section. defined in linker script */
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466 //extern unsigned long _sbss; /* start address for the .bss section. defined in linker script */
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467 //extern unsigned long _ebss; /* end address for the .bss section. defined in linker script */
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471 // unsigned long *pulSrc, *pulDest;
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474 // // Copy the data segment initializers from flash to SRAM in ROM mode
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476 //#if (__RAM_MODE__==0)
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477 // pulSrc = &_sidata;
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478 // for(pulDest = &_sdata; pulDest < &_edata; )
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480 // *(pulDest++) = *(pulSrc++);
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486 // // Zero fill the bss segment.
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488 // for(pulDest = &_sbss; pulDest < &_ebss; )
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490 // *(pulDest++) = 0;
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495 * Initialize the system
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500 * @brief Setup the microcontroller system.
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501 * Initialize the System.
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503 void SystemInit (void)
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506 #if (CLOCK_SETUP) /* Clock Setup */
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507 LPC_SC->SCS = SCS_Val;
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508 if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
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509 while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
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512 LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
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513 LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
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514 LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
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517 LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
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519 LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */
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520 LPC_SC->PLL0FEED = 0xAA;
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521 LPC_SC->PLL0FEED = 0x55;
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523 LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
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524 LPC_SC->PLL0FEED = 0xAA;
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525 LPC_SC->PLL0FEED = 0x55;
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526 while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
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528 LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
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529 LPC_SC->PLL0FEED = 0xAA;
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530 LPC_SC->PLL0FEED = 0x55;
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531 while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */
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535 LPC_SC->PLL1CFG = PLL1CFG_Val;
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536 LPC_SC->PLL1FEED = 0xAA;
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537 LPC_SC->PLL1FEED = 0x55;
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539 LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
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540 LPC_SC->PLL1FEED = 0xAA;
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541 LPC_SC->PLL1FEED = 0x55;
\r
542 while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
\r
544 LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
\r
545 LPC_SC->PLL1FEED = 0xAA;
\r
546 LPC_SC->PLL1FEED = 0x55;
\r
547 while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
\r
549 LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
\r
551 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
\r
553 LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
\r
556 #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
\r
557 LPC_SC->FLASHCFG = FLASHCFG_Val;
\r