1 /******************************************************************************
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3 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
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4 * NXP LPC17xx Device Series
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6 * @date: 14th May 2009
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7 *----------------------------------------------------------------------------
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9 * Copyright (C) 2008 ARM Limited. All rights reserved.
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11 * ARM Limited (ARM) is supplying this software for use with Cortex-M3
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12 * processor based microcontrollers. This file can be freely distributed
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13 * within development tools that are supporting such ARM based processors.
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15 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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16 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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18 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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19 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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21 ******************************************************************************/
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24 #ifndef __LPC17xx_H__
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25 #define __LPC17xx_H__
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28 * ==========================================================================
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29 * ---------- Interrupt Number Definition -----------------------------------
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30 * ==========================================================================
\r
35 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
\r
36 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
\r
37 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
\r
38 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
\r
39 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
\r
40 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
\r
41 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
\r
42 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
\r
43 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
\r
45 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
\r
46 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
\r
47 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
\r
48 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
\r
49 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
\r
50 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
\r
51 UART0_IRQn = 5, /*!< UART0 Interrupt */
\r
52 UART1_IRQn = 6, /*!< UART1 Interrupt */
\r
53 UART2_IRQn = 7, /*!< UART2 Interrupt */
\r
54 UART3_IRQn = 8, /*!< UART3 Interrupt */
\r
55 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
\r
56 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
\r
57 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
\r
58 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
\r
59 SPI_IRQn = 13, /*!< SPI Interrupt */
\r
60 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
\r
61 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
\r
62 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
\r
63 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
\r
64 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
\r
65 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
\r
66 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
\r
67 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
\r
68 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
\r
69 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
\r
70 USB_IRQn = 24, /*!< USB Interrupt */
\r
71 CAN_IRQn = 25, /*!< CAN Interrupt */
\r
72 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
\r
73 I2S_IRQn = 27, /*!< I2S Interrupt */
\r
74 ENET_IRQn = 28, /*!< Ethernet Interrupt */
\r
75 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
\r
76 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
\r
77 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
\r
78 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
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83 * ==========================================================================
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84 * ----------- Processor and Core Peripheral Section ------------------------
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85 * ==========================================================================
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88 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
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89 #define __MPU_PRESENT 1 /*!< MPU present or not */
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90 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
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91 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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94 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
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95 #include "system_LPC17xx.h" /* System Header */
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100 * Initialize the system clock
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105 * @brief Setup the microcontroller system.
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106 * Initialize the System and update the SystemFrequency variable.
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108 extern void SystemInit (void);
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111 /******************************************************************************/
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112 /* Device Specific Peripheral registers structures */
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113 /******************************************************************************/
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115 #pragma anon_unions
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117 /*------------- System Control (SC) ------------------------------------------*/
\r
120 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
\r
121 uint32_t RESERVED0[31];
\r
122 __IO uint32_t PLL0CON; /* Clocking and Power Control */
\r
123 __IO uint32_t PLL0CFG;
\r
124 __I uint32_t PLL0STAT;
\r
125 __O uint32_t PLL0FEED;
\r
126 uint32_t RESERVED1[4];
\r
127 __IO uint32_t PLL1CON;
\r
128 __IO uint32_t PLL1CFG;
\r
129 __I uint32_t PLL1STAT;
\r
130 __O uint32_t PLL1FEED;
\r
131 uint32_t RESERVED2[4];
\r
132 __IO uint32_t PCON;
\r
133 __IO uint32_t PCONP;
\r
134 uint32_t RESERVED3[15];
\r
135 __IO uint32_t CCLKCFG;
\r
136 __IO uint32_t USBCLKCFG;
\r
137 __IO uint32_t CLKSRCSEL;
\r
138 uint32_t RESERVED4[12];
\r
139 __IO uint32_t EXTINT; /* External Interrupts */
\r
140 uint32_t RESERVED5;
\r
141 __IO uint32_t EXTMODE;
\r
142 __IO uint32_t EXTPOLAR;
\r
143 uint32_t RESERVED6[12];
\r
144 __IO uint32_t RSID; /* Reset */
\r
145 uint32_t RESERVED7[7];
\r
146 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
\r
147 __IO uint32_t IRCTRIM; /* Clock Dividers */
\r
148 __IO uint32_t PCLKSEL0;
\r
149 __IO uint32_t PCLKSEL1;
\r
150 uint32_t RESERVED8[4];
\r
151 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
\r
152 uint32_t RESERVED9;
\r
153 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
\r
156 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
\r
159 __IO uint32_t PINSEL0;
\r
160 __IO uint32_t PINSEL1;
\r
161 __IO uint32_t PINSEL2;
\r
162 __IO uint32_t PINSEL3;
\r
163 __IO uint32_t PINSEL4;
\r
164 __IO uint32_t PINSEL5;
\r
165 __IO uint32_t PINSEL6;
\r
166 __IO uint32_t PINSEL7;
\r
167 __IO uint32_t PINSEL8;
\r
168 __IO uint32_t PINSEL9;
\r
169 __IO uint32_t PINSEL10;
\r
170 uint32_t RESERVED0[5];
\r
171 __IO uint32_t PINMODE0;
\r
172 __IO uint32_t PINMODE1;
\r
173 __IO uint32_t PINMODE2;
\r
174 __IO uint32_t PINMODE3;
\r
175 __IO uint32_t PINMODE4;
\r
176 __IO uint32_t PINMODE5;
\r
177 __IO uint32_t PINMODE6;
\r
178 __IO uint32_t PINMODE7;
\r
179 __IO uint32_t PINMODE8;
\r
180 __IO uint32_t PINMODE9;
\r
181 __IO uint32_t PINMODE_OD0;
\r
182 __IO uint32_t PINMODE_OD1;
\r
183 __IO uint32_t PINMODE_OD2;
\r
184 __IO uint32_t PINMODE_OD3;
\r
185 __IO uint32_t PINMODE_OD4;
\r
188 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
\r
191 __IO uint32_t FIODIR;
\r
192 uint32_t RESERVED0[3];
\r
193 __IO uint32_t FIOMASK;
\r
194 __IO uint32_t FIOPIN;
\r
195 __IO uint32_t FIOSET;
\r
196 __O uint32_t FIOCLR;
\r
201 __I uint32_t IntStatus;
\r
202 __I uint32_t IO0IntStatR;
\r
203 __I uint32_t IO0IntStatF;
\r
204 __O uint32_t IO0IntClr;
\r
205 __IO uint32_t IO0IntEnR;
\r
206 __IO uint32_t IO0IntEnF;
\r
207 uint32_t RESERVED0[3];
\r
208 __I uint32_t IO2IntStatR;
\r
209 __I uint32_t IO2IntStatF;
\r
210 __O uint32_t IO2IntClr;
\r
211 __IO uint32_t IO2IntEnR;
\r
212 __IO uint32_t IO2IntEnF;
\r
215 /*------------- Timer (TIM) --------------------------------------------------*/
\r
231 uint32_t RESERVED0[2];
\r
233 uint32_t RESERVED1[24];
\r
234 __IO uint32_t CTCR;
\r
237 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
\r
260 uint32_t RESERVED0[7];
\r
261 __IO uint32_t CTCR;
\r
264 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
\r
271 uint32_t RESERVED0;
\r
282 uint8_t RESERVED1[7];
\r
284 uint8_t RESERVED2[7];
\r
286 uint8_t RESERVED3[3];
\r
289 uint8_t RESERVED4[3];
\r
291 uint8_t RESERVED5[7];
\r
293 uint8_t RESERVED6[27];
\r
294 __IO uint8_t RS485CTRL;
\r
295 uint8_t RESERVED7[3];
\r
296 __IO uint8_t ADRMATCH;
\r
305 uint32_t RESERVED0;
\r
316 uint8_t RESERVED1[3];
\r
318 uint8_t RESERVED2[3];
\r
320 uint8_t RESERVED3[3];
\r
322 uint8_t RESERVED4[3];
\r
324 uint8_t RESERVED5[3];
\r
326 uint32_t RESERVED6;
\r
328 uint32_t RESERVED7;
\r
330 uint8_t RESERVED8[27];
\r
331 __IO uint8_t RS485CTRL;
\r
332 uint8_t RESERVED9[3];
\r
333 __IO uint8_t ADRMATCH;
\r
334 uint8_t RESERVED10[3];
\r
335 __IO uint8_t RS485DLY;
\r
338 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
\r
341 __IO uint32_t SPCR;
\r
343 __IO uint32_t SPDR;
\r
344 __IO uint32_t SPCCR;
\r
345 uint32_t RESERVED0[3];
\r
346 __IO uint32_t SPINT;
\r
349 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
\r
356 __IO uint32_t CPSR;
\r
357 __IO uint32_t IMSC;
\r
361 __IO uint32_t DMACR;
\r
364 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
\r
367 __IO uint32_t I2CONSET;
\r
368 __I uint32_t I2STAT;
\r
369 __IO uint32_t I2DAT;
\r
370 __IO uint32_t I2ADR0;
\r
371 __IO uint32_t I2SCLH;
\r
372 __IO uint32_t I2SCLL;
\r
373 __O uint32_t I2CONCLR;
\r
374 __IO uint32_t MMCTRL;
\r
375 __IO uint32_t I2ADR1;
\r
376 __IO uint32_t I2ADR2;
\r
377 __IO uint32_t I2ADR3;
\r
378 __I uint32_t I2DATA_BUFFER;
\r
379 __IO uint32_t I2MASK0;
\r
380 __IO uint32_t I2MASK1;
\r
381 __IO uint32_t I2MASK2;
\r
382 __IO uint32_t I2MASK3;
\r
385 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
\r
388 __IO uint32_t I2SDAO;
\r
389 __I uint32_t I2SDAI;
\r
390 __O uint32_t I2STXFIFO;
\r
391 __I uint32_t I2SRXFIFO;
\r
392 __I uint32_t I2SSTATE;
\r
393 __IO uint32_t I2SDMA1;
\r
394 __IO uint32_t I2SDMA2;
\r
395 __IO uint32_t I2SIRQ;
\r
396 __IO uint32_t I2STXRATE;
\r
397 __IO uint32_t I2SRXRATE;
\r
398 __IO uint32_t I2STXBITRATE;
\r
399 __IO uint32_t I2SRXBITRATE;
\r
400 __IO uint32_t I2STXMODE;
\r
401 __IO uint32_t I2SRXMODE;
\r
404 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
\r
407 __IO uint32_t RICOMPVAL;
\r
408 __IO uint32_t RIMASK;
\r
409 __IO uint8_t RICTRL;
\r
410 uint8_t RESERVED0[3];
\r
411 __IO uint32_t RICOUNTER;
\r
414 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
\r
418 uint8_t RESERVED0[3];
\r
420 uint8_t RESERVED1[3];
\r
422 uint8_t RESERVED2[3];
\r
424 uint8_t RESERVED3[3];
\r
425 __I uint32_t CTIME0;
\r
426 __I uint32_t CTIME1;
\r
427 __I uint32_t CTIME2;
\r
429 uint8_t RESERVED4[3];
\r
431 uint8_t RESERVED5[3];
\r
433 uint8_t RESERVED6[3];
\r
435 uint8_t RESERVED7[3];
\r
437 uint8_t RESERVED8[3];
\r
439 uint16_t RESERVED9;
\r
440 __IO uint8_t MONTH;
\r
441 uint8_t RESERVED10[3];
\r
442 __IO uint16_t YEAR;
\r
443 uint16_t RESERVED11;
\r
444 __IO uint32_t CALIBRATION;
\r
445 __IO uint32_t GPREG0;
\r
446 __IO uint32_t GPREG1;
\r
447 __IO uint32_t GPREG2;
\r
448 __IO uint32_t GPREG3;
\r
449 __IO uint32_t GPREG4;
\r
450 __IO uint8_t WAKEUPDIS;
\r
451 uint8_t RESERVED12[3];
\r
452 __IO uint8_t PWRCTRL;
\r
453 uint8_t RESERVED13[3];
\r
454 __IO uint8_t ALSEC;
\r
455 uint8_t RESERVED14[3];
\r
456 __IO uint8_t ALMIN;
\r
457 uint8_t RESERVED15[3];
\r
458 __IO uint8_t ALHOUR;
\r
459 uint8_t RESERVED16[3];
\r
460 __IO uint8_t ALDOM;
\r
461 uint8_t RESERVED17[3];
\r
462 __IO uint8_t ALDOW;
\r
463 uint8_t RESERVED18[3];
\r
464 __IO uint16_t ALDOY;
\r
465 uint16_t RESERVED19;
\r
466 __IO uint8_t ALMON;
\r
467 uint8_t RESERVED20[3];
\r
468 __IO uint16_t ALYEAR;
\r
469 uint16_t RESERVED21;
\r
472 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
\r
475 __IO uint8_t WDMOD;
\r
476 uint8_t RESERVED0[3];
\r
477 __IO uint32_t WDTC;
\r
478 __O uint8_t WDFEED;
\r
479 uint8_t RESERVED1[3];
\r
481 __IO uint32_t WDCLKSEL;
\r
484 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
\r
487 __IO uint32_t ADCR;
\r
488 __IO uint32_t ADGDR;
\r
489 uint32_t RESERVED0;
\r
490 __IO uint32_t ADINTEN;
\r
491 __I uint32_t ADDR0;
\r
492 __I uint32_t ADDR1;
\r
493 __I uint32_t ADDR2;
\r
494 __I uint32_t ADDR3;
\r
495 __I uint32_t ADDR4;
\r
496 __I uint32_t ADDR5;
\r
497 __I uint32_t ADDR6;
\r
498 __I uint32_t ADDR7;
\r
499 __I uint32_t ADSTAT;
\r
500 __IO uint32_t ADTRM;
\r
503 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
\r
506 __IO uint32_t DACR;
\r
507 __IO uint32_t DACCTRL;
\r
508 __IO uint16_t DACCNTVAL;
\r
511 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
\r
514 __I uint32_t MCCON;
\r
515 __O uint32_t MCCON_SET;
\r
516 __O uint32_t MCCON_CLR;
\r
517 __I uint32_t MCCAPCON;
\r
518 __O uint32_t MCCAPCON_SET;
\r
519 __O uint32_t MCCAPCON_CLR;
\r
520 __IO uint32_t MCTIM0;
\r
521 __IO uint32_t MCTIM1;
\r
522 __IO uint32_t MCTIM2;
\r
523 __IO uint32_t MCPER0;
\r
524 __IO uint32_t MCPER1;
\r
525 __IO uint32_t MCPER2;
\r
526 __IO uint32_t MCPW0;
\r
527 __IO uint32_t MCPW1;
\r
528 __IO uint32_t MCPW2;
\r
529 __IO uint32_t MCDEADTIME;
\r
530 __IO uint32_t MCCCP;
\r
531 __IO uint32_t MCCR0;
\r
532 __IO uint32_t MCCR1;
\r
533 __IO uint32_t MCCR2;
\r
534 __I uint32_t MCINTEN;
\r
535 __O uint32_t MCINTEN_SET;
\r
536 __O uint32_t MCINTEN_CLR;
\r
537 __I uint32_t MCCNTCON;
\r
538 __O uint32_t MCCNTCON_SET;
\r
539 __O uint32_t MCCNTCON_CLR;
\r
540 __I uint32_t MCINTFLAG;
\r
541 __O uint32_t MCINTFLAG_SET;
\r
542 __O uint32_t MCINTFLAG_CLR;
\r
543 __O uint32_t MCCAP_CLR;
\r
546 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
\r
549 __O uint32_t QEICON;
\r
550 __I uint32_t QEISTAT;
\r
551 __IO uint32_t QEICONF;
\r
552 __I uint32_t QEIPOS;
\r
553 __IO uint32_t QEIMAXPOS;
\r
554 __IO uint32_t CMPOS0;
\r
555 __IO uint32_t CMPOS1;
\r
556 __IO uint32_t CMPOS2;
\r
557 __I uint32_t INXCNT;
\r
558 __IO uint32_t INXCMP;
\r
559 __IO uint32_t QEILOAD;
\r
560 __I uint32_t QEITIME;
\r
561 __I uint32_t QEIVEL;
\r
562 __I uint32_t QEICAP;
\r
563 __IO uint32_t VELCOMP;
\r
564 __IO uint32_t FILTER;
\r
565 uint32_t RESERVED0[998];
\r
566 __O uint32_t QEIIEC;
\r
567 __O uint32_t QEIIES;
\r
568 __I uint32_t QEIINTSTAT;
\r
569 __I uint32_t QEIIE;
\r
570 __O uint32_t QEICLR;
\r
571 __O uint32_t QEISET;
\r
574 /*------------- Controller Area Network (CAN) --------------------------------*/
\r
577 __IO uint32_t mask[512]; /* ID Masks */
\r
578 } CANAF_RAM_TypeDef;
\r
580 typedef struct /* Acceptance Filter Registers */
\r
582 __IO uint32_t AFMR;
\r
583 __IO uint32_t SFF_sa;
\r
584 __IO uint32_t SFF_GRP_sa;
\r
585 __IO uint32_t EFF_sa;
\r
586 __IO uint32_t EFF_GRP_sa;
\r
587 __IO uint32_t ENDofTable;
\r
588 __I uint32_t LUTerrAd;
\r
589 __I uint32_t LUTerr;
\r
592 typedef struct /* Central Registers */
\r
594 __I uint32_t CANTxSR;
\r
595 __I uint32_t CANRxSR;
\r
596 __I uint32_t CANMSR;
\r
599 typedef struct /* Controller Registers */
\r
613 __IO uint32_t TFI1;
\r
614 __IO uint32_t TID1;
\r
615 __IO uint32_t TDA1;
\r
616 __IO uint32_t TDB1;
\r
617 __IO uint32_t TFI2;
\r
618 __IO uint32_t TID2;
\r
619 __IO uint32_t TDA2;
\r
620 __IO uint32_t TDB2;
\r
621 __IO uint32_t TFI3;
\r
622 __IO uint32_t TID3;
\r
623 __IO uint32_t TDA3;
\r
624 __IO uint32_t TDB3;
\r
627 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
\r
628 typedef struct /* Common Registers */
\r
630 __I uint32_t DMACIntStat;
\r
631 __I uint32_t DMACIntTCStat;
\r
632 __O uint32_t DMACIntTCClear;
\r
633 __I uint32_t DMACIntErrStat;
\r
634 __O uint32_t DMACIntErrClr;
\r
635 __I uint32_t DMACRawIntTCStat;
\r
636 __I uint32_t DMACRawIntErrStat;
\r
637 __I uint32_t DMACEnbldChns;
\r
638 __IO uint32_t DMACSoftBReq;
\r
639 __IO uint32_t DMACSoftSReq;
\r
640 __IO uint32_t DMACSoftLBReq;
\r
641 __IO uint32_t DMACSoftLSReq;
\r
642 __IO uint32_t DMACConfig;
\r
643 __IO uint32_t DMACSync;
\r
646 typedef struct /* Channel Registers */
\r
648 __IO uint32_t DMACCSrcAddr;
\r
649 __IO uint32_t DMACCDestAddr;
\r
650 __IO uint32_t DMACCLLI;
\r
651 __IO uint32_t DMACCControl;
\r
652 __IO uint32_t DMACCConfig;
\r
655 /*------------- Universal Serial Bus (USB) -----------------------------------*/
\r
658 __I uint32_t HcRevision; /* USB Host Registers */
\r
659 __IO uint32_t HcControl;
\r
660 __IO uint32_t HcCommandStatus;
\r
661 __IO uint32_t HcInterruptStatus;
\r
662 __IO uint32_t HcInterruptEnable;
\r
663 __IO uint32_t HcInterruptDisable;
\r
664 __IO uint32_t HcHCCA;
\r
665 __I uint32_t HcPeriodCurrentED;
\r
666 __IO uint32_t HcControlHeadED;
\r
667 __IO uint32_t HcControlCurrentED;
\r
668 __IO uint32_t HcBulkHeadED;
\r
669 __IO uint32_t HcBulkCurrentED;
\r
670 __I uint32_t HcDoneHead;
\r
671 __IO uint32_t HcFmInterval;
\r
672 __I uint32_t HcFmRemaining;
\r
673 __I uint32_t HcFmNumber;
\r
674 __IO uint32_t HcPeriodicStart;
\r
675 __IO uint32_t HcLSTreshold;
\r
676 __IO uint32_t HcRhDescriptorA;
\r
677 __IO uint32_t HcRhDescriptorB;
\r
678 __IO uint32_t HcRhStatus;
\r
679 __IO uint32_t HcRhPortStatus1;
\r
680 __IO uint32_t HcRhPortStatus2;
\r
681 uint32_t RESERVED0[40];
\r
682 __I uint32_t Module_ID;
\r
684 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
\r
685 __IO uint32_t OTGIntEn;
\r
686 __O uint32_t OTGIntSet;
\r
687 __O uint32_t OTGIntClr;
\r
688 __IO uint32_t OTGStCtrl;
\r
689 __IO uint32_t OTGTmr;
\r
690 uint32_t RESERVED1[58];
\r
692 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
\r
693 __IO uint32_t USBDevIntEn;
\r
694 __O uint32_t USBDevIntClr;
\r
695 __O uint32_t USBDevIntSet;
\r
697 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
\r
698 __I uint32_t USBCmdData;
\r
700 __I uint32_t USBRxData; /* USB Device Transfer Registers */
\r
701 __O uint32_t USBTxData;
\r
702 __I uint32_t USBRxPLen;
\r
703 __O uint32_t USBTxPLen;
\r
704 __IO uint32_t USBCtrl;
\r
705 __O uint32_t USBDevIntPri;
\r
707 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
\r
708 __IO uint32_t USBEpIntEn;
\r
709 __O uint32_t USBEpIntClr;
\r
710 __O uint32_t USBEpIntSet;
\r
711 __O uint32_t USBEpIntPri;
\r
713 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
\r
714 __O uint32_t USBEpInd;
\r
715 __IO uint32_t USBMaxPSize;
\r
717 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
\r
718 __O uint32_t USBDMARClr;
\r
719 __O uint32_t USBDMARSet;
\r
720 uint32_t RESERVED2[9];
\r
721 __IO uint32_t USBUDCAH;
\r
722 __I uint32_t USBEpDMASt;
\r
723 __O uint32_t USBEpDMAEn;
\r
724 __O uint32_t USBEpDMADis;
\r
725 __I uint32_t USBDMAIntSt;
\r
726 __IO uint32_t USBDMAIntEn;
\r
727 uint32_t RESERVED3[2];
\r
728 __I uint32_t USBEoTIntSt;
\r
729 __O uint32_t USBEoTIntClr;
\r
730 __O uint32_t USBEoTIntSet;
\r
731 __I uint32_t USBNDDRIntSt;
\r
732 __O uint32_t USBNDDRIntClr;
\r
733 __O uint32_t USBNDDRIntSet;
\r
734 __I uint32_t USBSysErrIntSt;
\r
735 __O uint32_t USBSysErrIntClr;
\r
736 __O uint32_t USBSysErrIntSet;
\r
737 uint32_t RESERVED4[15];
\r
739 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
\r
740 __O uint32_t I2C_WO;
\r
741 __I uint32_t I2C_STS;
\r
742 __IO uint32_t I2C_CTL;
\r
743 __IO uint32_t I2C_CLKHI;
\r
744 __O uint32_t I2C_CLKLO;
\r
745 uint32_t RESERVED5[823];
\r
748 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
\r
749 __IO uint32_t OTGClkCtrl;
\r
752 __I uint32_t USBClkSt;
\r
753 __I uint32_t OTGClkSt;
\r
757 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
\r
760 __IO uint32_t MAC1; /* MAC Registers */
\r
761 __IO uint32_t MAC2;
\r
762 __IO uint32_t IPGT;
\r
763 __IO uint32_t IPGR;
\r
764 __IO uint32_t CLRT;
\r
765 __IO uint32_t MAXF;
\r
766 __IO uint32_t SUPP;
\r
767 __IO uint32_t TEST;
\r
768 __IO uint32_t MCFG;
\r
769 __IO uint32_t MCMD;
\r
770 __IO uint32_t MADR;
\r
774 uint32_t RESERVED0[2];
\r
778 uint32_t RESERVED1[45];
\r
779 __IO uint32_t Command; /* Control Registers */
\r
780 __I uint32_t Status;
\r
781 __IO uint32_t RxDescriptor;
\r
782 __IO uint32_t RxStatus;
\r
783 __IO uint32_t RxDescriptorNumber;
\r
784 __I uint32_t RxProduceIndex;
\r
785 __IO uint32_t RxConsumeIndex;
\r
786 __IO uint32_t TxDescriptor;
\r
787 __IO uint32_t TxStatus;
\r
788 __IO uint32_t TxDescriptorNumber;
\r
789 __IO uint32_t TxProduceIndex;
\r
790 __I uint32_t TxConsumeIndex;
\r
791 uint32_t RESERVED2[10];
\r
795 uint32_t RESERVED3[3];
\r
796 __IO uint32_t FlowControlCounter;
\r
797 __I uint32_t FlowControlStatus;
\r
798 uint32_t RESERVED4[34];
\r
799 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
\r
800 __IO uint32_t RxFilterWoLStatus;
\r
801 __IO uint32_t RxFilterWoLClear;
\r
802 uint32_t RESERVED5;
\r
803 __IO uint32_t HashFilterL;
\r
804 __IO uint32_t HashFilterH;
\r
805 uint32_t RESERVED6[882];
\r
806 __I uint32_t IntStatus; /* Module Control Registers */
\r
807 __IO uint32_t IntEnable;
\r
808 __O uint32_t IntClear;
\r
809 __O uint32_t IntSet;
\r
810 uint32_t RESERVED7;
\r
811 __IO uint32_t PowerDown;
\r
812 uint32_t RESERVED8;
\r
813 __IO uint32_t Module_ID;
\r
816 #pragma no_anon_unions
\r
819 /******************************************************************************/
\r
820 /* Peripheral memory map */
\r
821 /******************************************************************************/
\r
822 /* Base addresses */
\r
823 #define FLASH_BASE (0x00000000UL)
\r
824 #define RAM_BASE (0x10000000UL)
\r
825 #define GPIO_BASE (0x2009C000UL)
\r
826 #define APB0_BASE (0x40000000UL)
\r
827 #define APB1_BASE (0x40080000UL)
\r
828 #define AHB_BASE (0x50000000UL)
\r
829 #define CM3_BASE (0xE0000000UL)
\r
831 /* APB0 peripherals */
\r
832 #define WDT_BASE (APB0_BASE + 0x00000)
\r
833 #define TIM0_BASE (APB0_BASE + 0x04000)
\r
834 #define TIM1_BASE (APB0_BASE + 0x08000)
\r
835 #define UART0_BASE (APB0_BASE + 0x0C000)
\r
836 #define UART1_BASE (APB0_BASE + 0x10000)
\r
837 #define PWM1_BASE (APB0_BASE + 0x18000)
\r
838 #define I2C0_BASE (APB0_BASE + 0x1C000)
\r
839 #define SPI_BASE (APB0_BASE + 0x20000)
\r
840 #define RTC_BASE (APB0_BASE + 0x24000)
\r
841 #define GPIOINT_BASE (APB0_BASE + 0x28080)
\r
842 #define PINCON_BASE (APB0_BASE + 0x2C000)
\r
843 #define SSP1_BASE (APB0_BASE + 0x30000)
\r
844 #define ADC_BASE (APB0_BASE + 0x34000)
\r
845 #define CANAF_RAM_BASE (APB0_BASE + 0x38000)
\r
846 #define CANAF_BASE (APB0_BASE + 0x3C000)
\r
847 #define CANCR_BASE (APB0_BASE + 0x40000)
\r
848 #define CAN1_BASE (APB0_BASE + 0x44000)
\r
849 #define CAN2_BASE (APB0_BASE + 0x48000)
\r
850 #define I2C1_BASE (APB0_BASE + 0x5C000)
\r
852 /* APB1 peripherals */
\r
853 #define SSP0_BASE (APB1_BASE + 0x08000)
\r
854 #define DAC_BASE (APB1_BASE + 0x0C000)
\r
855 #define TIM2_BASE (APB1_BASE + 0x10000)
\r
856 #define TIM3_BASE (APB1_BASE + 0x14000)
\r
857 #define UART2_BASE (APB1_BASE + 0x18000)
\r
858 #define UART3_BASE (APB1_BASE + 0x1C000)
\r
859 #define I2C2_BASE (APB1_BASE + 0x20000)
\r
860 #define I2S_BASE (APB1_BASE + 0x28000)
\r
861 #define RIT_BASE (APB1_BASE + 0x30000)
\r
862 #define MCPWM_BASE (APB1_BASE + 0x38000)
\r
863 #define QEI_BASE (APB1_BASE + 0x3C000)
\r
864 #define SC_BASE (APB1_BASE + 0x7C000)
\r
866 /* AHB peripherals */
\r
867 #define EMAC_BASE (AHB_BASE + 0x00000)
\r
868 #define GPDMA_BASE (AHB_BASE + 0x04000)
\r
869 #define GPDMACH0_BASE (AHB_BASE + 0x04100)
\r
870 #define GPDMACH1_BASE (AHB_BASE + 0x04120)
\r
871 #define GPDMACH2_BASE (AHB_BASE + 0x04140)
\r
872 #define GPDMACH3_BASE (AHB_BASE + 0x04160)
\r
873 #define GPDMACH4_BASE (AHB_BASE + 0x04180)
\r
874 #define GPDMACH5_BASE (AHB_BASE + 0x041A0)
\r
875 #define GPDMACH6_BASE (AHB_BASE + 0x041C0)
\r
876 #define GPDMACH7_BASE (AHB_BASE + 0x041E0)
\r
877 #define USB_BASE (AHB_BASE + 0x0C000)
\r
880 #define GPIO0_BASE (GPIO_BASE + 0x00000)
\r
881 #define GPIO1_BASE (GPIO_BASE + 0x00020)
\r
882 #define GPIO2_BASE (GPIO_BASE + 0x00040)
\r
883 #define GPIO3_BASE (GPIO_BASE + 0x00060)
\r
884 #define GPIO4_BASE (GPIO_BASE + 0x00080)
\r
887 /******************************************************************************/
\r
888 /* Peripheral declaration */
\r
889 /******************************************************************************/
\r
890 #define SC (( SC_TypeDef *) SC_BASE)
\r
891 #define GPIO0 (( GPIO_TypeDef *) GPIO0_BASE)
\r
892 #define GPIO1 (( GPIO_TypeDef *) GPIO1_BASE)
\r
893 #define GPIO2 (( GPIO_TypeDef *) GPIO2_BASE)
\r
894 #define GPIO3 (( GPIO_TypeDef *) GPIO3_BASE)
\r
895 #define GPIO4 (( GPIO_TypeDef *) GPIO4_BASE)
\r
896 #define WDT (( WDT_TypeDef *) WDT_BASE)
\r
897 #define TIM0 (( TIM_TypeDef *) TIM0_BASE)
\r
898 #define TIM1 (( TIM_TypeDef *) TIM1_BASE)
\r
899 #define TIM2 (( TIM_TypeDef *) TIM2_BASE)
\r
900 #define TIM3 (( TIM_TypeDef *) TIM3_BASE)
\r
901 #define RIT (( RIT_TypeDef *) RIT_BASE)
\r
902 #define UART0 (( UART_TypeDef *) UART0_BASE)
\r
903 #define UART1 (( UART1_TypeDef *) UART1_BASE)
\r
904 #define UART2 (( UART_TypeDef *) UART2_BASE)
\r
905 #define UART3 (( UART_TypeDef *) UART3_BASE)
\r
906 #define PWM1 (( PWM_TypeDef *) PWM1_BASE)
\r
907 #define I2C0 (( I2C_TypeDef *) I2C0_BASE)
\r
908 #define I2C1 (( I2C_TypeDef *) I2C1_BASE)
\r
909 #define I2C2 (( I2C_TypeDef *) I2C2_BASE)
\r
910 #define I2S (( I2S_TypeDef *) I2S_BASE)
\r
911 #define SPI (( SPI_TypeDef *) SPI_BASE)
\r
912 #define RTC (( RTC_TypeDef *) RTC_BASE)
\r
913 #define GPIOINT (( GPIOINT_TypeDef *) GPIOINT_BASE)
\r
914 #define PINCON (( PINCON_TypeDef *) PINCON_BASE)
\r
915 #define SSP0 (( SSP_TypeDef *) SSP0_BASE)
\r
916 #define SSP1 (( SSP_TypeDef *) SSP1_BASE)
\r
917 #define ADC (( ADC_TypeDef *) ADC_BASE)
\r
918 #define DAC (( DAC_TypeDef *) DAC_BASE)
\r
919 #define CANAF_RAM ((CANAF_RAM_TypeDef *) CANAF_RAM_BASE)
\r
920 #define CANAF (( CANAF_TypeDef *) CANAF_BASE)
\r
921 #define CANCR (( CANCR_TypeDef *) CANCR_BASE)
\r
922 #define CAN1 (( CAN_TypeDef *) CAN1_BASE)
\r
923 #define CAN2 (( CAN_TypeDef *) CAN2_BASE)
\r
924 #define MCPWM (( MCPWM_TypeDef *) MCPWM_BASE)
\r
925 #define QEI (( QEI_TypeDef *) QEI_BASE)
\r
926 #define EMAC (( EMAC_TypeDef *) EMAC_BASE)
\r
927 #define GPDMA (( GPDMA_TypeDef *) GPDMA_BASE)
\r
928 #define GPDMACH0 (( GPDMACH_TypeDef *) GPDMACH0_BASE)
\r
929 #define GPDMACH1 (( GPDMACH_TypeDef *) GPDMACH1_BASE)
\r
930 #define GPDMACH2 (( GPDMACH_TypeDef *) GPDMACH2_BASE)
\r
931 #define GPDMACH3 (( GPDMACH_TypeDef *) GPDMACH3_BASE)
\r
932 #define GPDMACH4 (( GPDMACH_TypeDef *) GPDMACH4_BASE)
\r
933 #define GPDMACH5 (( GPDMACH_TypeDef *) GPDMACH5_BASE)
\r
934 #define GPDMACH6 (( GPDMACH_TypeDef *) GPDMACH6_BASE)
\r
935 #define GPDMACH7 (( GPDMACH_TypeDef *) GPDMACH7_BASE)
\r
936 #define USB (( USB_TypeDef *) USB_BASE)
\r
938 #endif // __LPC17xx_H__
\r