1 /******************************************************************************
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2 * @file: system_LPC17xx.c
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3 * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Source File
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4 * for the NXP LPC17xx Device Series
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6 * @date: 18th May 2009
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7 *----------------------------------------------------------------------------
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9 * Copyright (C) 2008 ARM Limited. All rights reserved.
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11 * ARM Limited (ARM) is supplying this software for use with Cortex-M3
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12 * processor based microcontrollers. This file can be freely distributed
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13 * within development tools that are supporting such ARM based processors.
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15 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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16 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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18 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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19 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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21 ******************************************************************************/
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25 #include "LPC17xx.h"
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28 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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31 /*--------------------- Clock Configuration ----------------------------------
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33 // <e> Clock Configuration
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34 // <h> System Controls and Status Register (SCS)
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35 // <o1.4> OSCRANGE: Main Oscillator Range Select
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36 // <0=> 1 MHz to 20 MHz
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37 // <1=> 15 MHz to 24 MHz
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38 // <e1.5> OSCEN: Main Oscillator Enable
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42 // <h> Clock Source Select Register (CLKSRCSEL)
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43 // <o2.0..1> CLKSRC: PLL Clock Source Selection
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44 // <0=> Internal RC oscillator
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45 // <1=> Main oscillator
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46 // <2=> RTC oscillator
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49 // <e3> PLL0 Configuration (Main PLL)
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50 // <h> PLL0 Configuration Register (PLL0CFG)
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51 // <i> F_cco0 = (2 * M * F_in) / N
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52 // <i> F_in must be in the range of 32 kHz to 50 MHz
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53 // <i> F_cco0 must be in the range of 275 MHz to 550 MHz
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54 // <o4.0..14> MSEL: PLL Multiplier Selection
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57 // <o4.16..23> NSEL: PLL Divider Selection
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63 // <e5> PLL1 Configuration (USB PLL)
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64 // <h> PLL1 Configuration Register (PLL1CFG)
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65 // <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
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66 // <i> F_cco1 = F_osc * M * 2 * P
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67 // <i> F_cco1 must be in the range of 156 MHz to 320 MHz
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68 // <o6.0..4> MSEL: PLL Multiplier Selection
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70 // <i> M Value (for USB maximum value is 4)
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71 // <o6.5..6> PSEL: PLL Divider Selection
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80 // <h> CPU Clock Configuration Register (CCLKCFG)
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81 // <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
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85 // <h> USB Clock Configuration Register (USBCLKCFG)
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86 // <o8.0..3> USBSEL: Divide Value for USB Clock from PLL1
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88 // <i> Divide is USBSEL + 1
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91 // <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
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92 // <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
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93 // <0=> Pclk = Cclk / 4
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95 // <2=> Pclk = Cclk / 2
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96 // <3=> Pclk = Hclk / 8
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97 // <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
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98 // <0=> Pclk = Cclk / 4
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100 // <2=> Pclk = Cclk / 2
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101 // <3=> Pclk = Hclk / 8
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102 // <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
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103 // <0=> Pclk = Cclk / 4
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104 // <1=> Pclk = Cclk
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105 // <2=> Pclk = Cclk / 2
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106 // <3=> Pclk = Hclk / 8
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107 // <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
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108 // <0=> Pclk = Cclk / 4
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109 // <1=> Pclk = Cclk
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110 // <2=> Pclk = Cclk / 2
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111 // <3=> Pclk = Hclk / 8
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112 // <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
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113 // <0=> Pclk = Cclk / 4
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114 // <1=> Pclk = Cclk
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115 // <2=> Pclk = Cclk / 2
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116 // <3=> Pclk = Hclk / 8
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117 // <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
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118 // <0=> Pclk = Cclk / 4
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119 // <1=> Pclk = Cclk
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120 // <2=> Pclk = Cclk / 2
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121 // <3=> Pclk = Hclk / 8
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122 // <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
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123 // <0=> Pclk = Cclk / 4
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124 // <1=> Pclk = Cclk
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125 // <2=> Pclk = Cclk / 2
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126 // <3=> Pclk = Hclk / 8
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127 // <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
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128 // <0=> Pclk = Cclk / 4
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129 // <1=> Pclk = Cclk
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130 // <2=> Pclk = Cclk / 2
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131 // <3=> Pclk = Hclk / 8
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132 // <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
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133 // <0=> Pclk = Cclk / 4
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134 // <1=> Pclk = Cclk
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135 // <2=> Pclk = Cclk / 2
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136 // <3=> Pclk = Hclk / 8
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137 // <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
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138 // <0=> Pclk = Cclk / 4
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139 // <1=> Pclk = Cclk
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140 // <2=> Pclk = Cclk / 2
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141 // <3=> Pclk = Hclk / 8
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142 // <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
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143 // <0=> Pclk = Cclk / 4
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144 // <1=> Pclk = Cclk
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145 // <2=> Pclk = Cclk / 2
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146 // <3=> Pclk = Hclk / 8
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147 // <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
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148 // <0=> Pclk = Cclk / 4
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149 // <1=> Pclk = Cclk
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150 // <2=> Pclk = Cclk / 2
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151 // <3=> Pclk = Hclk / 6
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152 // <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
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153 // <0=> Pclk = Cclk / 4
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154 // <1=> Pclk = Cclk
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155 // <2=> Pclk = Cclk / 2
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156 // <3=> Pclk = Hclk / 6
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157 // <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
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158 // <0=> Pclk = Cclk / 4
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159 // <1=> Pclk = Cclk
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160 // <2=> Pclk = Cclk / 2
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161 // <3=> Pclk = Hclk / 6
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164 // <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
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165 // <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
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166 // <0=> Pclk = Cclk / 4
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167 // <1=> Pclk = Cclk
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168 // <2=> Pclk = Cclk / 2
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169 // <3=> Pclk = Hclk / 8
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170 // <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
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171 // <0=> Pclk = Cclk / 4
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172 // <1=> Pclk = Cclk
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173 // <2=> Pclk = Cclk / 2
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174 // <3=> Pclk = Hclk / 8
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175 // <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
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176 // <0=> Pclk = Cclk / 4
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177 // <1=> Pclk = Cclk
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178 // <2=> Pclk = Cclk / 2
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179 // <3=> Pclk = Hclk / 8
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180 // <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
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181 // <0=> Pclk = Cclk / 4
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182 // <1=> Pclk = Cclk
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183 // <2=> Pclk = Cclk / 2
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184 // <3=> Pclk = Hclk / 8
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185 // <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
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186 // <0=> Pclk = Cclk / 4
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187 // <1=> Pclk = Cclk
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188 // <2=> Pclk = Cclk / 2
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189 // <3=> Pclk = Hclk / 8
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190 // <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
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191 // <0=> Pclk = Cclk / 4
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192 // <1=> Pclk = Cclk
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193 // <2=> Pclk = Cclk / 2
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194 // <3=> Pclk = Hclk / 8
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195 // <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
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196 // <0=> Pclk = Cclk / 4
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197 // <1=> Pclk = Cclk
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198 // <2=> Pclk = Cclk / 2
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199 // <3=> Pclk = Hclk / 8
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200 // <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
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201 // <0=> Pclk = Cclk / 4
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202 // <1=> Pclk = Cclk
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203 // <2=> Pclk = Cclk / 2
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204 // <3=> Pclk = Hclk / 8
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205 // <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
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206 // <0=> Pclk = Cclk / 4
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207 // <1=> Pclk = Cclk
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208 // <2=> Pclk = Cclk / 2
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209 // <3=> Pclk = Hclk / 8
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210 // <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
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211 // <0=> Pclk = Cclk / 4
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212 // <1=> Pclk = Cclk
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213 // <2=> Pclk = Cclk / 2
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214 // <3=> Pclk = Hclk / 8
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215 // <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
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216 // <0=> Pclk = Cclk / 4
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217 // <1=> Pclk = Cclk
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218 // <2=> Pclk = Cclk / 2
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219 // <3=> Pclk = Hclk / 8
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220 // <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
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221 // <0=> Pclk = Cclk / 4
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222 // <1=> Pclk = Cclk
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223 // <2=> Pclk = Cclk / 2
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224 // <3=> Pclk = Hclk / 8
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225 // <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
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226 // <0=> Pclk = Cclk / 4
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227 // <1=> Pclk = Cclk
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228 // <2=> Pclk = Cclk / 2
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229 // <3=> Pclk = Hclk / 8
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230 // <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
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231 // <0=> Pclk = Cclk / 4
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232 // <1=> Pclk = Cclk
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233 // <2=> Pclk = Cclk / 2
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234 // <3=> Pclk = Hclk / 8
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237 // <h> Power Control for Peripherals Register (PCONP)
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238 // <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
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239 // <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
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240 // <o11.3> PCUART0: UART 0 power/clock enable
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241 // <o11.4> PCUART1: UART 1 power/clock enable
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242 // <o11.6> PCPWM1: PWM 1 power/clock enable
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243 // <o11.7> PCI2C0: I2C interface 0 power/clock enable
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244 // <o11.8> PCSPI: SPI interface power/clock enable
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245 // <o11.9> PCRTC: RTC power/clock enable
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246 // <o11.10> PCSSP1: SSP interface 1 power/clock enable
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247 // <o11.12> PCAD: A/D converter power/clock enable
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248 // <o11.13> PCCAN1: CAN controller 1 power/clock enable
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249 // <o11.14> PCCAN2: CAN controller 2 power/clock enable
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250 // <o11.15> PCGPIO: GPIOs power/clock enable
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251 // <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
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252 // <o11.17> PCMC: Motor control PWM power/clock enable
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253 // <o11.18> PCQEI: Quadrature encoder interface power/clock enable
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254 // <o11.19> PCI2C1: I2C interface 1 power/clock enable
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255 // <o11.21> PCSSP0: SSP interface 0 power/clock enable
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256 // <o11.22> PCTIM2: Timer 2 power/clock enable
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257 // <o11.23> PCTIM3: Timer 3 power/clock enable
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258 // <o11.24> PCUART2: UART 2 power/clock enable
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259 // <o11.25> PCUART3: UART 3 power/clock enable
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260 // <o11.26> PCI2C2: I2C interface 2 power/clock enable
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261 // <o11.27> PCI2S: I2S interface power/clock enable
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262 // <o11.29> PCGPDMA: GP DMA function power/clock enable
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263 // <o11.30> PCENET: Ethernet block power/clock enable
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264 // <o11.31> PCUSB: USB interface power/clock enable
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267 // <h> Clock Output Configuration Register (CLKOUTCFG)
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268 // <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
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270 // <1=> Main oscillator
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271 // <2=> Internal RC oscillator
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273 // <4=> RTC oscillator
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274 // <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
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276 // <o12.8> CLKOUT_EN: CLKOUT enable control
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281 #define CLOCK_SETUP 1
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282 #define SCS_Val 0x00000020
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283 #define CLKSRCSEL_Val 0x00000001
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284 #define PLL0_SETUP 1
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285 #define PLL0CFG_Val 0x0000000B
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286 #define PLL1_SETUP 0
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287 #define PLL1CFG_Val 0x00000000
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288 #define CCLKCFG_Val 0x00000003
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289 #define USBCLKCFG_Val 0x00000000
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290 #define PCLKSEL0_Val 0x00000000
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291 #define PCLKSEL1_Val 0x00000000
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292 #define PCONP_Val 0x042887DE
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293 #define CLKOUTCFG_Val 0x00000000
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296 /*--------------------- Flash Accelerator Configuration ----------------------
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298 // <e> Flash Accelerator Configuration
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299 // <o1.0..1> FETCHCFG: Fetch Configuration
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300 // <0=> Instruction fetches from flash are not buffered
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301 // <1=> One buffer is used for all instruction fetch buffering
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302 // <2=> All buffers may be used for instruction fetch buffering
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303 // <3=> Reserved (do not use this setting)
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304 // <o1.2..3> DATACFG: Data Configuration
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305 // <0=> Data accesses from flash are not buffered
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306 // <1=> One buffer is used for all data access buffering
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307 // <2=> All buffers may be used for data access buffering
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308 // <3=> Reserved (do not use this setting)
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309 // <o1.4> ACCEL: Acceleration Enable
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310 // <o1.5> PREFEN: Prefetch Enable
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311 // <o1.6> PREFOVR: Prefetch Override
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312 // <o1.12..15> FLASHTIM: Flash Access Time
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313 // <0=> 1 CPU clock (for CPU clock up to 20 MHz)
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314 // <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
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315 // <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
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316 // <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
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317 // <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
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318 // <5=> 6 CPU clocks (for any CPU clock)
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321 #define FLASH_SETUP 1
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322 #define FLASHCFG_Val 0x0000303A
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325 //-------- <<< end of configuration section >>> ------------------------------
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328 /*----------------------------------------------------------------------------
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329 Check the register settings
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330 *----------------------------------------------------------------------------*/
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331 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
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332 #define CHECK_RSVD(val, mask) (val & mask)
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334 /* Clock Configuration -------------------------------------------------------*/
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335 #if (CHECK_RSVD((SCS_Val), ~0x00000030))
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336 #error "SCS: Invalid values of reserved bits!"
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339 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
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340 #error "CLKSRCSEL: Value out of range!"
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343 #if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
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344 #error "PLL0CFG: Invalid values of reserved bits!"
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347 #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
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348 #error "PLL1CFG: Invalid values of reserved bits!"
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351 #if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
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352 #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
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355 #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
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356 #error "USBCLKCFG: Invalid values of reserved bits!"
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359 #if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
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360 #error "PCLKSEL0: Invalid values of reserved bits!"
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363 #if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
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364 #error "PCLKSEL1: Invalid values of reserved bits!"
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367 #if (CHECK_RSVD((PCONP_Val), 0x10100821))
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368 #error "PCONP: Invalid values of reserved bits!"
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371 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
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372 #error "CLKOUTCFG: Invalid values of reserved bits!"
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375 /* Flash Accelerator Configuration -------------------------------------------*/
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376 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
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377 #error "FLASHCFG: Invalid values of reserved bits!"
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381 /*----------------------------------------------------------------------------
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383 *----------------------------------------------------------------------------*/
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385 /*----------------------------------------------------------------------------
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387 *----------------------------------------------------------------------------*/
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388 #define XTAL (12000000UL) /* Oscillator frequency */
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389 #define OSC_CLK ( XTAL) /* Main oscillator frequency */
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390 #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
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391 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
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394 /*----------------------------------------------------------------------------
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395 Clock Variable definitions
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396 *----------------------------------------------------------------------------*/
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397 uint32_t SystemFrequency = IRC_OSC; /*!< System Clock Frequency (Core Clock) */
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401 * Initialize the system
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406 * @brief Setup the microcontroller system.
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407 * Initialize the System and update the SystemFrequency variable.
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409 void SystemInit (void)
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411 #if (CLOCK_SETUP) /* Clock Setup */
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413 if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
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414 while ((SC->SCS & (1 << 6)) == 0); /* Wait for Oscillator to be ready */
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417 SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
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420 SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
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421 SC->PLL0CFG = PLL0CFG_Val;
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422 SC->PLL0CON = 0x01; /* PLL0 Enable */
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423 SC->PLL0FEED = 0xAA;
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424 SC->PLL0FEED = 0x55;
\r
425 while (!(SC->PLL0STAT & (1 << 26))); /* Wait for PLOCK0 */
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427 SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
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428 SC->PLL0FEED = 0xAA;
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429 SC->PLL0FEED = 0x55;
\r
433 SC->PLL1CFG = PLL1CFG_Val;
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434 SC->PLL1CON = 0x01; /* PLL1 Enable */
\r
435 SC->PLL1FEED = 0xAA;
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436 SC->PLL1FEED = 0x55;
\r
437 while (!(SC->PLL1STAT & (1 << 10))); /* Wait for PLOCK1 */
\r
439 SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
\r
440 SC->PLL1FEED = 0xAA;
\r
441 SC->PLL1FEED = 0x55;
\r
443 SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
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446 SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
\r
447 SC->PCLKSEL1 = PCLKSEL1_Val;
\r
449 SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
\r
451 SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
\r
454 /* Determine clock frequency according to clock register values */
\r
455 if (((SC->PLL0STAT >> 24) & 3) == 3) {/* If PLL0 enabled and connected */
\r
456 switch (SC->CLKSRCSEL & 0x03) {
\r
457 case 0: /* Internal RC oscillator => PLL0 */
\r
458 case 3: /* Reserved, default to Internal RC */
\r
459 SystemFrequency = (IRC_OSC *
\r
460 (((2 * ((SC->PLL0STAT & 0x7FFF) + 1))) /
\r
461 (((SC->PLL0STAT >> 16) & 0xFF) + 1)) /
\r
462 ((SC->CCLKCFG & 0xFF)+ 1));
\r
464 case 1: /* Main oscillator => PLL0 */
\r
465 SystemFrequency = (OSC_CLK *
\r
466 (((2 * ((SC->PLL0STAT & 0x7FFF) + 1))) /
\r
467 (((SC->PLL0STAT >> 16) & 0xFF) + 1)) /
\r
468 ((SC->CCLKCFG & 0xFF)+ 1));
\r
470 case 2: /* RTC oscillator => PLL0 */
\r
471 SystemFrequency = (RTC_CLK *
\r
472 (((2 * ((SC->PLL0STAT & 0x7FFF) + 1))) /
\r
473 (((SC->PLL0STAT >> 16) & 0xFF) + 1)) /
\r
474 ((SC->CCLKCFG & 0xFF)+ 1));
\r
478 switch (SC->CLKSRCSEL & 0x03) {
\r
479 case 0: /* Internal RC oscillator => PLL0 */
\r
480 case 3: /* Reserved, default to Internal RC */
\r
481 SystemFrequency = IRC_OSC / ((SC->CCLKCFG & 0xFF)+ 1);
\r
483 case 1: /* Main oscillator => PLL0 */
\r
484 SystemFrequency = OSC_CLK / ((SC->CCLKCFG & 0xFF)+ 1);
\r
486 case 2: /* RTC oscillator => PLL0 */
\r
487 SystemFrequency = RTC_CLK / ((SC->CCLKCFG & 0xFF)+ 1);
\r
492 #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
\r
493 SC->FLASHCFG = FLASHCFG_Val;
\r