1 /*----------------------------------------------------------------------------
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2 * U S B - K e r n e l
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3 *----------------------------------------------------------------------------
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5 * Purpose: USB Hardware Layer Definitions for NXP LPC Family MCUs
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7 *----------------------------------------------------------------------------
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8 * This software is supplied "AS IS" without any warranties, express,
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9 * implied or statutory, including but not limited to the implied
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10 * warranties of fitness for purpose, satisfactory quality and
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11 * noninfringement. Keil extends you a royalty-free right to reproduce
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12 * and distribute executable files created using this software for use
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13 * on NXP Semiconductors LPC family microcontroller devices only. Nothing
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14 * else gives you the right to use this software.
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16 * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
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17 *---------------------------------------------------------------------------*/
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22 /* Device Interrupt Bit Definitions */
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23 #define FRAME_INT 0x00000001
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24 #define EP_FAST_INT 0x00000002
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25 #define EP_SLOW_INT 0x00000004
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26 #define DEV_STAT_INT 0x00000008
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27 #define CCEMTY_INT 0x00000010
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28 #define CDFULL_INT 0x00000020
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29 #define RxENDPKT_INT 0x00000040
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30 #define TxENDPKT_INT 0x00000080
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31 #define EP_RLZED_INT 0x00000100
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32 #define ERR_INT 0x00000200
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34 /* Rx & Tx Packet Length Definitions */
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35 #define PKT_LNGTH_MASK 0x000003FF
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36 #define PKT_DV 0x00000400
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37 #define PKT_RDY 0x00000800
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39 /* USB Control Definitions */
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40 #define CTRL_RD_EN 0x00000001
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41 #define CTRL_WR_EN 0x00000002
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44 #define CMD_SET_ADDR 0x00D00500
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45 #define CMD_CFG_DEV 0x00D80500
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46 #define CMD_SET_MODE 0x00F30500
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47 #define CMD_RD_FRAME 0x00F50500
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48 #define DAT_RD_FRAME 0x00F50200
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49 #define CMD_RD_TEST 0x00FD0500
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50 #define DAT_RD_TEST 0x00FD0200
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51 #define CMD_SET_DEV_STAT 0x00FE0500
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52 #define CMD_GET_DEV_STAT 0x00FE0500
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53 #define DAT_GET_DEV_STAT 0x00FE0200
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54 #define CMD_GET_ERR_CODE 0x00FF0500
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55 #define DAT_GET_ERR_CODE 0x00FF0200
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56 #define CMD_RD_ERR_STAT 0x00FB0500
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57 #define DAT_RD_ERR_STAT 0x00FB0200
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58 #define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
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59 #define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
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60 #define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
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61 #define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
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62 #define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
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63 #define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
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64 #define CMD_CLR_BUF 0x00F20500
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65 #define DAT_CLR_BUF 0x00F20200
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66 #define CMD_VALID_BUF 0x00FA0500
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68 /* Device Address Register Definitions */
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69 #define DEV_ADDR_MASK 0x7F
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72 /* Device Configure Register Definitions */
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73 #define CONF_DVICE 0x01
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75 /* Device Mode Register Definitions */
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77 #define INAK_CI 0x02
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78 #define INAK_CO 0x04
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79 #define INAK_II 0x08
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80 #define INAK_IO 0x10
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81 #define INAK_BI 0x20
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82 #define INAK_BO 0x40
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84 /* Device Status Register Definitions */
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85 #define DEV_CON 0x01
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86 #define DEV_CON_CH 0x02
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87 #define DEV_SUS 0x04
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88 #define DEV_SUS_CH 0x08
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89 #define DEV_RST 0x10
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91 /* Error Code Register Definitions */
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92 #define ERR_EC_MASK 0x0F
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95 /* Error Status Register Definitions */
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96 #define ERR_PID 0x01
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97 #define ERR_UEPKT 0x02
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98 #define ERR_DCRC 0x04
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99 #define ERR_TIMOUT 0x08
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100 #define ERR_EOP 0x10
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101 #define ERR_B_OVRN 0x20
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102 #define ERR_BTSTF 0x40
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103 #define ERR_TGL 0x80
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105 /* Endpoint Select Register Definitions */
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106 #define EP_SEL_F 0x01
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107 #define EP_SEL_ST 0x02
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108 #define EP_SEL_STP 0x04
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109 #define EP_SEL_PO 0x08
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110 #define EP_SEL_EPN 0x10
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111 #define EP_SEL_B_1_FULL 0x20
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112 #define EP_SEL_B_2_FULL 0x40
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114 /* Endpoint Status Register Definitions */
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115 #define EP_STAT_ST 0x01
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116 #define EP_STAT_DA 0x20
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117 #define EP_STAT_RF_MO 0x40
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118 #define EP_STAT_CND_ST 0x80
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120 /* Clear Buffer Register Definitions */
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121 #define CLR_BUF_PO 0x01
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124 /* DMA Interrupt Bit Definitions */
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125 #define EOT_INT 0x01
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126 #define NDD_REQ_INT 0x02
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127 #define SYS_ERR_INT 0x04
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130 #endif /* __USBREG_H */
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