--- /dev/null
+/**************************************************************************//**\r
+ * @file system_LPC17xx.c\r
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File\r
+ * for the NXP LPC17xx Device Series\r
+ * @version V1.03\r
+ * @date 07. October 2009\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#include <stdint.h>\r
+#include "LPC17xx.h"\r
+\r
+/*\r
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
+*/\r
+\r
+/*--------------------- Clock Configuration ----------------------------------\r
+//\r
+// <e> Clock Configuration\r
+// <h> System Controls and Status Register (SCS)\r
+// <o1.4> OSCRANGE: Main Oscillator Range Select\r
+// <0=> 1 MHz to 20 MHz\r
+// <1=> 15 MHz to 24 MHz\r
+// <e1.5> OSCEN: Main Oscillator Enable\r
+// </e>\r
+// </h>\r
+//\r
+// <h> Clock Source Select Register (CLKSRCSEL)\r
+// <o2.0..1> CLKSRC: PLL Clock Source Selection\r
+// <0=> Internal RC oscillator\r
+// <1=> Main oscillator\r
+// <2=> RTC oscillator\r
+// </h>\r
+//\r
+// <e3> PLL0 Configuration (Main PLL)\r
+// <h> PLL0 Configuration Register (PLL0CFG)\r
+// <i> F_cco0 = (2 * M * F_in) / N\r
+// <i> F_in must be in the range of 32 kHz to 50 MHz\r
+// <i> F_cco0 must be in the range of 275 MHz to 550 MHz\r
+// <o4.0..14> MSEL: PLL Multiplier Selection\r
+// <6-32768><#-1>\r
+// <i> M Value\r
+// <o4.16..23> NSEL: PLL Divider Selection\r
+// <1-256><#-1>\r
+// <i> N Value\r
+// </h>\r
+// </e>\r
+//\r
+// <e5> PLL1 Configuration (USB PLL)\r
+// <h> PLL1 Configuration Register (PLL1CFG)\r
+// <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)\r
+// <i> F_cco1 = F_osc * M * 2 * P\r
+// <i> F_cco1 must be in the range of 156 MHz to 320 MHz\r
+// <o6.0..4> MSEL: PLL Multiplier Selection\r
+// <1-32><#-1>\r
+// <i> M Value (for USB maximum value is 4)\r
+// <o6.5..6> PSEL: PLL Divider Selection\r
+// <0=> 1\r
+// <1=> 2\r
+// <2=> 4\r
+// <3=> 8\r
+// <i> P Value\r
+// </h>\r
+// </e>\r
+//\r
+// <h> CPU Clock Configuration Register (CCLKCFG)\r
+// <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0\r
+// <3-256><#-1>\r
+// </h>\r
+//\r
+// <h> USB Clock Configuration Register (USBCLKCFG)\r
+// <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0\r
+// <0-15>\r
+// <i> Divide is USBSEL + 1\r
+// </h>\r
+//\r
+// <h> Peripheral Clock Selection Register 0 (PCLKSEL0)\r
+// <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 6\r
+// <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 6\r
+// <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 6\r
+// </h>\r
+//\r
+// <h> Peripheral Clock Selection Register 1 (PCLKSEL1)\r
+// <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM\r
+// <0=> Pclk = Cclk / 4\r
+// <1=> Pclk = Cclk\r
+// <2=> Pclk = Cclk / 2\r
+// <3=> Pclk = Hclk / 8\r
+// </h>\r
+//\r
+// <h> Power Control for Peripherals Register (PCONP)\r
+// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable\r
+// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable\r
+// <o11.3> PCUART0: UART 0 power/clock enable\r
+// <o11.4> PCUART1: UART 1 power/clock enable\r
+// <o11.6> PCPWM1: PWM 1 power/clock enable\r
+// <o11.7> PCI2C0: I2C interface 0 power/clock enable\r
+// <o11.8> PCSPI: SPI interface power/clock enable\r
+// <o11.9> PCRTC: RTC power/clock enable\r
+// <o11.10> PCSSP1: SSP interface 1 power/clock enable\r
+// <o11.12> PCAD: A/D converter power/clock enable\r
+// <o11.13> PCCAN1: CAN controller 1 power/clock enable\r
+// <o11.14> PCCAN2: CAN controller 2 power/clock enable\r
+// <o11.15> PCGPIO: GPIOs power/clock enable\r
+// <o11.16> PCRIT: Repetitive interrupt timer power/clock enable\r
+// <o11.17> PCMC: Motor control PWM power/clock enable\r
+// <o11.18> PCQEI: Quadrature encoder interface power/clock enable\r
+// <o11.19> PCI2C1: I2C interface 1 power/clock enable\r
+// <o11.21> PCSSP0: SSP interface 0 power/clock enable\r
+// <o11.22> PCTIM2: Timer 2 power/clock enable\r
+// <o11.23> PCTIM3: Timer 3 power/clock enable\r
+// <o11.24> PCUART2: UART 2 power/clock enable\r
+// <o11.25> PCUART3: UART 3 power/clock enable\r
+// <o11.26> PCI2C2: I2C interface 2 power/clock enable\r
+// <o11.27> PCI2S: I2S interface power/clock enable\r
+// <o11.29> PCGPDMA: GP DMA function power/clock enable\r
+// <o11.30> PCENET: Ethernet block power/clock enable\r
+// <o11.31> PCUSB: USB interface power/clock enable\r
+// </h>\r
+//\r
+// <h> Clock Output Configuration Register (CLKOUTCFG)\r
+// <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT\r
+// <0=> CPU clock\r
+// <1=> Main oscillator\r
+// <2=> Internal RC oscillator\r
+// <3=> USB clock\r
+// <4=> RTC oscillator\r
+// <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT\r
+// <1-16><#-1>\r
+// <o12.8> CLKOUT_EN: CLKOUT enable control\r
+// </h>\r
+//\r
+// </e>\r
+*/\r
+#define CLOCK_SETUP 1\r
+#define SCS_Val 0x00000020\r
+#define CLKSRCSEL_Val 0x00000001\r
+#define PLL0_SETUP 1\r
+#define PLL0CFG_Val 0x00050063\r
+#define PLL1_SETUP 1\r
+#define PLL1CFG_Val 0x00000023\r
+#define CCLKCFG_Val 0x00000003\r
+#define USBCLKCFG_Val 0x00000000\r
+#define PCLKSEL0_Val 0x00000000\r
+#define PCLKSEL1_Val 0x00000000\r
+#define PCONP_Val 0x042887DE\r
+#define CLKOUTCFG_Val 0x00000000\r
+\r
+\r
+/*--------------------- Flash Accelerator Configuration ----------------------\r
+//\r
+// <e> Flash Accelerator Configuration\r
+// <o1.0..11> Reserved\r
+// <o1.12..15> FLASHTIM: Flash Access Time\r
+// <0=> 1 CPU clock (for CPU clock up to 20 MHz)\r
+// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)\r
+// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)\r
+// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)\r
+// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)\r
+// <5=> 6 CPU clocks (for any CPU clock)\r
+// </e>\r
+*/\r
+#define FLASH_SETUP 1\r
+#define FLASHCFG_Val 0x0000303A\r
+\r
+/*\r
+//-------- <<< end of configuration section >>> ------------------------------\r
+*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ Check the register settings\r
+ *----------------------------------------------------------------------------*/\r
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))\r
+#define CHECK_RSVD(val, mask) (val & mask)\r
+\r
+/* Clock Configuration -------------------------------------------------------*/\r
+#if (CHECK_RSVD((SCS_Val), ~0x00000030))\r
+ #error "SCS: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))\r
+ #error "CLKSRCSEL: Value out of range!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))\r
+ #error "PLL0CFG: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))\r
+ #error "PLL1CFG: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))\r
+ #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))\r
+ #error "USBCLKCFG: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))\r
+ #error "PCLKSEL0: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))\r
+ #error "PCLKSEL1: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((PCONP_Val), 0x10100821))\r
+ #error "PCONP: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))\r
+ #error "CLKOUTCFG: Invalid values of reserved bits!"\r
+#endif\r
+\r
+/* Flash Accelerator Configuration -------------------------------------------*/\r
+#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))\r
+ #error "FLASHCFG: Invalid values of reserved bits!"\r
+#endif\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ DEFINES\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ Define clocks\r
+ *----------------------------------------------------------------------------*/\r
+#define XTAL (12000000UL) /* Oscillator frequency */\r
+#define OSC_CLK ( XTAL) /* Main oscillator frequency */\r
+#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */\r
+#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */\r
+\r
+\r
+/* F_cco0 = (2 * M * F_in) / N */\r
+#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)\r
+#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)\r
+#define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)\r
+#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)\r
+\r
+/* Determine core clock frequency according to settings */\r
+ #if (PLL0_SETUP)\r
+ #if ((CLKSRCSEL_Val & 0x03) == 1)\r
+ #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)\r
+ #elif ((CLKSRCSEL_Val & 0x03) == 2)\r
+ #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)\r
+ #else\r
+ #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)\r
+ #endif\r
+ #else\r
+ #if ((CLKSRCSEL_Val & 0x03) == 1)\r
+ #define __CORE_CLK (OSC_CLK / __CCLK_DIV)\r
+ #elif ((CLKSRCSEL_Val & 0x03) == 2)\r
+ #define __CORE_CLK (RTC_CLK / __CCLK_DIV)\r
+ #else\r
+ #define __CORE_CLK (IRC_OSC / __CCLK_DIV)\r
+ #endif\r
+ #endif\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock functions\r
+ *----------------------------------------------------------------------------*/\r
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */\r
+{\r
+ /* Determine clock frequency according to clock register values */\r
+ if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */\r
+ switch (LPC_SC->CLKSRCSEL & 0x03) {\r
+ case 0: /* Int. RC oscillator => PLL0 */\r
+ case 3: /* Reserved, default to Int. RC */\r
+ SystemCoreClock = (IRC_OSC *\r
+ ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /\r
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /\r
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));\r
+ break;\r
+ case 1: /* Main oscillator => PLL0 */\r
+ SystemCoreClock = (OSC_CLK *\r
+ ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /\r
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /\r
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));\r
+ break;\r
+ case 2: /* RTC oscillator => PLL0 */\r
+ SystemCoreClock = (RTC_CLK *\r
+ ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /\r
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /\r
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));\r
+ break;\r
+ }\r
+ } else {\r
+ switch (LPC_SC->CLKSRCSEL & 0x03) {\r
+ case 0: /* Int. RC oscillator => PLL0 */\r
+ case 3: /* Reserved, default to Int. RC */\r
+ SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);\r
+ break;\r
+ case 1: /* Main oscillator => PLL0 */\r
+ SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);\r
+ break;\r
+ case 2: /* RTC oscillator => PLL0 */\r
+ SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);\r
+ break;\r
+ }\r
+ }\r
+\r
+}\r
+/* Exported types --------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+//extern unsigned long _sidata; /* start address for the initialization values of the .data section. defined in linker script */\r
+//extern unsigned long _sdata; /* start address for the .data section. defined in linker script */\r
+//extern unsigned long _edata; /* end address for the .data section. defined in linker script */\r
+//\r
+//extern unsigned long _sbss; /* start address for the .bss section. defined in linker script */\r
+//extern unsigned long _ebss; /* end address for the .bss section. defined in linker script */\r
+\r
+//void _init(void)\r
+//{\r
+// unsigned long *pulSrc, *pulDest;\r
+//\r
+// //\r
+// // Copy the data segment initializers from flash to SRAM in ROM mode\r
+// //\r
+//#if (__RAM_MODE__==0)\r
+// pulSrc = &_sidata;\r
+// for(pulDest = &_sdata; pulDest < &_edata; )\r
+// {\r
+// *(pulDest++) = *(pulSrc++);\r
+// }\r
+//#endif\r
+//\r
+//\r
+// //\r
+// // Zero fill the bss segment.\r
+// //\r
+// for(pulDest = &_sbss; pulDest < &_ebss; )\r
+// {\r
+// *(pulDest++) = 0;\r
+// }\r
+//}\r
+\r
+/**\r
+ * Initialize the system\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the System.\r
+ */\r
+void SystemInit (void)\r
+{\r
+\r
+#if (CLOCK_SETUP) /* Clock Setup */\r
+ LPC_SC->SCS = SCS_Val;\r
+ if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */\r
+ while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */\r
+ }\r
+\r
+ LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */\r
+ LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */\r
+ LPC_SC->PCLKSEL1 = PCLKSEL1_Val;\r
+\r
+#if (PLL0_SETUP)\r
+ LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */\r
+\r
+ LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */\r
+ LPC_SC->PLL0FEED = 0xAA;\r
+ LPC_SC->PLL0FEED = 0x55;\r
+\r
+ LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */\r
+ LPC_SC->PLL0FEED = 0xAA;\r
+ LPC_SC->PLL0FEED = 0x55;\r
+ while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */\r
+\r
+ LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */\r
+ LPC_SC->PLL0FEED = 0xAA;\r
+ LPC_SC->PLL0FEED = 0x55;\r
+ while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */\r
+#endif\r
+\r
+#if (PLL1_SETUP)\r
+ LPC_SC->PLL1CFG = PLL1CFG_Val;\r
+ LPC_SC->PLL1FEED = 0xAA;\r
+ LPC_SC->PLL1FEED = 0x55;\r
+\r
+ LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */\r
+ LPC_SC->PLL1FEED = 0xAA;\r
+ LPC_SC->PLL1FEED = 0x55;\r
+ while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */\r
+\r
+ LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */\r
+ LPC_SC->PLL1FEED = 0xAA;\r
+ LPC_SC->PLL1FEED = 0x55;\r
+ while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */\r
+#else\r
+ LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */\r
+#endif\r
+ LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */\r
+\r
+ LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */\r
+#endif\r
+\r
+#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */\r
+ LPC_SC->FLASHCFG = FLASHCFG_Val;\r
+#endif\r
+}\r
git.asbjorn.biz / rapper.git / blobdiff