X-Git-Url: http://git.asbjorn.biz/?p=rapper.git;a=blobdiff_plain;f=bitbucket_lpc1768%2FCMSIS%2Fsystem_LPC17xx.c;fp=bitbucket_lpc1768%2FCMSIS%2Fsystem_LPC17xx.c;h=0000000000000000000000000000000000000000;hp=9687619ed73689486d3be874487d6a632e04e695;hb=7964505b5eaf8be846f82c6c3c5a3f6c9dc84ede;hpb=dddaffd50b66ca9c149601a71673a66b90924b52 diff --git a/bitbucket_lpc1768/CMSIS/system_LPC17xx.c b/bitbucket_lpc1768/CMSIS/system_LPC17xx.c deleted file mode 100755 index 9687619..0000000 --- a/bitbucket_lpc1768/CMSIS/system_LPC17xx.c +++ /dev/null @@ -1,559 +0,0 @@ -/**************************************************************************//** - * @file system_LPC17xx.c - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File - * for the NXP LPC17xx Device Series - * @version V1.03 - * @date 07. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#include -#include "LPC17xx.h" - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- Clock Configuration ---------------------------------- -// -// Clock Configuration -// System Controls and Status Register (SCS) -// OSCRANGE: Main Oscillator Range Select -// <0=> 1 MHz to 20 MHz -// <1=> 15 MHz to 24 MHz -// OSCEN: Main Oscillator Enable -// -// -// -// Clock Source Select Register (CLKSRCSEL) -// CLKSRC: PLL Clock Source Selection -// <0=> Internal RC oscillator -// <1=> Main oscillator -// <2=> RTC oscillator -// -// -// PLL0 Configuration (Main PLL) -// PLL0 Configuration Register (PLL0CFG) -// F_cco0 = (2 * M * F_in) / N -// F_in must be in the range of 32 kHz to 50 MHz -// F_cco0 must be in the range of 275 MHz to 550 MHz -// MSEL: PLL Multiplier Selection -// <6-32768><#-1> -// M Value -// NSEL: PLL Divider Selection -// <1-256><#-1> -// N Value -// -// -// -// PLL1 Configuration (USB PLL) -// PLL1 Configuration Register (PLL1CFG) -// F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) -// F_cco1 = F_osc * M * 2 * P -// F_cco1 must be in the range of 156 MHz to 320 MHz -// MSEL: PLL Multiplier Selection -// <1-32><#-1> -// M Value (for USB maximum value is 4) -// PSEL: PLL Divider Selection -// <0=> 1 -// <1=> 2 -// <2=> 4 -// <3=> 8 -// P Value -// -// -// -// CPU Clock Configuration Register (CCLKCFG) -// CCLKSEL: Divide Value for CPU Clock from PLL0 -// <3-256><#-1> -// -// -// USB Clock Configuration Register (USBCLKCFG) -// USBSEL: Divide Value for USB Clock from PLL0 -// <0-15> -// Divide is USBSEL + 1 -// -// -// Peripheral Clock Selection Register 0 (PCLKSEL0) -// PCLK_WDT: Peripheral Clock Selection for WDT -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_TIMER0: Peripheral Clock Selection for TIMER0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_TIMER1: Peripheral Clock Selection for TIMER1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_UART0: Peripheral Clock Selection for UART0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_UART1: Peripheral Clock Selection for UART1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_PWM1: Peripheral Clock Selection for PWM1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_I2C0: Peripheral Clock Selection for I2C0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_SPI: Peripheral Clock Selection for SPI -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_SSP1: Peripheral Clock Selection for SSP1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_DAC: Peripheral Clock Selection for DAC -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_ADC: Peripheral Clock Selection for ADC -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_CAN1: Peripheral Clock Selection for CAN1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 6 -// PCLK_CAN2: Peripheral Clock Selection for CAN2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 6 -// PCLK_ACF: Peripheral Clock Selection for ACF -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 6 -// -// -// Peripheral Clock Selection Register 1 (PCLKSEL1) -// PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_GPIO: Peripheral Clock Selection for GPIOs -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_I2C1: Peripheral Clock Selection for I2C1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_SSP0: Peripheral Clock Selection for SSP0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_TIMER2: Peripheral Clock Selection for TIMER2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_TIMER3: Peripheral Clock Selection for TIMER3 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_UART2: Peripheral Clock Selection for UART2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_UART3: Peripheral Clock Selection for UART3 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_I2C2: Peripheral Clock Selection for I2C2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_I2S: Peripheral Clock Selection for I2S -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_SYSCON: Peripheral Clock Selection for the System Control Block -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_MC: Peripheral Clock Selection for the Motor Control PWM -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// -// -// Power Control for Peripherals Register (PCONP) -// PCTIM0: Timer/Counter 0 power/clock enable -// PCTIM1: Timer/Counter 1 power/clock enable -// PCUART0: UART 0 power/clock enable -// PCUART1: UART 1 power/clock enable -// PCPWM1: PWM 1 power/clock enable -// PCI2C0: I2C interface 0 power/clock enable -// PCSPI: SPI interface power/clock enable -// PCRTC: RTC power/clock enable -// PCSSP1: SSP interface 1 power/clock enable -// PCAD: A/D converter power/clock enable -// PCCAN1: CAN controller 1 power/clock enable -// PCCAN2: CAN controller 2 power/clock enable -// PCGPIO: GPIOs power/clock enable -// PCRIT: Repetitive interrupt timer power/clock enable -// PCMC: Motor control PWM power/clock enable -// PCQEI: Quadrature encoder interface power/clock enable -// PCI2C1: I2C interface 1 power/clock enable -// PCSSP0: SSP interface 0 power/clock enable -// PCTIM2: Timer 2 power/clock enable -// PCTIM3: Timer 3 power/clock enable -// PCUART2: UART 2 power/clock enable -// PCUART3: UART 3 power/clock enable -// PCI2C2: I2C interface 2 power/clock enable -// PCI2S: I2S interface power/clock enable -// PCGPDMA: GP DMA function power/clock enable -// PCENET: Ethernet block power/clock enable -// PCUSB: USB interface power/clock enable -// -// -// Clock Output Configuration Register (CLKOUTCFG) -// CLKOUTSEL: Selects clock source for CLKOUT -// <0=> CPU clock -// <1=> Main oscillator -// <2=> Internal RC oscillator -// <3=> USB clock -// <4=> RTC oscillator -// CLKOUTDIV: Selects clock divider for CLKOUT -// <1-16><#-1> -// CLKOUT_EN: CLKOUT enable control -// -// -// -*/ -#define CLOCK_SETUP 1 -#define SCS_Val 0x00000020 -#define CLKSRCSEL_Val 0x00000001 -#define PLL0_SETUP 1 -#define PLL0CFG_Val 0x00050063 -#define PLL1_SETUP 1 -#define PLL1CFG_Val 0x00000023 -#define CCLKCFG_Val 0x00000003 -#define USBCLKCFG_Val 0x00000000 -#define PCLKSEL0_Val 0x00000000 -#define PCLKSEL1_Val 0x00000000 -#define PCONP_Val 0x042887DE -#define CLKOUTCFG_Val 0x00000000 - - -/*--------------------- Flash Accelerator Configuration ---------------------- -// -// Flash Accelerator Configuration -// Reserved -// FLASHTIM: Flash Access Time -// <0=> 1 CPU clock (for CPU clock up to 20 MHz) -// <1=> 2 CPU clocks (for CPU clock up to 40 MHz) -// <2=> 3 CPU clocks (for CPU clock up to 60 MHz) -// <3=> 4 CPU clocks (for CPU clock up to 80 MHz) -// <4=> 5 CPU clocks (for CPU clock up to 100 MHz) -// <5=> 6 CPU clocks (for any CPU clock) -// -*/ -#define FLASH_SETUP 1 -#define FLASHCFG_Val 0x0000303A - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -/*---------------------------------------------------------------------------- - Check the register settings - *----------------------------------------------------------------------------*/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) -#define CHECK_RSVD(val, mask) (val & mask) - -/* Clock Configuration -------------------------------------------------------*/ -#if (CHECK_RSVD((SCS_Val), ~0x00000030)) - #error "SCS: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2)) - #error "CLKSRCSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF)) - #error "PLL0CFG: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) - #error "PLL1CFG: Invalid values of reserved bits!" -#endif - -#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2))) - #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!" -#endif - -#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F)) - #error "USBCLKCFG: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00)) - #error "PCLKSEL0: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300)) - #error "PCLKSEL1: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCONP_Val), 0x10100821)) - #error "PCONP: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) - #error "CLKOUTCFG: Invalid values of reserved bits!" -#endif - -/* Flash Accelerator Configuration -------------------------------------------*/ -#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F)) - #error "FLASHCFG: Invalid values of reserved bits!" -#endif - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (12000000UL) /* Oscillator frequency */ -#define OSC_CLK ( XTAL) /* Main oscillator frequency */ -#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */ -#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ - - -/* F_cco0 = (2 * M * F_in) / N */ -#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1) -#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1) -#define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N) -#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1) - -/* Determine core clock frequency according to settings */ - #if (PLL0_SETUP) - #if ((CLKSRCSEL_Val & 0x03) == 1) - #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV) - #elif ((CLKSRCSEL_Val & 0x03) == 2) - #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV) - #else - #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV) - #endif - #else - #if ((CLKSRCSEL_Val & 0x03) == 1) - #define __CORE_CLK (OSC_CLK / __CCLK_DIV) - #elif ((CLKSRCSEL_Val & 0x03) == 2) - #define __CORE_CLK (RTC_CLK / __CCLK_DIV) - #else - #define __CORE_CLK (IRC_OSC / __CCLK_DIV) - #endif - #endif - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ - - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ - /* Determine clock frequency according to clock register values */ - if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */ - switch (LPC_SC->CLKSRCSEL & 0x03) { - case 0: /* Int. RC oscillator => PLL0 */ - case 3: /* Reserved, default to Int. RC */ - SystemCoreClock = (IRC_OSC * - ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / - ((LPC_SC->CCLKCFG & 0xFF)+ 1)); - break; - case 1: /* Main oscillator => PLL0 */ - SystemCoreClock = (OSC_CLK * - ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / - ((LPC_SC->CCLKCFG & 0xFF)+ 1)); - break; - case 2: /* RTC oscillator => PLL0 */ - SystemCoreClock = (RTC_CLK * - ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / - ((LPC_SC->CCLKCFG & 0xFF)+ 1)); - break; - } - } else { - switch (LPC_SC->CLKSRCSEL & 0x03) { - case 0: /* Int. RC oscillator => PLL0 */ - case 3: /* Reserved, default to Int. RC */ - SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1); - break; - case 1: /* Main oscillator => PLL0 */ - SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); - break; - case 2: /* RTC oscillator => PLL0 */ - SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); - break; - } - } - -} -/* Exported types --------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -//extern unsigned long _sidata; /* start address for the initialization values of the .data section. defined in linker script */ -//extern unsigned long _sdata; /* start address for the .data section. defined in linker script */ -//extern unsigned long _edata; /* end address for the .data section. defined in linker script */ -// -//extern unsigned long _sbss; /* start address for the .bss section. defined in linker script */ -//extern unsigned long _ebss; /* end address for the .bss section. defined in linker script */ - -//void _init(void) -//{ -// unsigned long *pulSrc, *pulDest; -// -// // -// // Copy the data segment initializers from flash to SRAM in ROM mode -// // -//#if (__RAM_MODE__==0) -// pulSrc = &_sidata; -// for(pulDest = &_sdata; pulDest < &_edata; ) -// { -// *(pulDest++) = *(pulSrc++); -// } -//#endif -// -// -// // -// // Zero fill the bss segment. -// // -// for(pulDest = &_sbss; pulDest < &_ebss; ) -// { -// *(pulDest++) = 0; -// } -//} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) -{ - -#if (CLOCK_SETUP) /* Clock Setup */ - LPC_SC->SCS = SCS_Val; - if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ - while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ - } - - LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ - LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */ - LPC_SC->PCLKSEL1 = PCLKSEL1_Val; - -#if (PLL0_SETUP) - LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ - - LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - - LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */ - - LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */ -#endif - -#if (PLL1_SETUP) - LPC_SC->PLL1CFG = PLL1CFG_Val; - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - - LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ - - LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */ - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */ -#else - LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */ -#endif - LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ - - LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ -#endif - -#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ - LPC_SC->FLASHCFG = FLASHCFG_Val; -#endif -}