From: Asbjørn Sloth Tønnesen Date: Thu, 2 Dec 2010 17:57:14 +0000 (+0000) Subject: removing bitbucket_lpc1768 again now that new_cmsis works X-Git-Url: http://git.asbjorn.biz/?p=rapper.git;a=commitdiff_plain;h=7964505b5eaf8be846f82c6c3c5a3f6c9dc84ede removing bitbucket_lpc1768 again now that new_cmsis works Signed-off-by: Asbjørn Sloth Tønnesen --- diff --git a/bitbucket_lpc1768/.hg/00changelog.i b/bitbucket_lpc1768/.hg/00changelog.i deleted file mode 100644 index d3a8311..0000000 Binary files a/bitbucket_lpc1768/.hg/00changelog.i and /dev/null differ diff --git a/bitbucket_lpc1768/.hg/branch b/bitbucket_lpc1768/.hg/branch deleted file mode 100644 index c191305..0000000 --- a/bitbucket_lpc1768/.hg/branch +++ /dev/null @@ -1 +0,0 @@ -4-io-pin-blinky diff --git a/bitbucket_lpc1768/.hg/branchheads.cache b/bitbucket_lpc1768/.hg/branchheads.cache deleted file mode 100644 index f82b085..0000000 --- a/bitbucket_lpc1768/.hg/branchheads.cache +++ /dev/null @@ -1,5 +0,0 @@ -dea43fb213fffca688938b96a265a788797ef3f4 11 -41ecca7377d50d23f66177ded872cd5c03503035 2-simple-blinky-100MHz -dea43fb213fffca688938b96a265a788797ef3f4 4-io-pin-blinky -4500b8db379f48245b0e560355cdce3a4c1d132f 1-simple-blinky -29d00ba31af5afb6159f71a22930cb8b4d884965 3-systick-blinky diff --git a/bitbucket_lpc1768/.hg/dirstate b/bitbucket_lpc1768/.hg/dirstate deleted file mode 100644 index cdc30e2..0000000 Binary files a/bitbucket_lpc1768/.hg/dirstate and /dev/null differ diff --git a/bitbucket_lpc1768/.hg/hgrc b/bitbucket_lpc1768/.hg/hgrc deleted file mode 100644 index cf8bc2d..0000000 --- a/bitbucket_lpc1768/.hg/hgrc +++ /dev/null @@ -1,2 +0,0 @@ -[paths] -default = http://bitbucket.org/jpc/lpc1768 diff --git a/bitbucket_lpc1768/.hg/requires b/bitbucket_lpc1768/.hg/requires deleted file mode 100644 index 5175383..0000000 --- a/bitbucket_lpc1768/.hg/requires +++ /dev/null @@ -1,3 +0,0 @@ -revlogv1 -store -fncache diff --git a/bitbucket_lpc1768/.hg/store/00changelog.i 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2-simple-blinky-100MHz -0a00a016c609c4a31f9c2b1fc7dc4ea5958ba8c3 3-systick-blinky -0a00a016c609c4a31f9c2b1fc7dc4ea5958ba8c3 3-systick-blinky -390e9530c93f57868311aa2ab69c67c4cce2226a 3-systick-blinky -bb46c18616910e1ce3f962a2831a888865057518 1-simple-blinky -0000000000000000000000000000000000000000 1-simple-blinky -765e4649efad723b7bf4d47773d9b784e5d8f9c3 2-simple-blinky-100MHz -0000000000000000000000000000000000000000 2-simple-blinky-100MHz -390e9530c93f57868311aa2ab69c67c4cce2226a 3-systick-blinky -0000000000000000000000000000000000000000 3-systick-blinky diff --git a/bitbucket_lpc1768/2 b/bitbucket_lpc1768/2 deleted file mode 100644 index e69de29..0000000 diff --git a/bitbucket_lpc1768/CMSIS/LPC17xx.h b/bitbucket_lpc1768/CMSIS/LPC17xx.h deleted file mode 100755 index 7019e2d..0000000 --- a/bitbucket_lpc1768/CMSIS/LPC17xx.h +++ /dev/null @@ -1,1038 +0,0 @@ -/**************************************************************************//** - * @file LPC17xx.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for - * NXP LPC17xx Device Series - * @version V1.07 - * @date 19. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __LPC17xx_H__ -#define __LPC17xx_H__ - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ - -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** LPC17xx Specific Interrupt Numbers *******************************************************/ - WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ - TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ - TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ - TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ - TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ - UART0_IRQn = 5, /*!< UART0 Interrupt */ - UART1_IRQn = 6, /*!< UART1 Interrupt */ - UART2_IRQn = 7, /*!< UART2 Interrupt */ - UART3_IRQn = 8, /*!< UART3 Interrupt */ - PWM1_IRQn = 9, /*!< PWM1 Interrupt */ - I2C0_IRQn = 10, /*!< I2C0 Interrupt */ - I2C1_IRQn = 11, /*!< I2C1 Interrupt */ - I2C2_IRQn = 12, /*!< I2C2 Interrupt */ - SPI_IRQn = 13, /*!< SPI Interrupt */ - SSP0_IRQn = 14, /*!< SSP0 Interrupt */ - SSP1_IRQn = 15, /*!< SSP1 Interrupt */ - PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ - RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ - EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ - EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ - EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ - EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ - ADC_IRQn = 22, /*!< A/D Converter Interrupt */ - BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ - USB_IRQn = 24, /*!< USB Interrupt */ - CAN_IRQn = 25, /*!< CAN Interrupt */ - DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ - I2S_IRQn = 27, /*!< I2S Interrupt */ - ENET_IRQn = 28, /*!< Ethernet Interrupt */ - RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */ - MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ - QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ - PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ - USBActivity_IRQn = 33, /*!< USB Activity Interrupt */ - CANActivity_IRQn = 34, /*!< CAN Activity Interrupt */ -} IRQn_Type; - - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/* Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - - -#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ -#include "system_LPC17xx.h" /* System Header */ - - -/******************************************************************************/ -/* Device Specific Peripheral registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/*------------- System Control (SC) ------------------------------------------*/ -typedef struct -{ - __IO uint32_t FLASHCFG; /* Flash Accelerator Module */ - uint32_t RESERVED0[31]; - __IO uint32_t PLL0CON; /* Clocking and Power Control */ - __IO uint32_t PLL0CFG; - __I uint32_t PLL0STAT; - __O uint32_t PLL0FEED; - uint32_t RESERVED1[4]; - __IO uint32_t PLL1CON; - __IO uint32_t PLL1CFG; - __I uint32_t PLL1STAT; - __O uint32_t PLL1FEED; - uint32_t RESERVED2[4]; - __IO uint32_t PCON; - __IO uint32_t PCONP; - uint32_t RESERVED3[15]; - __IO uint32_t CCLKCFG; - __IO uint32_t USBCLKCFG; - __IO uint32_t CLKSRCSEL; - uint32_t RESERVED4[12]; - __IO uint32_t EXTINT; /* External Interrupts */ - uint32_t RESERVED5; - __IO uint32_t EXTMODE; - __IO uint32_t EXTPOLAR; - uint32_t RESERVED6[12]; - __IO uint32_t RSID; /* Reset */ - uint32_t RESERVED7[7]; - __IO uint32_t SCS; /* Syscon Miscellaneous Registers */ - __IO uint32_t IRCTRIM; /* Clock Dividers */ - __IO uint32_t PCLKSEL0; - __IO uint32_t PCLKSEL1; - uint32_t RESERVED8[4]; - __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */ - __IO uint32_t DMAREQSEL; - __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */ - } LPC_SC_TypeDef; - -/*------------- Pin Connect Block (PINCON) -----------------------------------*/ -typedef struct -{ - __IO uint32_t PINSEL0; - __IO uint32_t PINSEL1; - __IO uint32_t PINSEL2; - __IO uint32_t PINSEL3; - __IO uint32_t PINSEL4; - __IO uint32_t PINSEL5; - __IO uint32_t PINSEL6; - __IO uint32_t PINSEL7; - __IO uint32_t PINSEL8; - __IO uint32_t PINSEL9; - __IO uint32_t PINSEL10; - uint32_t RESERVED0[5]; - __IO uint32_t PINMODE0; - __IO uint32_t PINMODE1; - __IO uint32_t PINMODE2; - __IO uint32_t PINMODE3; - __IO uint32_t PINMODE4; - __IO uint32_t PINMODE5; - __IO uint32_t PINMODE6; - __IO uint32_t PINMODE7; - __IO uint32_t PINMODE8; - __IO uint32_t PINMODE9; - __IO uint32_t PINMODE_OD0; - __IO uint32_t PINMODE_OD1; - __IO uint32_t PINMODE_OD2; - __IO uint32_t PINMODE_OD3; - __IO uint32_t PINMODE_OD4; - __IO uint32_t I2CPADCFG; -} LPC_PINCON_TypeDef; - -/*------------- General Purpose Input/Output (GPIO) --------------------------*/ -typedef struct -{ - union { - __IO uint32_t FIODIR; - struct { - __IO uint16_t FIODIRL; - __IO uint16_t FIODIRH; - }; - struct { - __IO uint8_t FIODIR0; - __IO uint8_t FIODIR1; - __IO uint8_t FIODIR2; - __IO uint8_t FIODIR3; - }; - }; - uint32_t RESERVED0[3]; - union { - __IO uint32_t FIOMASK; - struct { - __IO uint16_t FIOMASKL; - __IO uint16_t FIOMASKH; - }; - struct { - __IO uint8_t FIOMASK0; - __IO uint8_t FIOMASK1; - __IO uint8_t FIOMASK2; - __IO uint8_t FIOMASK3; - }; - }; - union { - __IO uint32_t FIOPIN; - struct { - __IO uint16_t FIOPINL; - __IO uint16_t FIOPINH; - }; - struct { - __IO uint8_t FIOPIN0; - __IO uint8_t FIOPIN1; - __IO uint8_t FIOPIN2; - __IO uint8_t FIOPIN3; - }; - }; - union { - __IO uint32_t FIOSET; - struct { - __IO uint16_t FIOSETL; - __IO uint16_t FIOSETH; - }; - struct { - __IO uint8_t FIOSET0; - __IO uint8_t FIOSET1; - __IO uint8_t FIOSET2; - __IO uint8_t FIOSET3; - }; - }; - union { - __O uint32_t FIOCLR; - struct { - __O uint16_t FIOCLRL; - __O uint16_t FIOCLRH; - }; - struct { - __O uint8_t FIOCLR0; - __O uint8_t FIOCLR1; - __O uint8_t FIOCLR2; - __O uint8_t FIOCLR3; - }; - }; -} LPC_GPIO_TypeDef; - -typedef struct -{ - __I uint32_t IntStatus; - __I uint32_t IO0IntStatR; - __I uint32_t IO0IntStatF; - __O uint32_t IO0IntClr; - __IO uint32_t IO0IntEnR; - __IO uint32_t IO0IntEnF; - uint32_t RESERVED0[3]; - __I uint32_t IO2IntStatR; - __I uint32_t IO2IntStatF; - __O uint32_t IO2IntClr; - __IO uint32_t IO2IntEnR; - __IO uint32_t IO2IntEnF; -} LPC_GPIOINT_TypeDef; - -/*------------- Timer (TIM) --------------------------------------------------*/ -typedef struct -{ - __IO uint32_t IR; - __IO uint32_t TCR; - __IO uint32_t TC; - __IO uint32_t PR; - __IO uint32_t PC; - __IO uint32_t MCR; - __IO uint32_t MR0; - __IO uint32_t MR1; - __IO uint32_t MR2; - __IO uint32_t MR3; - __IO uint32_t CCR; - __I uint32_t CR0; - __I uint32_t CR1; - uint32_t RESERVED0[2]; - __IO uint32_t EMR; - uint32_t RESERVED1[12]; - __IO uint32_t CTCR; -} LPC_TIM_TypeDef; - -/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ -typedef struct -{ - __IO uint32_t IR; - __IO uint32_t TCR; - __IO uint32_t TC; - __IO uint32_t PR; - __IO uint32_t PC; - __IO uint32_t MCR; - __IO uint32_t MR0; - __IO uint32_t MR1; - __IO uint32_t MR2; - __IO uint32_t MR3; - __IO uint32_t CCR; - __I uint32_t CR0; - __I uint32_t CR1; - __I uint32_t CR2; - __I uint32_t CR3; - uint32_t RESERVED0; - __IO uint32_t MR4; - __IO uint32_t MR5; - __IO uint32_t MR6; - __IO uint32_t PCR; - __IO uint32_t LER; - uint32_t RESERVED1[7]; - __IO uint32_t CTCR; -} LPC_PWM_TypeDef; - -/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[7]; - __I uint8_t LSR; - uint8_t RESERVED2[7]; - __IO uint8_t SCR; - uint8_t RESERVED3[3]; - __IO uint32_t ACR; - __IO uint8_t ICR; - uint8_t RESERVED4[3]; - __IO uint8_t FDR; - uint8_t RESERVED5[7]; - __IO uint8_t TER; - uint8_t RESERVED6[39]; - __I uint8_t FIFOLVL; -} LPC_UART_TypeDef; - -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[7]; - __I uint8_t LSR; - uint8_t RESERVED2[7]; - __IO uint8_t SCR; - uint8_t RESERVED3[3]; - __IO uint32_t ACR; - __IO uint8_t ICR; - uint8_t RESERVED4[3]; - __IO uint8_t FDR; - uint8_t RESERVED5[7]; - __IO uint8_t TER; - uint8_t RESERVED6[39]; - __I uint8_t FIFOLVL; -} LPC_UART0_TypeDef; - -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[3]; - __IO uint8_t MCR; - uint8_t RESERVED2[3]; - __I uint8_t LSR; - uint8_t RESERVED3[3]; - __I uint8_t MSR; - uint8_t RESERVED4[3]; - __IO uint8_t SCR; - uint8_t RESERVED5[3]; - __IO uint32_t ACR; - uint32_t RESERVED6; - __IO uint32_t FDR; - uint32_t RESERVED7; - __IO uint8_t TER; - uint8_t RESERVED8[27]; - __IO uint8_t RS485CTRL; - uint8_t RESERVED9[3]; - __IO uint8_t ADRMATCH; - uint8_t RESERVED10[3]; - __IO uint8_t RS485DLY; - uint8_t RESERVED11[3]; - __I uint8_t FIFOLVL; -} LPC_UART1_TypeDef; - -/*------------- Serial Peripheral Interface (SPI) ----------------------------*/ -typedef struct -{ - __IO uint32_t SPCR; - __I uint32_t SPSR; - __IO uint32_t SPDR; - __IO uint32_t SPCCR; - uint32_t RESERVED0[3]; - __IO uint32_t SPINT; -} LPC_SPI_TypeDef; - -/*------------- Synchronous Serial Communication (SSP) -----------------------*/ -typedef struct -{ - __IO uint32_t CR0; - __IO uint32_t CR1; - __IO uint32_t DR; - __I uint32_t SR; - __IO uint32_t CPSR; - __IO uint32_t IMSC; - __IO uint32_t RIS; - __IO uint32_t MIS; - __IO uint32_t ICR; - __IO uint32_t DMACR; -} LPC_SSP_TypeDef; - -/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ -typedef struct -{ - __IO uint32_t I2CONSET; - __I uint32_t I2STAT; - __IO uint32_t I2DAT; - __IO uint32_t I2ADR0; - __IO uint32_t I2SCLH; - __IO uint32_t I2SCLL; - __O uint32_t I2CONCLR; - __IO uint32_t MMCTRL; - __IO uint32_t I2ADR1; - __IO uint32_t I2ADR2; - __IO uint32_t I2ADR3; - __I uint32_t I2DATA_BUFFER; - __IO uint32_t I2MASK0; - __IO uint32_t I2MASK1; - __IO uint32_t I2MASK2; - __IO uint32_t I2MASK3; -} LPC_I2C_TypeDef; - -/*------------- Inter IC Sound (I2S) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t I2SDAO; - __IO uint32_t I2SDAI; - __O uint32_t I2STXFIFO; - __I uint32_t I2SRXFIFO; - __I uint32_t I2SSTATE; - __IO uint32_t I2SDMA1; - __IO uint32_t I2SDMA2; - __IO uint32_t I2SIRQ; - __IO uint32_t I2STXRATE; - __IO uint32_t I2SRXRATE; - __IO uint32_t I2STXBITRATE; - __IO uint32_t I2SRXBITRATE; - __IO uint32_t I2STXMODE; - __IO uint32_t I2SRXMODE; -} LPC_I2S_TypeDef; - -/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/ -typedef struct -{ - __IO uint32_t RICOMPVAL; - __IO uint32_t RIMASK; - __IO uint8_t RICTRL; - uint8_t RESERVED0[3]; - __IO uint32_t RICOUNTER; -} LPC_RIT_TypeDef; - -/*------------- Real-Time Clock (RTC) ----------------------------------------*/ -typedef struct -{ - __IO uint8_t ILR; - uint8_t RESERVED0[7]; - __IO uint8_t CCR; - uint8_t RESERVED1[3]; - __IO uint8_t CIIR; - uint8_t RESERVED2[3]; - __IO uint8_t AMR; - uint8_t RESERVED3[3]; - __I uint32_t CTIME0; - __I uint32_t CTIME1; - __I uint32_t CTIME2; - __IO uint8_t SEC; - uint8_t RESERVED4[3]; - __IO uint8_t MIN; - uint8_t RESERVED5[3]; - __IO uint8_t HOUR; - uint8_t RESERVED6[3]; - __IO uint8_t DOM; - uint8_t RESERVED7[3]; - __IO uint8_t DOW; - uint8_t RESERVED8[3]; - __IO uint16_t DOY; - uint16_t RESERVED9; - __IO uint8_t MONTH; - uint8_t RESERVED10[3]; - __IO uint16_t YEAR; - uint16_t RESERVED11; - __IO uint32_t CALIBRATION; - __IO uint32_t GPREG0; - __IO uint32_t GPREG1; - __IO uint32_t GPREG2; - __IO uint32_t GPREG3; - __IO uint32_t GPREG4; - __IO uint8_t RTC_AUXEN; - uint8_t RESERVED12[3]; - __IO uint8_t RTC_AUX; - uint8_t RESERVED13[3]; - __IO uint8_t ALSEC; - uint8_t RESERVED14[3]; - __IO uint8_t ALMIN; - uint8_t RESERVED15[3]; - __IO uint8_t ALHOUR; - uint8_t RESERVED16[3]; - __IO uint8_t ALDOM; - uint8_t RESERVED17[3]; - __IO uint8_t ALDOW; - uint8_t RESERVED18[3]; - __IO uint16_t ALDOY; - uint16_t RESERVED19; - __IO uint8_t ALMON; - uint8_t RESERVED20[3]; - __IO uint16_t ALYEAR; - uint16_t RESERVED21; -} LPC_RTC_TypeDef; - -/*------------- Watchdog Timer (WDT) -----------------------------------------*/ -typedef struct -{ - __IO uint8_t WDMOD; - uint8_t RESERVED0[3]; - __IO uint32_t WDTC; - __O uint8_t WDFEED; - uint8_t RESERVED1[3]; - __I uint32_t WDTV; - __IO uint32_t WDCLKSEL; -} LPC_WDT_TypeDef; - -/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ -typedef struct -{ - __IO uint32_t ADCR; - __IO uint32_t ADGDR; - uint32_t RESERVED0; - __IO uint32_t ADINTEN; - __I uint32_t ADDR0; - __I uint32_t ADDR1; - __I uint32_t ADDR2; - __I uint32_t ADDR3; - __I uint32_t ADDR4; - __I uint32_t ADDR5; - __I uint32_t ADDR6; - __I uint32_t ADDR7; - __I uint32_t ADSTAT; - __IO uint32_t ADTRM; -} LPC_ADC_TypeDef; - -/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ -typedef struct -{ - __IO uint32_t DACR; - __IO uint32_t DACCTRL; - __IO uint16_t DACCNTVAL; -} LPC_DAC_TypeDef; - -/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ -typedef struct -{ - __I uint32_t MCCON; - __O uint32_t MCCON_SET; - __O uint32_t MCCON_CLR; - __I uint32_t MCCAPCON; - __O uint32_t MCCAPCON_SET; - __O uint32_t MCCAPCON_CLR; - __IO uint32_t MCTIM0; - __IO uint32_t MCTIM1; - __IO uint32_t MCTIM2; - __IO uint32_t MCPER0; - __IO uint32_t MCPER1; - __IO uint32_t MCPER2; - __IO uint32_t MCPW0; - __IO uint32_t MCPW1; - __IO uint32_t MCPW2; - __IO uint32_t MCDEADTIME; - __IO uint32_t MCCCP; - __IO uint32_t MCCR0; - __IO uint32_t MCCR1; - __IO uint32_t MCCR2; - __I uint32_t MCINTEN; - __O uint32_t MCINTEN_SET; - __O uint32_t MCINTEN_CLR; - __I uint32_t MCCNTCON; - __O uint32_t MCCNTCON_SET; - __O uint32_t MCCNTCON_CLR; - __I uint32_t MCINTFLAG; - __O uint32_t MCINTFLAG_SET; - __O uint32_t MCINTFLAG_CLR; - __O uint32_t MCCAP_CLR; -} LPC_MCPWM_TypeDef; - -/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ -typedef struct -{ - __O uint32_t QEICON; - __I uint32_t QEISTAT; - __IO uint32_t QEICONF; - __I uint32_t QEIPOS; - __IO uint32_t QEIMAXPOS; - __IO uint32_t CMPOS0; - __IO uint32_t CMPOS1; - __IO uint32_t CMPOS2; - __I uint32_t INXCNT; - __IO uint32_t INXCMP; - __IO uint32_t QEILOAD; - __I uint32_t QEITIME; - __I uint32_t QEIVEL; - __I uint32_t QEICAP; - __IO uint32_t VELCOMP; - __IO uint32_t FILTER; - uint32_t RESERVED0[998]; - __O uint32_t QEIIEC; - __O uint32_t QEIIES; - __I uint32_t QEIINTSTAT; - __I uint32_t QEIIE; - __O uint32_t QEICLR; - __O uint32_t QEISET; -} LPC_QEI_TypeDef; - -/*------------- Controller Area Network (CAN) --------------------------------*/ -typedef struct -{ - __IO uint32_t mask[512]; /* ID Masks */ -} LPC_CANAF_RAM_TypeDef; - -typedef struct /* Acceptance Filter Registers */ -{ - __IO uint32_t AFMR; - __IO uint32_t SFF_sa; - __IO uint32_t SFF_GRP_sa; - __IO uint32_t EFF_sa; - __IO uint32_t EFF_GRP_sa; - __IO uint32_t ENDofTable; - __I uint32_t LUTerrAd; - __I uint32_t LUTerr; - __IO uint32_t FCANIE; - __IO uint32_t FCANIC0; - __IO uint32_t FCANIC1; -} LPC_CANAF_TypeDef; - -typedef struct /* Central Registers */ -{ - __I uint32_t CANTxSR; - __I uint32_t CANRxSR; - __I uint32_t CANMSR; -} LPC_CANCR_TypeDef; - -typedef struct /* Controller Registers */ -{ - __IO uint32_t MOD; - __O uint32_t CMR; - __IO uint32_t GSR; - __I uint32_t ICR; - __IO uint32_t IER; - __IO uint32_t BTR; - __IO uint32_t EWL; - __I uint32_t SR; - __IO uint32_t RFS; - __IO uint32_t RID; - __IO uint32_t RDA; - __IO uint32_t RDB; - __IO uint32_t TFI1; - __IO uint32_t TID1; - __IO uint32_t TDA1; - __IO uint32_t TDB1; - __IO uint32_t TFI2; - __IO uint32_t TID2; - __IO uint32_t TDA2; - __IO uint32_t TDB2; - __IO uint32_t TFI3; - __IO uint32_t TID3; - __IO uint32_t TDA3; - __IO uint32_t TDB3; -} LPC_CAN_TypeDef; - -/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ -typedef struct /* Common Registers */ -{ - __I uint32_t DMACIntStat; - __I uint32_t DMACIntTCStat; - __O uint32_t DMACIntTCClear; - __I uint32_t DMACIntErrStat; - __O uint32_t DMACIntErrClr; - __I uint32_t DMACRawIntTCStat; - __I uint32_t DMACRawIntErrStat; - __I uint32_t DMACEnbldChns; - __IO uint32_t DMACSoftBReq; - __IO uint32_t DMACSoftSReq; - __IO uint32_t DMACSoftLBReq; - __IO uint32_t DMACSoftLSReq; - __IO uint32_t DMACConfig; - __IO uint32_t DMACSync; -} LPC_GPDMA_TypeDef; - -typedef struct /* Channel Registers */ -{ - __IO uint32_t DMACCSrcAddr; - __IO uint32_t DMACCDestAddr; - __IO uint32_t DMACCLLI; - __IO uint32_t DMACCControl; - __IO uint32_t DMACCConfig; -} LPC_GPDMACH_TypeDef; - -/*------------- Universal Serial Bus (USB) -----------------------------------*/ -typedef struct -{ - __I uint32_t HcRevision; /* USB Host Registers */ - __IO uint32_t HcControl; - __IO uint32_t HcCommandStatus; - __IO uint32_t HcInterruptStatus; - __IO uint32_t HcInterruptEnable; - __IO uint32_t HcInterruptDisable; - __IO uint32_t HcHCCA; - __I uint32_t HcPeriodCurrentED; - __IO uint32_t HcControlHeadED; - __IO uint32_t HcControlCurrentED; - __IO uint32_t HcBulkHeadED; - __IO uint32_t HcBulkCurrentED; - __I uint32_t HcDoneHead; - __IO uint32_t HcFmInterval; - __I uint32_t HcFmRemaining; - __I uint32_t HcFmNumber; - __IO uint32_t HcPeriodicStart; - __IO uint32_t HcLSTreshold; - __IO uint32_t HcRhDescriptorA; - __IO uint32_t HcRhDescriptorB; - __IO uint32_t HcRhStatus; - __IO uint32_t HcRhPortStatus1; - __IO uint32_t HcRhPortStatus2; - uint32_t RESERVED0[40]; - __I uint32_t Module_ID; - - __I uint32_t OTGIntSt; /* USB On-The-Go Registers */ - __IO uint32_t OTGIntEn; - __O uint32_t OTGIntSet; - __O uint32_t OTGIntClr; - __IO uint32_t OTGStCtrl; - __IO uint32_t OTGTmr; - uint32_t RESERVED1[58]; - - __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */ - __IO uint32_t USBDevIntEn; - __O uint32_t USBDevIntClr; - __O uint32_t USBDevIntSet; - - __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */ - __I uint32_t USBCmdData; - - __I uint32_t USBRxData; /* USB Device Transfer Registers */ - __O uint32_t USBTxData; - __I uint32_t USBRxPLen; - __O uint32_t USBTxPLen; - __IO uint32_t USBCtrl; - __O uint32_t USBDevIntPri; - - __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */ - __IO uint32_t USBEpIntEn; - __O uint32_t USBEpIntClr; - __O uint32_t USBEpIntSet; - __O uint32_t USBEpIntPri; - - __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/ - __O uint32_t USBEpInd; - __IO uint32_t USBMaxPSize; - - __I uint32_t USBDMARSt; /* USB Device DMA Registers */ - __O uint32_t USBDMARClr; - __O uint32_t USBDMARSet; - uint32_t RESERVED2[9]; - __IO uint32_t USBUDCAH; - __I uint32_t USBEpDMASt; - __O uint32_t USBEpDMAEn; - __O uint32_t USBEpDMADis; - __I uint32_t USBDMAIntSt; - __IO uint32_t USBDMAIntEn; - uint32_t RESERVED3[2]; - __I uint32_t USBEoTIntSt; - __O uint32_t USBEoTIntClr; - __O uint32_t USBEoTIntSet; - __I uint32_t USBNDDRIntSt; - __O uint32_t USBNDDRIntClr; - __O uint32_t USBNDDRIntSet; - __I uint32_t USBSysErrIntSt; - __O uint32_t USBSysErrIntClr; - __O uint32_t USBSysErrIntSet; - uint32_t RESERVED4[15]; - - __I uint32_t I2C_RX; /* USB OTG I2C Registers */ - __O uint32_t I2C_WO; - __I uint32_t I2C_STS; - __IO uint32_t I2C_CTL; - __IO uint32_t I2C_CLKHI; - __O uint32_t I2C_CLKLO; - uint32_t RESERVED5[823]; - - union { - __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ - __IO uint32_t OTGClkCtrl; - }; - union { - __I uint32_t USBClkSt; - __I uint32_t OTGClkSt; - }; -} LPC_USB_TypeDef; - -/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ -typedef struct -{ - __IO uint32_t MAC1; /* MAC Registers */ - __IO uint32_t MAC2; - __IO uint32_t IPGT; - __IO uint32_t IPGR; - __IO uint32_t CLRT; - __IO uint32_t MAXF; - __IO uint32_t SUPP; - __IO uint32_t TEST; - __IO uint32_t MCFG; - __IO uint32_t MCMD; - __IO uint32_t MADR; - __O uint32_t MWTD; - __I uint32_t MRDD; - __I uint32_t MIND; - uint32_t RESERVED0[2]; - __IO uint32_t SA0; - __IO uint32_t SA1; - __IO uint32_t SA2; - uint32_t RESERVED1[45]; - __IO uint32_t Command; /* Control Registers */ - __I uint32_t Status; - __IO uint32_t RxDescriptor; - __IO uint32_t RxStatus; - __IO uint32_t RxDescriptorNumber; - __I uint32_t RxProduceIndex; - __IO uint32_t RxConsumeIndex; - __IO uint32_t TxDescriptor; - __IO uint32_t TxStatus; - __IO uint32_t TxDescriptorNumber; - __IO uint32_t TxProduceIndex; - __I uint32_t TxConsumeIndex; - uint32_t RESERVED2[10]; - __I uint32_t TSV0; - __I uint32_t TSV1; - __I uint32_t RSV; - uint32_t RESERVED3[3]; - __IO uint32_t FlowControlCounter; - __I uint32_t FlowControlStatus; - uint32_t RESERVED4[34]; - __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ - __IO uint32_t RxFilterWoLStatus; - __IO uint32_t RxFilterWoLClear; - uint32_t RESERVED5; - __IO uint32_t HashFilterL; - __IO uint32_t HashFilterH; - uint32_t RESERVED6[882]; - __I uint32_t IntStatus; /* Module Control Registers */ - __IO uint32_t IntEnable; - __O uint32_t IntClear; - __O uint32_t IntSet; - uint32_t RESERVED7; - __IO uint32_t PowerDown; - uint32_t RESERVED8; - __IO uint32_t Module_ID; -} LPC_EMAC_TypeDef; - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Base addresses */ -#define LPC_FLASH_BASE (0x00000000UL) -#define LPC_RAM_BASE (0x10000000UL) -#ifdef __LPC17XX_REV00 -#define LPC_AHBRAM0_BASE (0x20000000UL) -#define LPC_AHBRAM1_BASE (0x20004000UL) -#else -#define LPC_AHBRAM0_BASE (0x2007C000UL) -#define LPC_AHBRAM1_BASE (0x20080000UL) -#endif -#define LPC_GPIO_BASE (0x2009C000UL) -#define LPC_APB0_BASE (0x40000000UL) -#define LPC_APB1_BASE (0x40080000UL) -#define LPC_AHB_BASE (0x50000000UL) -#define LPC_CM3_BASE (0xE0000000UL) - -/* APB0 peripherals */ -#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) -#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) -#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) -#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) -#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) -#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) -#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) -#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) -#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) -#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) -#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000) -#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) -#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) -#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) -#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) -#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) -#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) -#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) -#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) - -/* APB1 peripherals */ -#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) -#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) -#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) -#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) -#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) -#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) -#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) -#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) -#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000) -#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) -#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) -#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) - -/* AHB peripherals */ -#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000) -#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100) -#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120) -#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140) -#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160) -#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180) -#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0) -#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0) -#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0) -#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) - -/* GPIOs */ -#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000) -#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020) -#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040) -#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060) -#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080) - - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) -#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) -#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) -#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) -#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) -#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) -#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) -#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) -#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) -#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) -#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) -#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE ) -#define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE ) -#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) -#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) -#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) -#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) -#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) -#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) -#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) -#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) -#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE ) -#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) -#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) -#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE ) -#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) -#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) -#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) -#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) -#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) -#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) -#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) -#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) -#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) -#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) -#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) -#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) -#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) -#define DMAREQSEL (*(__IO uint32_t *) ( 0x4000C1C4)) -#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) -#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) -#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) -#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) -#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) -#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) -#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) -#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) -#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) - -#endif // __LPC17xx_H__ diff --git a/bitbucket_lpc1768/CMSIS/core_cm3.h b/bitbucket_lpc1768/CMSIS/core_cm3.h deleted file mode 100755 index 2c46056..0000000 --- a/bitbucket_lpc1768/CMSIS/core_cm3.h +++ /dev/null @@ -1,1818 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CM3_CORE_H__ -#define __CM3_CORE_H__ - -/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration - * - * List of Lint messages which will be suppressed and not shown: - * - Error 10: \n - * register uint32_t __regBasePri __asm("basepri"); \n - * Error 10: Expecting ';' - * . - * - Error 530: \n - * return(__regBasePri); \n - * Warning 530: Symbol '__regBasePri' (line 264) not initialized - * . - * - Error 550: \n - * __regBasePri = (basePri & 0x1ff); \n - * Warning 550: Symbol '__regBasePri' (line 271) not accessed - * . - * - Error 754: \n - * uint32_t RESERVED0[24]; \n - * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced - * . - * - Error 750: \n - * #define __CM3_CORE_H__ \n - * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced - * . - * - Error 528: \n - * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n - * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced - * . - * - Error 751: \n - * } InterruptType_Type; \n - * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced - * . - * Note: To re-enable a Message, insert a space before 'lint' * - * - */ - -/*lint -save */ -/*lint -e10 */ -/*lint -e530 */ -/*lint -e550 */ -/*lint -e754 */ -/*lint -e750 */ -/*lint -e528 */ -/*lint -e751 */ - - -/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core registers and bitfields - - Cortex-M core peripheral base address - @{ - */ - -#ifdef __cplusplus - extern "C" { -#endif - -#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - -#include /* Include standard types */ - -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - - -#ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ -#endif - - - - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ - -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register - @{ -*/ - - -/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC - memory mapped structure for Nested Vectored Interrupt Controller (NVIC) - @{ - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ -} NVIC_Type; -/*@}*/ /* end of group CMSIS_CM3_NVIC */ - - -/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB - memory mapped structure for System Control Block (SCB) - @{ - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ -/*@}*/ /* end of group CMSIS_CM3_SCB */ - - -/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick - memory mapped structure for SysTick - @{ - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ -/*@}*/ /* end of group CMSIS_CM3_SysTick */ - - -/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM - memory mapped structure for Instrumentation Trace Macrocell (ITM) - @{ - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ - __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ - __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ -/*@}*/ /* end of group CMSIS_CM3_ITM */ - - -/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type - memory mapped structure for Interrupt Type - @{ - */ -typedef struct -{ - uint32_t RESERVED0; - __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ -#else - uint32_t RESERVED1; -#endif -} InterruptType_Type; - -/* Interrupt Controller Type Register Definitions */ -#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ -#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ -#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ - -#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ -#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ - -#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ -#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ -/*@}*/ /* end of group CMSIS_CM3_InterruptType */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) -/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU - memory mapped structure for Memory Protection Unit (MPU) - @{ - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ -#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ -#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ -#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ -#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ -#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ -#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@}*/ /* end of group CMSIS_CM3_MPU */ -#endif - - -/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug - memory mapped structure for Core Debug Register - @{ - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ -/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ - - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ - -#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ -#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_register */ - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#define __enable_fault_irq __enable_fiq -#define __disable_fault_irq __disable_fiq - -#define __NOP __nop -#define __WFI __wfi -#define __WFE __wfe -#define __SEV __sev -#define __ISB() __isb(0) -#define __DSB() __dsb(0) -#define __DMB() __dmb(0) -#define __REV __rev -#define __RBIT __rbit -#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) -#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) -#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) -#define __STREXB(value, ptr) __strex(value, ptr) -#define __STREXH(value, ptr) __strex(value, ptr) -#define __STREXW(value, ptr) __strex(value, ptr) - - -/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ -/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -extern void __CLREX(void); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -#else /* (__ARMCC_VERSION >= 400000) */ - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -#define __CLREX __clrex - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & 1); -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ -#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ - -static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } - -#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ -static __INLINE void __WFI() { __ASM ("wfi"); } -static __INLINE void __WFE() { __ASM ("wfe"); } -static __INLINE void __SEV() { __ASM ("sev"); } -static __INLINE void __CLREX() { __ASM ("clrex"); } - -/* intrinsic void __ISB(void) */ -/* intrinsic void __DSB(void) */ -/* intrinsic void __DMB(void) */ -/* intrinsic void __set_PRIMASK(); */ -/* intrinsic void __get_PRIMASK(); */ -/* intrinsic void __set_FAULTMASK(); */ -/* intrinsic void __get_FAULTMASK(); */ -/* intrinsic uint32_t __REV(uint32_t value); */ -/* intrinsic uint32_t __REVSH(uint32_t value); */ -/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ -/* intrinsic unsigned long __LDREX(unsigned long *); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } -static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } - -static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } - -static __INLINE void __NOP() { __ASM volatile ("nop"); } -static __INLINE void __WFI() { __ASM volatile ("wfi"); } -static __INLINE void __WFE() { __ASM volatile ("wfe"); } -static __INLINE void __SEV() { __ASM volatile ("sev"); } -static __INLINE void __ISB() { __ASM volatile ("isb"); } -static __INLINE void __DSB() { __ASM volatile ("dsb"); } -static __INLINE void __DMB() { __ASM volatile ("dmb"); } -static __INLINE void __CLREX() { __ASM volatile ("clrex"); } - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -extern uint32_t __REV(uint32_t value); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - - -/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface - Core Function Interface containing: - - Core NVIC Functions - - Core SysTick Functions - - Core Reset Functions -*/ -/*@{*/ - -/* ########################## NVIC functions #################################### */ - -/** - * @brief Set the Priority Grouping in NVIC Interrupt Controller - * - * @param PriorityGroup is priority grouping field - * - * Set the priority grouping field using the required unlock sequence. - * The parameter priority_grouping is assigned to the field - * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - (0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - -/** - * @brief Get the Priority Grouping from NVIC Interrupt Controller - * - * @return priority grouping field - * - * Get the priority grouping from NVIC Interrupt Controller. - * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - -/** - * @brief Enable Interrupt in NVIC Interrupt Controller - * - * @param IRQn The positive number of the external interrupt to enable - * - * Enable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - -/** - * @brief Disable the interrupt line for external interrupt specified - * - * @param IRQn The positive number of the external interrupt to disable - * - * Disable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - -/** - * @brief Read the interrupt pending bit for a device specific interrupt source - * - * @param IRQn The number of the device specifc interrupt - * @return 1 = interrupt pending, 0 = interrupt not pending - * - * Read the pending register in NVIC and return 1 if its status is pending, - * otherwise it returns 0 - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - -/** - * @brief Set the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for set pending - * - * Set the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - -/** - * @brief Clear the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for clear pending - * - * Clear the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - -/** - * @brief Read the active bit for an external interrupt - * - * @param IRQn The number of the interrupt for read active bit - * @return 1 = interrupt active, 0 = interrupt not active - * - * Read the active register in NVIC and returns 1 if its status is active, - * otherwise it returns 0. - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - -/** - * @brief Set the priority for an interrupt - * - * @param IRQn The number of the interrupt for set priority - * @param priority The priority to set - * - * Set the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - -/** - * @brief Read the priority for an interrupt - * - * @param IRQn The number of the interrupt for get priority - * @return The priority for the interrupt - * - * Read the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * The returned priority value is automatically aligned to the implemented - * priority bits of the microcontroller. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** - * @brief Encode the priority for an interrupt - * - * @param PriorityGroup The used priority group - * @param PreemptPriority The preemptive priority value (starting from 0) - * @param SubPriority The sub priority value (starting from 0) - * @return The encoded priority for the interrupt - * - * Encode the priority for an interrupt with the given priority group, - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The returned priority value can be used for NVIC_SetPriority(...) function - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** - * @brief Decode the priority of an interrupt - * - * @param Priority The priority for the interrupt - * @param PriorityGroup The used priority group - * @param pPreemptPriority The preemptive priority value (starting from 0) - * @param pSubPriority The sub priority value (starting from 0) - * - * Decode an interrupt priority value with the given priority group to - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The priority value can be retrieved with NVIC_GetPriority(...) function - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - - -/* ################################## SysTick function ############################################ */ - -#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) - -/** - * @brief Initialize and start the SysTick counter and its interrupt. - * - * @param ticks number of ticks between two interrupts - * @return 1 = failed, 0 = successful - * - * Initialise the system tick timer and its interrupt and start the - * system tick timer / counter in free running mode to generate - * periodical interrupts. - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - - - - -/* ################################## Reset function ############################################ */ - -/** - * @brief Initiate a system reset request. - * - * Initiate a system reset request to reset the MCU - */ -static __INLINE void NVIC_SystemReset(void) -{ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ - - - -/* ##################################### Debug In/Output function ########################################### */ - -/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface - Core Debug Interface containing: - - Core Debug Receive / Transmit Functions - - Core Debug Defines - - Core Debug Variables -*/ -/*@{*/ - -extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** - * @brief Outputs a character via the ITM channel 0 - * - * @param ch character to output - * @return character to output - * - * The function outputs a character via the ITM channel 0. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** - * @brief Inputs a character via variable ITM_RxBuffer - * - * @return received character, -1 = no character received - * - * The function inputs a character via variable ITM_RxBuffer. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE int ITM_ReceiveChar (void) { - int ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - * @brief Check if a character via variable ITM_RxBuffer is available - * - * @return 1 = character available, 0 = no character available - * - * The function checks variable ITM_RxBuffer whether a character is available or not. - * The function returns '1' if a character is available and '0' if no character is available. - */ -static __INLINE int ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_definitions */ - -#endif /* __CM3_CORE_H__ */ - -/*lint -restore */ diff --git a/bitbucket_lpc1768/CMSIS/system_LPC17xx.c b/bitbucket_lpc1768/CMSIS/system_LPC17xx.c deleted file mode 100755 index 9687619..0000000 --- a/bitbucket_lpc1768/CMSIS/system_LPC17xx.c +++ /dev/null @@ -1,559 +0,0 @@ -/**************************************************************************//** - * @file system_LPC17xx.c - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File - * for the NXP LPC17xx Device Series - * @version V1.03 - * @date 07. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#include -#include "LPC17xx.h" - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- Clock Configuration ---------------------------------- -// -// Clock Configuration -// System Controls and Status Register (SCS) -// OSCRANGE: Main Oscillator Range Select -// <0=> 1 MHz to 20 MHz -// <1=> 15 MHz to 24 MHz -// OSCEN: Main Oscillator Enable -// -// -// -// Clock Source Select Register (CLKSRCSEL) -// CLKSRC: PLL Clock Source Selection -// <0=> Internal RC oscillator -// <1=> Main oscillator -// <2=> RTC oscillator -// -// -// PLL0 Configuration (Main PLL) -// PLL0 Configuration Register (PLL0CFG) -// F_cco0 = (2 * M * F_in) / N -// F_in must be in the range of 32 kHz to 50 MHz -// F_cco0 must be in the range of 275 MHz to 550 MHz -// MSEL: PLL Multiplier Selection -// <6-32768><#-1> -// M Value -// NSEL: PLL Divider Selection -// <1-256><#-1> -// N Value -// -// -// -// PLL1 Configuration (USB PLL) -// PLL1 Configuration Register (PLL1CFG) -// F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) -// F_cco1 = F_osc * M * 2 * P -// F_cco1 must be in the range of 156 MHz to 320 MHz -// MSEL: PLL Multiplier Selection -// <1-32><#-1> -// M Value (for USB maximum value is 4) -// PSEL: PLL Divider Selection -// <0=> 1 -// <1=> 2 -// <2=> 4 -// <3=> 8 -// P Value -// -// -// -// CPU Clock Configuration Register (CCLKCFG) -// CCLKSEL: Divide Value for CPU Clock from PLL0 -// <3-256><#-1> -// -// -// USB Clock Configuration Register (USBCLKCFG) -// USBSEL: Divide Value for USB Clock from PLL0 -// <0-15> -// Divide is USBSEL + 1 -// -// -// Peripheral Clock Selection Register 0 (PCLKSEL0) -// PCLK_WDT: Peripheral Clock Selection for WDT -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_TIMER0: Peripheral Clock Selection for TIMER0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_TIMER1: Peripheral Clock Selection for TIMER1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_UART0: Peripheral Clock Selection for UART0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_UART1: Peripheral Clock Selection for UART1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_PWM1: Peripheral Clock Selection for PWM1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_I2C0: Peripheral Clock Selection for I2C0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_SPI: Peripheral Clock Selection for SPI -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_SSP1: Peripheral Clock Selection for SSP1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_DAC: Peripheral Clock Selection for DAC -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_ADC: Peripheral Clock Selection for ADC -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_CAN1: Peripheral Clock Selection for CAN1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 6 -// PCLK_CAN2: Peripheral Clock Selection for CAN2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 6 -// PCLK_ACF: Peripheral Clock Selection for ACF -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 6 -// -// -// Peripheral Clock Selection Register 1 (PCLKSEL1) -// PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_GPIO: Peripheral Clock Selection for GPIOs -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_I2C1: Peripheral Clock Selection for I2C1 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_SSP0: Peripheral Clock Selection for SSP0 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_TIMER2: Peripheral Clock Selection for TIMER2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_TIMER3: Peripheral Clock Selection for TIMER3 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_UART2: Peripheral Clock Selection for UART2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_UART3: Peripheral Clock Selection for UART3 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_I2C2: Peripheral Clock Selection for I2C2 -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_I2S: Peripheral Clock Selection for I2S -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_SYSCON: Peripheral Clock Selection for the System Control Block -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// PCLK_MC: Peripheral Clock Selection for the Motor Control PWM -// <0=> Pclk = Cclk / 4 -// <1=> Pclk = Cclk -// <2=> Pclk = Cclk / 2 -// <3=> Pclk = Hclk / 8 -// -// -// Power Control for Peripherals Register (PCONP) -// PCTIM0: Timer/Counter 0 power/clock enable -// PCTIM1: Timer/Counter 1 power/clock enable -// PCUART0: UART 0 power/clock enable -// PCUART1: UART 1 power/clock enable -// PCPWM1: PWM 1 power/clock enable -// PCI2C0: I2C interface 0 power/clock enable -// PCSPI: SPI interface power/clock enable -// PCRTC: RTC power/clock enable -// PCSSP1: SSP interface 1 power/clock enable -// PCAD: A/D converter power/clock enable -// PCCAN1: CAN controller 1 power/clock enable -// PCCAN2: CAN controller 2 power/clock enable -// PCGPIO: GPIOs power/clock enable -// PCRIT: Repetitive interrupt timer power/clock enable -// PCMC: Motor control PWM power/clock enable -// PCQEI: Quadrature encoder interface power/clock enable -// PCI2C1: I2C interface 1 power/clock enable -// PCSSP0: SSP interface 0 power/clock enable -// PCTIM2: Timer 2 power/clock enable -// PCTIM3: Timer 3 power/clock enable -// PCUART2: UART 2 power/clock enable -// PCUART3: UART 3 power/clock enable -// PCI2C2: I2C interface 2 power/clock enable -// PCI2S: I2S interface power/clock enable -// PCGPDMA: GP DMA function power/clock enable -// PCENET: Ethernet block power/clock enable -// PCUSB: USB interface power/clock enable -// -// -// Clock Output Configuration Register (CLKOUTCFG) -// CLKOUTSEL: Selects clock source for CLKOUT -// <0=> CPU clock -// <1=> Main oscillator -// <2=> Internal RC oscillator -// <3=> USB clock -// <4=> RTC oscillator -// CLKOUTDIV: Selects clock divider for CLKOUT -// <1-16><#-1> -// CLKOUT_EN: CLKOUT enable control -// -// -// -*/ -#define CLOCK_SETUP 1 -#define SCS_Val 0x00000020 -#define CLKSRCSEL_Val 0x00000001 -#define PLL0_SETUP 1 -#define PLL0CFG_Val 0x00050063 -#define PLL1_SETUP 1 -#define PLL1CFG_Val 0x00000023 -#define CCLKCFG_Val 0x00000003 -#define USBCLKCFG_Val 0x00000000 -#define PCLKSEL0_Val 0x00000000 -#define PCLKSEL1_Val 0x00000000 -#define PCONP_Val 0x042887DE -#define CLKOUTCFG_Val 0x00000000 - - -/*--------------------- Flash Accelerator Configuration ---------------------- -// -// Flash Accelerator Configuration -// Reserved -// FLASHTIM: Flash Access Time -// <0=> 1 CPU clock (for CPU clock up to 20 MHz) -// <1=> 2 CPU clocks (for CPU clock up to 40 MHz) -// <2=> 3 CPU clocks (for CPU clock up to 60 MHz) -// <3=> 4 CPU clocks (for CPU clock up to 80 MHz) -// <4=> 5 CPU clocks (for CPU clock up to 100 MHz) -// <5=> 6 CPU clocks (for any CPU clock) -// -*/ -#define FLASH_SETUP 1 -#define FLASHCFG_Val 0x0000303A - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -/*---------------------------------------------------------------------------- - Check the register settings - *----------------------------------------------------------------------------*/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) -#define CHECK_RSVD(val, mask) (val & mask) - -/* Clock Configuration -------------------------------------------------------*/ -#if (CHECK_RSVD((SCS_Val), ~0x00000030)) - #error "SCS: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2)) - #error "CLKSRCSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF)) - #error "PLL0CFG: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) - #error "PLL1CFG: Invalid values of reserved bits!" -#endif - -#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2))) - #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!" -#endif - -#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F)) - #error "USBCLKCFG: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00)) - #error "PCLKSEL0: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300)) - #error "PCLKSEL1: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((PCONP_Val), 0x10100821)) - #error "PCONP: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) - #error "CLKOUTCFG: Invalid values of reserved bits!" -#endif - -/* Flash Accelerator Configuration -------------------------------------------*/ -#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F)) - #error "FLASHCFG: Invalid values of reserved bits!" -#endif - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (12000000UL) /* Oscillator frequency */ -#define OSC_CLK ( XTAL) /* Main oscillator frequency */ -#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */ -#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ - - -/* F_cco0 = (2 * M * F_in) / N */ -#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1) -#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1) -#define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N) -#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1) - -/* Determine core clock frequency according to settings */ - #if (PLL0_SETUP) - #if ((CLKSRCSEL_Val & 0x03) == 1) - #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV) - #elif ((CLKSRCSEL_Val & 0x03) == 2) - #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV) - #else - #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV) - #endif - #else - #if ((CLKSRCSEL_Val & 0x03) == 1) - #define __CORE_CLK (OSC_CLK / __CCLK_DIV) - #elif ((CLKSRCSEL_Val & 0x03) == 2) - #define __CORE_CLK (RTC_CLK / __CCLK_DIV) - #else - #define __CORE_CLK (IRC_OSC / __CCLK_DIV) - #endif - #endif - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ - - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ - /* Determine clock frequency according to clock register values */ - if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */ - switch (LPC_SC->CLKSRCSEL & 0x03) { - case 0: /* Int. RC oscillator => PLL0 */ - case 3: /* Reserved, default to Int. RC */ - SystemCoreClock = (IRC_OSC * - ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / - ((LPC_SC->CCLKCFG & 0xFF)+ 1)); - break; - case 1: /* Main oscillator => PLL0 */ - SystemCoreClock = (OSC_CLK * - ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / - ((LPC_SC->CCLKCFG & 0xFF)+ 1)); - break; - case 2: /* RTC oscillator => PLL0 */ - SystemCoreClock = (RTC_CLK * - ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / - ((LPC_SC->CCLKCFG & 0xFF)+ 1)); - break; - } - } else { - switch (LPC_SC->CLKSRCSEL & 0x03) { - case 0: /* Int. RC oscillator => PLL0 */ - case 3: /* Reserved, default to Int. RC */ - SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1); - break; - case 1: /* Main oscillator => PLL0 */ - SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); - break; - case 2: /* RTC oscillator => PLL0 */ - SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); - break; - } - } - -} -/* Exported types --------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -//extern unsigned long _sidata; /* start address for the initialization values of the .data section. defined in linker script */ -//extern unsigned long _sdata; /* start address for the .data section. defined in linker script */ -//extern unsigned long _edata; /* end address for the .data section. defined in linker script */ -// -//extern unsigned long _sbss; /* start address for the .bss section. defined in linker script */ -//extern unsigned long _ebss; /* end address for the .bss section. defined in linker script */ - -//void _init(void) -//{ -// unsigned long *pulSrc, *pulDest; -// -// // -// // Copy the data segment initializers from flash to SRAM in ROM mode -// // -//#if (__RAM_MODE__==0) -// pulSrc = &_sidata; -// for(pulDest = &_sdata; pulDest < &_edata; ) -// { -// *(pulDest++) = *(pulSrc++); -// } -//#endif -// -// -// // -// // Zero fill the bss segment. -// // -// for(pulDest = &_sbss; pulDest < &_ebss; ) -// { -// *(pulDest++) = 0; -// } -//} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) -{ - -#if (CLOCK_SETUP) /* Clock Setup */ - LPC_SC->SCS = SCS_Val; - if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ - while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ - } - - LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ - LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */ - LPC_SC->PCLKSEL1 = PCLKSEL1_Val; - -#if (PLL0_SETUP) - LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ - - LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - - LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */ - - LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */ -#endif - -#if (PLL1_SETUP) - LPC_SC->PLL1CFG = PLL1CFG_Val; - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - - LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ - - LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */ - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */ -#else - LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */ -#endif - LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ - - LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ -#endif - -#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ - LPC_SC->FLASHCFG = FLASHCFG_Val; -#endif -} diff --git a/bitbucket_lpc1768/CMSIS/system_LPC17xx.d b/bitbucket_lpc1768/CMSIS/system_LPC17xx.d deleted file mode 100644 index 2b7fdc4..0000000 --- a/bitbucket_lpc1768/CMSIS/system_LPC17xx.d +++ /dev/null @@ -1,8 +0,0 @@ -system_LPC17xx.o: CMSIS/system_LPC17xx.c CMSIS/LPC17xx.h CMSIS/core_cm3.h \ - CMSIS/system_LPC17xx.h - -CMSIS/LPC17xx.h: - -CMSIS/core_cm3.h: - -CMSIS/system_LPC17xx.h: diff --git a/bitbucket_lpc1768/CMSIS/system_LPC17xx.h b/bitbucket_lpc1768/CMSIS/system_LPC17xx.h deleted file mode 100755 index ba31c9a..0000000 --- a/bitbucket_lpc1768/CMSIS/system_LPC17xx.h +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************//** - * @file system_LPC17xx.h - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File - * for the NXP LPC17xx Device Series - * @version V1.02 - * @date 08. September 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __SYSTEM_LPC17xx_H -#define __SYSTEM_LPC17xx_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC17xx_H */ diff --git a/bitbucket_lpc1768/CMSIS/system_LPC17xx.o b/bitbucket_lpc1768/CMSIS/system_LPC17xx.o deleted file mode 100644 index e885d7c..0000000 Binary files a/bitbucket_lpc1768/CMSIS/system_LPC17xx.o and /dev/null differ diff --git a/bitbucket_lpc1768/LPC1768-flash.ld b/bitbucket_lpc1768/LPC1768-flash.ld deleted file mode 100644 index 68d07ed..0000000 --- a/bitbucket_lpc1768/LPC1768-flash.ld +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This is the NXP LPC1768 linker file for code running from flash. - * - * TODO: - * - handle the exotic input sections (e.g. glue and veneer, C++ sections) - * - add additional Ethernet and USB RAM memory regions (2x16k) - * - add boot ROM memory regions - * - * See also: http://bitbucket.org/jpc/lpc1768/ - * - * Copyright (c) 2010 LoEE - Jakub Piotr Cłapa - * This program is released under the new BSD license. - */ -OUTPUT_FORMAT("elf32-littlearm") -OUTPUT_ARCH(arm) - -ENTRY(Reset_Handler) - -MEMORY { - flash (rx) : ORIGIN = 0x00000000, LENGTH = 512K - ram (rwx) : ORIGIN = 0x10000000, LENGTH = 32K -} - -SECTIONS { - . = 0; - - .text : { - _stext = .; - KEEP(*(.cs3.interrupt_vector)) - *(.text*) - *(.rodata*) - . = ALIGN(4); - _etext = .; - } > flash - - .data : { - _sdata = .; - *(.data*) - _edata = .; - } > ram AT > flash - - .bss : { - _sbss = .; - *(.bss*) - . = ALIGN(4); - _ebss = .; - } > ram - - _sstack = ORIGIN(ram) + LENGTH(ram); -} diff --git a/bitbucket_lpc1768/Makefile b/bitbucket_lpc1768/Makefile deleted file mode 100644 index 348e0be..0000000 --- a/bitbucket_lpc1768/Makefile +++ /dev/null @@ -1,76 +0,0 @@ -# Copyright (c) 2008-2010 Jakub Piotr Cłapa -# This program is released under the new BSD license. -ARCH = /home/asbjorn/dev/armchain/arm-none-eabi/bin/arm-none-eabi -MBED_VOLUME = /Volumes/MBED - -# Tool definitions -CC = $(ARCH)-gcc -LD = $(ARCH)-ld -AR = $(ARCH)-ar -AS = $(ARCH)-as -CP = $(ARCH)-objcopy -OD = $(ARCH)-objdump -SIZE = $(ARCH)-size -RM = rm -Q = @./quiet "$@" - -# Flags -CFLAGS = -W -Wall -Os --std=gnu99 -fgnu89-inline -mcpu=cortex-m3 -mthumb -CFLAGS += -ffunction-sections -fdata-sections -ASFLAGS = -LDFLAGS = --gc-sections -CPFLAGS = -ODFLAGS = -x --syms -PRFLAGS ?= - -# Source files -LINKER_SCRIPT = LPC1768-flash.ld -CSRCS = startup.c $(wildcard CMSIS/*.c) -CSRCS += main.c -ASRCS = - - -OBJS = $(CSRCS:.c=.o) $(ASRCS:.s=.o) - -.PHONY: all size clean nuke - -all: main.bin main.hex - -isp: main.bin - @./quiet $< cp $^ $(MBED_VOLUME)/ - -size: main.elf - @$(SIZE) $< - -%.hex: %.elf - $Q $(CP) $(CPFLAGS) -O ihex $< $*.hex - -%.bin: %.elf - $Q $(CP) $(CPFLAGS) -O binary $< $*.bin - -main.elf: $(LINKER_SCRIPT) $(OBJS) - $Q $(LD) -Map $(@:.elf=.map) $(LDFLAGS) -T $^ -o $@ - $Q $(OD) $(ODFLAGS) $@ > $(@:.elf=.dump) - @$(SIZE) $@ - -%.o: %.c - @$(CC) -MM $< -MF $*.d -MP - $Q $(CC) -c $(CFLAGS) $< -o $@ - -%.o: %.S - $Q $(AS) $(ASFLAGS) $< -o $@ - -io-pin.h: io-pin.ss - $Q mzscheme $< > $@ - -clean: - @-rm -f *.elf quiet.log - @-\ -for D in "." "**"; do \ - rm -f $$D/*.o $$D/*.d $$D/*.lst $$D/*.dump $$D/*.map; \ -done - -nuke: clean - -rm -f *.hex *.bin - --include $(CSRCS:.c=.d) diff --git a/bitbucket_lpc1768/io-pin.h b/bitbucket_lpc1768/io-pin.h deleted file mode 100644 index 507ac4d..0000000 --- a/bitbucket_lpc1768/io-pin.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * IO functions for NXP LPC1768. (generated file, check io-pin.ss) - * - * See also: http://bitbucket.org/jpc/lpc1768/ - * - * Copyright (c) 2010 LoEE - Jakub Piotr Cłapa - * This program is released under the new BSD license. - */ -#ifndef IO_PIN_H -#define IO_PIN_H - -#include "CMSIS/LPC17xx.h" - -enum pin_port { -P0 = 0, -P1 = 32, -P2 = 64, -P3 = 96, -P4 = 128, -}; - -enum pin_dir { - PIN_IN = 0, - PIN_OUT = 1, -}; - -extern void invalid_pin_error () __attribute__((error ("Invalid IO pin number."))); - -extern __inline__ __attribute__((always_inline)) -int pin_read (int pin_no) -{ - switch(pin_no) { - case 0 ... 31: - return LPC_GPIO0->FIOPIN & (1 << (pin_no - 0)); - case 32 ... 63: - return LPC_GPIO1->FIOPIN & (1 << (pin_no - 32)); - case 64 ... 95: - return LPC_GPIO2->FIOPIN & (1 << (pin_no - 64)); - case 96 ... 127: - return LPC_GPIO3->FIOPIN & (1 << (pin_no - 96)); - case 128 ... 159: - return LPC_GPIO4->FIOPIN & (1 << (pin_no - 128)); - default: - invalid_pin_error (); - break; - } - return 0; -} - -extern __inline__ __attribute__((always_inline)) -void pin_write (int pin_no, int value) -{ - switch(pin_no) { - case 0 ... 31: - if (value) { - LPC_GPIO0->FIOSET = (1 << (pin_no - 0)); - } else { - LPC_GPIO0->FIOCLR = (1 << (pin_no - 0)); - } - break; - case 32 ... 63: - if (value) { - LPC_GPIO1->FIOSET = (1 << (pin_no - 32)); - } else { - LPC_GPIO1->FIOCLR = (1 << (pin_no - 32)); - } - break; - case 64 ... 95: - if (value) { - LPC_GPIO2->FIOSET = (1 << (pin_no - 64)); - } else { - LPC_GPIO2->FIOCLR = (1 << (pin_no - 64)); - } - break; - case 96 ... 127: - if (value) { - LPC_GPIO3->FIOSET = (1 << (pin_no - 96)); - } else { - LPC_GPIO3->FIOCLR = (1 << (pin_no - 96)); - } - break; - case 128 ... 159: - if (value) { - LPC_GPIO4->FIOSET = (1 << (pin_no - 128)); - } else { - LPC_GPIO4->FIOCLR = (1 << (pin_no - 128)); - } - break; - default: - invalid_pin_error (); - break; - } -} - -extern __inline__ __attribute__((always_inline)) -void pin_dir (int pin_no, enum pin_dir dir) -{ - switch(pin_no) { - case 0 ... 31: - if (dir == PIN_OUT) { - LPC_GPIO0->FIODIR |= (1 << (pin_no - 0)); - } else { - LPC_GPIO0->FIODIR &= (1 << (pin_no - 0)); - } - break; - case 32 ... 63: - if (dir == PIN_OUT) { - LPC_GPIO1->FIODIR |= (1 << (pin_no - 32)); - } else { - LPC_GPIO1->FIODIR &= (1 << (pin_no - 32)); - } - break; - case 64 ... 95: - if (dir == PIN_OUT) { - LPC_GPIO2->FIODIR |= (1 << (pin_no - 64)); - } else { - LPC_GPIO2->FIODIR &= (1 << (pin_no - 64)); - } - break; - case 96 ... 127: - if (dir == PIN_OUT) { - LPC_GPIO3->FIODIR |= (1 << (pin_no - 96)); - } else { - LPC_GPIO3->FIODIR &= (1 << (pin_no - 96)); - } - break; - case 128 ... 159: - if (dir == PIN_OUT) { - LPC_GPIO4->FIODIR |= (1 << (pin_no - 128)); - } else { - LPC_GPIO4->FIODIR &= (1 << (pin_no - 128)); - } - break; - default: - invalid_pin_error (); - break; - } -} - -#endif \ No newline at end of file diff --git a/bitbucket_lpc1768/io-pin.ss b/bitbucket_lpc1768/io-pin.ss deleted file mode 100644 index 5b8cda9..0000000 --- a/bitbucket_lpc1768/io-pin.ss +++ /dev/null @@ -1,76 +0,0 @@ -#lang scribble/text -@(define ports '(P0 P1 P2 P3 P4)) -@(define registers '(LPC_GPIO0 LPC_GPIO1 LPC_GPIO2 LPC_GPIO3 LPC_GPIO4)) -/* - * IO functions for NXP LPC1768. (generated file, check io-pin.ss) - * - * See also: http://bitbucket.org/jpc/lpc1768/ - * - * Copyright (c) 2010 LoEE - Jakub Piotr Cłapa - * This program is released under the new BSD license. - */ -#ifndef IO_PIN_H -#define IO_PIN_H - -#include "CMSIS/LPC17xx.h" - -enum pin_port { -@(add-newlines - (for/list ([i (in-naturals)] - [port ports]) - @list{@port = @(* i 32),})) -}; - -enum pin_dir { - PIN_IN = 0, - PIN_OUT = 1, -}; - -extern void invalid_pin_error () __attribute__((error ("Invalid IO pin number."))); - -@(define INLINE "extern __inline__ __attribute__((always_inline))") -@(define-syntax-rule (switch pin_no i register template) - @list{switch(pin_no) { - @(add-newlines - (for/list ([i (in-naturals)] - [register registers]) - @list{case @(* i 32) ... @(sub1 (* (add1 i) 32)): - @template})) - default: - invalid_pin_error (); - break; - }}) - -@INLINE -int pin_read (int pin_no) -{ - @(switch @{pin_no} i register - @list{return @|register|->FIOPIN & (1 << (pin_no - @(* i 32)));}) - return 0; -} - -@INLINE -void pin_write (int pin_no, int value) -{ - @(switch @{pin_no} i register - @list{if (value) { - @|register|->FIOSET = (1 << (pin_no - @(* i 32))); - } else { - @|register|->FIOCLR = (1 << (pin_no - @(* i 32))); - } - break;}) -} - -@INLINE -void pin_dir (int pin_no, enum pin_dir dir) -{ - @(switch @{pin_no} i register - @list{if (dir == PIN_OUT) { - @|register|->FIODIR @"|=" (1 << (pin_no - @(* i 32))); - } else { - @|register|->FIODIR @"&=" (1 << (pin_no - @(* i 32))); - } - break;}) -} - -#endif \ No newline at end of file diff --git a/bitbucket_lpc1768/lpcrc/Makefile b/bitbucket_lpc1768/lpcrc/Makefile deleted file mode 100644 index f7c03d3..0000000 --- a/bitbucket_lpc1768/lpcrc/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -CC = gcc -LD = gcc -LDFLAGS = -Wall -O4 -std=c99 -EXES = lpcrc - -all: $(EXES) - -% : %.c - $(LD) $(LDFLAGS) -o $@ $< - -clean: - rm -f $(EXES) diff --git a/bitbucket_lpc1768/lpcrc/lpcrc b/bitbucket_lpc1768/lpcrc/lpcrc deleted file mode 100755 index eb9515e..0000000 Binary files a/bitbucket_lpc1768/lpcrc/lpcrc and /dev/null differ diff --git a/bitbucket_lpc1768/lpcrc/lpcrc.c b/bitbucket_lpc1768/lpcrc/lpcrc.c deleted file mode 100644 index e811c45..0000000 --- a/bitbucket_lpc1768/lpcrc/lpcrc.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Software License Agreement (BSD License) - * - * Copyright (c) 2010, Roel Verdult - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holders nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY - * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include -#include - -#define BLOCK_COUNT 7 -#define BLOCK_LENGTH 4 -#define BLOCK_TOTAL (BLOCK_COUNT*BLOCK_LENGTH) - -typedef unsigned char byte_t; - -int main(int argc, char *argv[]) -{ - FILE* pf; - byte_t buf[BLOCK_TOTAL]; - uint32_t crc = 0; - uint32_t block; - - // Check for required arguments - if (argc < 2) - { - printf("syntax: lpcrc \n"); - return 1; - } - - // Try to open the supplied firmware - if ((pf = fopen(argv[1],"rb+")) == NULL) - { - printf("error: could not open file [%s] with write access\n",argv[1]); - return 1; - } - - // Read out the data blocks used for crc calculation - if (fread(buf,1,BLOCK_TOTAL,pf) != BLOCK_TOTAL) - { - printf("error: could not read required bytes\n"); - fclose(pf); - return 1; - } - - // Compute the crc value - for (block=0; block&2 - -rm -f quiet.log -"$@" 2>> quiet.log -RET=$? -# if we check $? we won't notice the warnings -if [ $RET -ne 0 -o -s quiet.log ]; then - echo "$@" >& 2 - if [ $RET -ne 0 ]; then - $RED >& 2 - else - $YELLOW >& 2 - fi - cat quiet.log >& 2 - $NORM &> 2 - - exit $RET -else - $GREEN >& 2 - printf "${MSG}\n" 1>&2 - $NORM >& 2 -fi -rm quiet.log -exit $RET diff --git a/bitbucket_lpc1768/startup.c b/bitbucket_lpc1768/startup.c deleted file mode 100644 index b1c6418..0000000 --- a/bitbucket_lpc1768/startup.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This is an ARM Cortex-M3 startup file for the NXP LPC1768. - * - * TODO: Add vendor (NXP) specific interrupt vectors. - * - * See also: http://bitbucket.org/jpc/lpc1768/ - * - * Copyright (c) 2010 LoEE - Jakub Piotr Cłapa - * This program is released under the new BSD license. - */ -#include "CMSIS/LPC17xx.h" - -// Dummy handler. -void Default_Handler (void) { while (1); } - -// Weakly bind all interrupt vectors to the dummy handler. -void __attribute__((weak)) Reset_Handler(void); -void __attribute__((weak)) NMI_Handler(void); -void __attribute__((weak)) HardFault_Handler(void); -void __attribute__((weak)) MemManage_Handler(void); -void __attribute__((weak)) BusFault_Handler(void); -void __attribute__((weak)) UsageFault_Handler(void); -void __attribute__((weak)) SVC_Handler(void); -void __attribute__((weak)) DebugMon_Handler(void); -void __attribute__((weak)) PendSV_Handler(void); -void __attribute__((weak)) SysTick_Handler(void); -#pragma weak NMI_Handler = Default_Handler -#pragma weak HardFault_Handler = Default_Handler -#pragma weak MemManage_Handler = Default_Handler -#pragma weak BusFault_Handler = Default_Handler -#pragma weak UsageFault_Handler = Default_Handler -#pragma weak SVC_Handler = Default_Handler -#pragma weak DebugMon_Handler = Default_Handler -#pragma weak PendSV_Handler = Default_Handler -#pragma weak SysTick_Handler = Default_Handler - -// Start of the stack (last RAM address; exported in the linker script) -extern void _sstack; - -// The signature of Cortex-M3 interrupt handlers. -typedef void (* const Interrupt_Handler_P)(void); - -// Interrupt vectors table -__attribute__ ((section(".cs3.interrupt_vector"))) -Interrupt_Handler_P interrupt_vectors[] = { - &_sstack, // the first word contains the initial - // stack pointer the hardware loads it - // to the SP register before the first - // instruction - // Standard Cortex-M3 interrupts: - Reset_Handler, - NMI_Handler, - HardFault_Handler, - MemManage_Handler, - BusFault_Handler, - UsageFault_Handler, - 0xefff7d26, - 0, - 0, - 0, - SVC_Handler, - DebugMon_Handler, - 0, - PendSV_Handler, - SysTick_Handler, - // Vendor specific interrupts for LPC1768: -}; - -extern int main (void); - -extern uint32_t _etext, _sdata, _edata, _sbss, _ebss; - -void -Reset_Handler(void) -{ - // Initialize clocks - SystemInit (); - - uint32_t *s, *d; - // Copy initialization data to RAM (.data section) - s = &_etext; - d = &_sdata; - while (d < &_edata) *d++ = *s++; - // Zero the remaining allocated RAM (.bss section) - d = &_sbss; - while (d < &_ebss) *d++ = 0; - - // Everything is ready. Run the user program. - main(); - while (1); -} diff --git a/bitbucket_lpc1768/startup.d b/bitbucket_lpc1768/startup.d deleted file mode 100644 index 1505e22..0000000 --- a/bitbucket_lpc1768/startup.d +++ /dev/null @@ -1,8 +0,0 @@ -startup.o: startup.c CMSIS/LPC17xx.h CMSIS/core_cm3.h \ - CMSIS/system_LPC17xx.h - -CMSIS/LPC17xx.h: - -CMSIS/core_cm3.h: - -CMSIS/system_LPC17xx.h: diff --git a/bitbucket_lpc1768/startup.o b/bitbucket_lpc1768/startup.o deleted file mode 100644 index 4c4ebc0..0000000 Binary files a/bitbucket_lpc1768/startup.o and /dev/null differ