-void sysinit() {
- // xtal_freq = 12000000;
-
- volatile int *scs;
- scs = (int *)0x400fc1a0;
- // enable main oscillator
- *scs = 0x20;
-
- // wait for oscillator to get ready
- while ((*scs & (1<<6)) == 0);
-
- volatile int *cclkcfg;
- cclkcfg = (int *)0x400FC104;
- // set clockdivider to 1/4x
- *cclkcfg = 0x03;
-
- // peripheral clocks (all set to 1/4x cclk)
- volatile int *pclksel0, *pclksel1;
- pclksel0=(int *)0x400FC1A8;
- *pclksel0 = 0;
- pclksel1=(int *)0x400FC1AC;
- *pclksel1 = 0;
-
- // main clock set (pll0)
- volatile int *clksrcsel;
- clksrcsel = (int *)0x400FC10C;
- *clksrcsel = 0x01;
-
- volatile int *pll0con, *pll0stat, *pll0feed, *pll0cfg;
- pll0con=(int*)0x400FC080;
- pll0stat=(int *)0x400FC088;
- // pll0feed : feed 0xAA followed by 0x55 to feed
- pll0feed=(int *)0x400FC08C;
- pll0cfg=(int *)0x400FC084;
-
- // FORMULA = FCCO = (2 * M * FIN) / N
- // as Xtal (FIN) is 12MHz, N = 6 , M = 25 gives 100 MHz
- // as both msel and nsel stores "N-1" store 24 and 5
- *pll0cfg = 24 | (5 << 16);
-
- // feed to set clock
- *pll0feed = 0xaa;
- *pll0feed = 0x55;
-
-
- // enable pll0
- *pll0con = 0x01;
- *pll0feed = 0xaa;
- *pll0feed = 0x55;
-
- // wait for enable
- while (!(*pll0stat & (1<<26)));
-
- // lock pll0
- *pll0con = 0x03;
- *pll0feed = 0xaa;
- *pll0feed = 0x55;
-
- // wait for lock
- while (!(*pll0stat & ((1<<25) | (1<<24))));
-
- volatile int *pll1con, *pll1cfg, *pll1stat, *pll1feed;
- pll1con=(int *)0x400FC0A0;
- pll1cfg=(int *)0x400FC0A4;
- pll1stat=(int *)0x400FC0A8;
- pll1feed=(int *)0x400FC0AC;
-
- // setup pll1 (multiplier 4, divider 6)
- *pll1cfg = 3 | (0x01 << 5);
-
- // enable pll1
- *pll1con = 0x01;
- *pll1feed = 0xaa;
- *pll1feed = 0x55;
- while (!(*pll1stat & (1<<10)));
-
- // connect pll1
- *pll1con = 0x03;
- *pll1feed = 0xaa;
- *pll1feed = 0x55;
- while (!(*pll1stat & ((1<< 9) | (1<< 8))));
-}
+void sysinit() {\r
+ // xtal_freq = 12000000;\r
+\r
+ volatile int *scs; \r
+ scs = (int *)0x400fc1a0;\r
+ // enable main oscillator\r
+ *scs = 0x20;\r
+\r
+ // wait for oscillator to get ready\r
+ while ((*scs & (1<<6)) == 0);\r
+\r
+ volatile int *cclkcfg; \r
+ cclkcfg = (int *)0x400FC104;\r
+ // set clockdivider to 1/4x\r
+ *cclkcfg = 0x03;\r
+\r
+ // peripheral clocks (all set to 1/4x cclk)\r
+ volatile int *pclksel0, *pclksel1;\r
+ pclksel0=(int *)0x400FC1A8;\r
+ *pclksel0 = 0;\r
+ pclksel1=(int *)0x400FC1AC;\r
+ *pclksel1 = 0;\r
+\r
+ // main clock set (pll0)\r
+ volatile int *clksrcsel;\r
+ clksrcsel = (int *)0x400FC10C;\r
+ *clksrcsel = 0x01;\r
+\r
+ volatile int *pll0con, *pll0stat, *pll0feed, *pll0cfg;\r
+ pll0con=(int*)0x400FC080;\r
+ pll0stat=(int *)0x400FC088;\r
+ // pll0feed : feed 0xAA followed by 0x55 to feed \r
+ pll0feed=(int *)0x400FC08C;\r
+ pll0cfg=(int *)0x400FC084;\r
+\r
+ // FORMULA = FCCO = (2 * M * FIN) / N\r
+ // as Xtal (FIN) is 12MHz, N = 6 , M = 25 gives 100 MHz\r
+ // as both msel and nsel stores "N-1" store 24 and 5\r
+ *pll0cfg = 24 | (5 << 16);\r
+\r
+ // feed to set clock\r
+ *pll0feed = 0xaa;\r
+ *pll0feed = 0x55;\r
+\r
+\r
+ // enable pll0\r
+ *pll0con = 0x01;\r
+ *pll0feed = 0xaa;\r
+ *pll0feed = 0x55;\r
+\r
+ // wait for enable\r
+ while (!(*pll0stat & (1<<26)));\r
+\r
+ // lock pll0\r
+ *pll0con = 0x03;\r
+ *pll0feed = 0xaa;\r
+ *pll0feed = 0x55;\r
+\r
+ // wait for lock\r
+ while (!(*pll0stat & ((1<<25) | (1<<24))));\r
+\r
+ volatile int *pll1con, *pll1cfg, *pll1stat, *pll1feed;\r
+ pll1con=(int *)0x400FC0A0;\r
+ pll1cfg=(int *)0x400FC0A4;\r
+ pll1stat=(int *)0x400FC0A8;\r
+ pll1feed=(int *)0x400FC0AC;\r
+\r
+ // setup pll1 (multiplier 4, divider 6)\r
+ *pll1cfg = 3 | (0x01 << 5);\r
+\r
+ // enable pll1\r
+ *pll1con = 0x01;\r
+ *pll1feed = 0xaa;\r
+ *pll1feed = 0x55;\r
+ while (!(*pll1stat & (1<<10)));\r
+\r
+ // connect pll1\r
+ *pll1con = 0x03;\r
+ *pll1feed = 0xaa;\r
+ *pll1feed = 0x55;\r
+ while (!(*pll1stat & ((1<< 9) | (1<< 8))));\r
+}\r