initial usb

[rapper.git] / new_cmsis / usb / usbreg.h

diff --git a/new_cmsis/usb/usbreg.h b/new_cmsis/usb/usbreg.h
new file mode 100755 (executable)
index 0000000..fe1d58d
--- /dev/null
+++ b/new_cmsis/usb/usbreg.h
@@ -0,0 +1,130 @@
+/*----------------------------------------------------------------------------\r
+ *      U S B  -  K e r n e l\r
+ *----------------------------------------------------------------------------\r
+ * Name:    usbreg.h\r
+ * Purpose: USB Hardware Layer Definitions for NXP LPC Family MCUs\r
+ * Version: V1.20\r
+ *----------------------------------------------------------------------------\r
+ *      This software is supplied "AS IS" without any warranties, express,\r
+ *      implied or statutory, including but not limited to the implied\r
+ *      warranties of fitness for purpose, satisfactory quality and\r
+ *      noninfringement. Keil extends you a royalty-free right to reproduce\r
+ *      and distribute executable files created using this software for use\r
+ *      on NXP Semiconductors LPC family microcontroller devices only. Nothing \r
+ *      else gives you the right to use this software.\r
+ *\r
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#ifndef __USBREG_H\r
+#define __USBREG_H\r
+\r
+/* Device Interrupt Bit Definitions */\r
+#define FRAME_INT           0x00000001\r
+#define EP_FAST_INT         0x00000002\r
+#define EP_SLOW_INT         0x00000004\r
+#define DEV_STAT_INT        0x00000008\r
+#define CCEMTY_INT          0x00000010\r
+#define CDFULL_INT          0x00000020\r
+#define RxENDPKT_INT        0x00000040\r
+#define TxENDPKT_INT        0x00000080\r
+#define EP_RLZED_INT        0x00000100\r
+#define ERR_INT             0x00000200\r
+\r
+/* Rx & Tx Packet Length Definitions */\r
+#define PKT_LNGTH_MASK      0x000003FF\r
+#define PKT_DV              0x00000400\r
+#define PKT_RDY             0x00000800\r
+\r
+/* USB Control Definitions */\r
+#define CTRL_RD_EN          0x00000001\r
+#define CTRL_WR_EN          0x00000002\r
+\r
+/* Command Codes */\r
+#define CMD_SET_ADDR        0x00D00500\r
+#define CMD_CFG_DEV         0x00D80500\r
+#define CMD_SET_MODE        0x00F30500\r
+#define CMD_RD_FRAME        0x00F50500\r
+#define DAT_RD_FRAME        0x00F50200\r
+#define CMD_RD_TEST         0x00FD0500\r
+#define DAT_RD_TEST         0x00FD0200\r
+#define CMD_SET_DEV_STAT    0x00FE0500\r
+#define CMD_GET_DEV_STAT    0x00FE0500\r
+#define DAT_GET_DEV_STAT    0x00FE0200\r
+#define CMD_GET_ERR_CODE    0x00FF0500\r
+#define DAT_GET_ERR_CODE    0x00FF0200\r
+#define CMD_RD_ERR_STAT     0x00FB0500\r
+#define DAT_RD_ERR_STAT     0x00FB0200\r
+#define DAT_WR_BYTE(x)     (0x00000100 | ((x) << 16))\r
+#define CMD_SEL_EP(x)      (0x00000500 | ((x) << 16))\r
+#define DAT_SEL_EP(x)      (0x00000200 | ((x) << 16))\r
+#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))\r
+#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))\r
+#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))\r
+#define CMD_CLR_BUF         0x00F20500\r
+#define DAT_CLR_BUF         0x00F20200\r
+#define CMD_VALID_BUF       0x00FA0500\r
+\r
+/* Device Address Register Definitions */\r
+#define DEV_ADDR_MASK       0x7F\r
+#define DEV_EN              0x80\r
+\r
+/* Device Configure Register Definitions */\r
+#define CONF_DVICE          0x01\r
+\r
+/* Device Mode Register Definitions */\r
+#define AP_CLK              0x01\r
+#define INAK_CI             0x02\r
+#define INAK_CO             0x04\r
+#define INAK_II             0x08\r
+#define INAK_IO             0x10\r
+#define INAK_BI             0x20\r
+#define INAK_BO             0x40\r
+\r
+/* Device Status Register Definitions */\r
+#define DEV_CON             0x01\r
+#define DEV_CON_CH          0x02\r
+#define DEV_SUS             0x04\r
+#define DEV_SUS_CH          0x08\r
+#define DEV_RST             0x10\r
+\r
+/* Error Code Register Definitions */\r
+#define ERR_EC_MASK         0x0F\r
+#define ERR_EA              0x10\r
+\r
+/* Error Status Register Definitions */\r
+#define ERR_PID             0x01\r
+#define ERR_UEPKT           0x02\r
+#define ERR_DCRC            0x04\r
+#define ERR_TIMOUT          0x08\r
+#define ERR_EOP             0x10\r
+#define ERR_B_OVRN          0x20\r
+#define ERR_BTSTF           0x40\r
+#define ERR_TGL             0x80\r
+\r
+/* Endpoint Select Register Definitions */\r
+#define EP_SEL_F            0x01\r
+#define EP_SEL_ST           0x02\r
+#define EP_SEL_STP          0x04\r
+#define EP_SEL_PO           0x08\r
+#define EP_SEL_EPN          0x10\r
+#define EP_SEL_B_1_FULL     0x20\r
+#define EP_SEL_B_2_FULL     0x40\r
+\r
+/* Endpoint Status Register Definitions */\r
+#define EP_STAT_ST          0x01\r
+#define EP_STAT_DA          0x20\r
+#define EP_STAT_RF_MO       0x40\r
+#define EP_STAT_CND_ST      0x80\r
+\r
+/* Clear Buffer Register Definitions */\r
+#define CLR_BUF_PO          0x01\r
+\r
+\r
+/* DMA Interrupt Bit Definitions */\r
+#define EOT_INT             0x01\r
+#define NDD_REQ_INT         0x02\r
+#define SYS_ERR_INT         0x04\r
+\r
+\r
+#endif  /* __USBREG_H */\r