-target remote localhost:3333\r
+target remote localhost:3333
+monitor reset init
+monitor reset halt
+symbol-file rapper.elf
-PROJECT=rapper\r
-PLATFORM ?= arm-none-eabi\r
-LDFLAGS=--gc-sections -g -T LPC1768-flash.ld\r
-CFLAGS=-W -Wall --std=gnu99 -fgnu89-inline -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -I. -g\r
-#CFLAGS+=-Os\r
-\r
-# objects are separated by space\r
-OBJECTS=startup.o system_LPC17xx.o main.o core_cm3.o\r
-\r
-\r
-all: $(PROJECT).elf\r
-\r
-$(PROJECT).elf: $(OBJECTS)\r
- $(PLATFORM)-ld -Map $(PROJECT).map $(LDFLAGS) $(OBJECTS) -o $@\r
-\r
-%.o: %.c\r
- $(PLATFORM)-gcc -MM $< -MF $(patsubst %.o,%.d,$@) -MP\r
- $(PLATFORM)-gcc $(CFLAGS) -c $< -o $@\r
-\r
-.PHONY: clean gdb\r
-\r
-clean:\r
- rm -f $(PROJECT).elf $(OBJECTS) $(OBJECTS:.o=.d) $(PROJECT).map\r
-\r
-gdb:\r
- $(PLATFORM)-gdb $(PROJECT).elf\r
+PROJECT=rapper
+PLATFORM ?= arm-none-eabi
+BOARD?=lpc1768
+BPATH=boards/$(BOARD)
+LDFLAGS=--gc-sections -g -T $(BPATH)/flash.ld
+CFLAGS=-W -Wall --std=gnu99 -fgnu89-inline -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -I$(BPATH) -I. -g
+#CFLAGS+=-Os
+
+# objects are separated by space
+USB_OBJS=usb/serial.o usb/core.o usb/desc.o usb/hw.o usb/user.o usb/vcom.o usb/cdcuser.o
+BOARD_OBJS=$(BPATH)/startup.o $(BPATH)/system.o boards/cortex_m3/core_cm3.o
+OBJECTS=main.o $(BOARD_OBJS) $(USB_OBJS)
+
+
+all: crc
+
+$(PROJECT).elf: $(OBJECTS)
+ $(PLATFORM)-ld -Map $(PROJECT).map $(LDFLAGS) $(OBJECTS) -o $@
+
+%.bin: %.elf
+ $(PLATFORM)-objcopy -O binary $< $*.bin
+
+%.o: %.c
+ $(PLATFORM)-gcc -MM $< -MF $(patsubst %.o,%.d,$@) -MP
+ $(PLATFORM)-gcc $(CFLAGS) -c $< -o $@
+
+.PHONY: clean gdb crc
+
+clean:
+ rm -f $(PROJECT).elf $(OBJECTS) $(OBJECTS:.o=.d) $(PROJECT).map
+
+gdb:
+ $(PLATFORM)-gdb $(PROJECT).elf
+
+crc: $(PROJECT).bin
+ ../tools/lpcrc/lpcrc.sh $(PROJECT).bin $(BPATH)/startup.c
-/******************************************************************************\r
- * @file: core_cm3.c\r
- * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File\r
- * @version: V1.20\r
- * @date: 22. May 2009\r
- *----------------------------------------------------------------------------\r
- *\r
- * Copyright (C) 2009 ARM Limited. All rights reserved.\r
- *\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-Mx \r
- * processor based microcontrollers. This file can be freely distributed \r
- * within development tools that are supporting such ARM based processors. \r
- *\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-\r
-\r
-#include <stdint.h>\r
-\r
-\r
-/* define compiler specific symbols */\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for armcc */\r
- #define __INLINE __inline /*!< inline keyword for armcc */\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for iarcc */\r
- #define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for gcc */\r
- #define __INLINE inline /*!< inline keyword for gcc */\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
-\r
-#endif\r
-\r
-\r
-\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-__ASM uint32_t __get_PSP(void)\r
-{\r
- mrs r0, psp\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param uint32_t Process Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-__ASM void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- msr psp, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-__ASM uint32_t __get_MSP(void)\r
-{\r
- mrs r0, msp\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param uint32_t Main Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-__ASM void __set_MSP(uint32_t mainStackPointer)\r
-{\r
- msr msp, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param uint16_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-__ASM uint32_t __REV16(uint16_t value)\r
-{\r
- rev16 r0, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param int16_t value to reverse\r
- * @return int32_t reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-__ASM int32_t __REVSH(int16_t value)\r
-{\r
- revsh r0, r0\r
- bx lr\r
-}\r
-\r
-\r
-#if (__ARMCC_VERSION < 400000)\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-__ASM void __CLREX(void)\r
-{\r
- clrex\r
-}\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @param none\r
- * @return uint32_t BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-__ASM uint32_t __get_BASEPRI(void)\r
-{\r
- mrs r0, basepri\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param uint32_t BasePriority\r
- * @return none\r
- *\r
- * Set the base priority register\r
- */\r
-__ASM void __set_BASEPRI(uint32_t basePri)\r
-{\r
- msr basepri, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @param none\r
- * @return uint32_t PriMask\r
- *\r
- * Return the state of the priority mask bit from the priority mask\r
- * register\r
- */\r
-__ASM uint32_t __get_PRIMASK(void)\r
-{\r
- mrs r0, primask\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param uint32_t PriMask\r
- * @return none\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-__ASM void __set_PRIMASK(uint32_t priMask)\r
-{\r
- msr primask, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @param none\r
- * @return uint32_t FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-__ASM uint32_t __get_FAULTMASK(void)\r
-{\r
- mrs r0, faultmask\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param uint32_t faultMask value\r
- * @return none\r
- *\r
- * Set the fault mask register\r
- */\r
-__ASM void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- msr faultmask, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- * \r
- * @param none\r
- * @return uint32_t Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-__ASM uint32_t __get_CONTROL(void)\r
-{\r
- mrs r0, control\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param uint32_t Control value\r
- * @return none\r
- *\r
- * Set the control register\r
- */\r
-__ASM void __set_CONTROL(uint32_t control)\r
-{\r
- msr control, r0\r
- bx lr\r
-}\r
-\r
-#endif /* __ARMCC_VERSION */ \r
-\r
-\r
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
-#pragma diag_suppress=Pe940\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-uint32_t __get_PSP(void)\r
-{\r
- __ASM("mrs r0, psp");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param uint32_t Process Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- __ASM("msr psp, r0");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-uint32_t __get_MSP(void)\r
-{\r
- __ASM("mrs r0, msp");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param uint32_t Main Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- __ASM("msr msp, r0");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param uint16_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-uint32_t __REV16(uint16_t value)\r
-{\r
- __ASM("rev16 r0, r0");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param uint32_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-uint32_t __RBIT(uint32_t value)\r
-{\r
- __ASM("rbit r0, r0");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint8_t* address\r
- * @return uint8_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-uint8_t __LDREXB(uint8_t *addr)\r
-{\r
- __ASM("ldrexb r0, [r0]");\r
- __ASM("bx lr"); \r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint16_t* address\r
- * @return uint16_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-uint16_t __LDREXH(uint16_t *addr)\r
-{\r
- __ASM("ldrexh r0, [r0]");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint32_t* address\r
- * @return uint32_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-uint32_t __LDREXW(uint32_t *addr)\r
-{\r
- __ASM("ldrex r0, [r0]");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint8_t *address\r
- * @param uint8_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
-{\r
- __ASM("strexb r0, r0, [r1]");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint16_t *address\r
- * @param uint16_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
-{\r
- __ASM("strexh r0, r0, [r1]");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint32_t *address\r
- * @param uint32_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
-{\r
- __ASM("strex r0, r0, [r1]");\r
- __ASM("bx lr");\r
-}\r
-\r
-#pragma diag_default=Pe940\r
-\r
-\r
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-uint32_t __get_PSP(void) __attribute__( ( naked ) );\r
-uint32_t __get_PSP(void)\r
-{\r
- uint32_t result=0;\r
-\r
- __ASM volatile ("MRS %0, psp\n\t" \r
- "MOV r0, %0 \n\t"\r
- "BX lr \n\t" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param uint32_t Process Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );\r
-void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- __ASM volatile ("MSR psp, %0\n\t"\r
- "BX lr \n\t" : : "r" (topOfProcStack) );\r
-}\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-uint32_t __get_MSP(void) __attribute__( ( naked ) );\r
-uint32_t __get_MSP(void)\r
-{\r
- uint32_t result=0;\r
-\r
- __ASM volatile ("MRS %0, msp\n\t" \r
- "MOV r0, %0 \n\t"\r
- "BX lr \n\t" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param uint32_t Main Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );\r
-void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- __ASM volatile ("MSR msp, %0\n\t"\r
- "BX lr \n\t" : : "r" (topOfMainStack) );\r
-}\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @param none\r
- * @return uint32_t BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-uint32_t __get_BASEPRI(void)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param uint32_t BasePriority\r
- * @return none\r
- *\r
- * Set the base priority register\r
- */\r
-void __set_BASEPRI(uint32_t value)\r
-{\r
- __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
-}\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @param none\r
- * @return uint32_t PriMask\r
- *\r
- * Return the state of the priority mask bit from the priority mask\r
- * register\r
- */\r
-uint32_t __get_PRIMASK(void)\r
-{\r
- uint32_t result=0;\r
-\r
- __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param uint32_t PriMask\r
- * @return none\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-void __set_PRIMASK(uint32_t priMask)\r
-{\r
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
-}\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @param none\r
- * @return uint32_t FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-uint32_t __get_FAULTMASK(void)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param uint32_t faultMask value\r
- * @return none\r
- *\r
- * Set the fault mask register\r
- */\r
-void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in integer value\r
- *\r
- * @param uint32_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in integer value\r
- */\r
-uint32_t __REV(uint32_t value)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param uint16_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-uint32_t __REV16(uint16_t value)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param int32_t value to reverse\r
- * @return int32_t reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-int32_t __REVSH(int16_t value)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param uint32_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-uint32_t __RBIT(uint32_t value)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint8_t* address\r
- * @return uint8_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-uint8_t __LDREXB(uint8_t *addr)\r
-{\r
- uint8_t result=0;\r
- \r
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint16_t* address\r
- * @return uint16_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-uint16_t __LDREXH(uint16_t *addr)\r
-{\r
- uint16_t result=0;\r
- \r
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint32_t* address\r
- * @return uint32_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-uint32_t __LDREXW(uint32_t *addr)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint8_t *address\r
- * @param uint8_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint16_t *address\r
- * @param uint16_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint32_t *address\r
- * @param uint32_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- * \r
- * @param none\r
- * @return uint32_t Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-uint32_t __get_CONTROL(void)\r
-{\r
- uint32_t result=0;\r
-\r
- __ASM volatile ("MRS %0, control" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param uint32_t Control value\r
- * @return none\r
- *\r
- * Set the control register\r
- */\r
-void __set_CONTROL(uint32_t control)\r
-{\r
- __ASM volatile ("MSR control, %0" : : "r" (control) );\r
-}\r
-\r
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all instrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-#endif\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
+/******************************************************************************
+ * @file: core_cm3.c
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File
+ * @version: V1.20
+ * @date: 22. May 2009
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+
+#include <stdint.h>
+
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for armcc */
+ #define __INLINE __inline /*!< inline keyword for armcc */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for iarcc */
+ #define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for gcc */
+ #define __INLINE inline /*!< inline keyword for gcc */
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+
+#endif
+
+
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+__ASM uint32_t __get_PSP(void)
+{
+ mrs r0, psp
+ bx lr
+}
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+__ASM void __set_PSP(uint32_t topOfProcStack)
+{
+ msr psp, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+__ASM uint32_t __get_MSP(void)
+{
+ mrs r0, msp
+ bx lr
+}
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+__ASM void __set_MSP(uint32_t mainStackPointer)
+{
+ msr msp, r0
+ bx lr
+}
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+__ASM uint32_t __REV16(uint16_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+
+/**
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param int16_t value to reverse
+ * @return int32_t reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+__ASM int32_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief Remove the exclusive lock created by ldrex
+ *
+ * @param none
+ * @return none
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+__ASM void __CLREX(void)
+{
+ clrex
+}
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @param none
+ * @return uint32_t BasePriority
+ *
+ * Return the content of the base priority register
+ */
+__ASM uint32_t __get_BASEPRI(void)
+{
+ mrs r0, basepri
+ bx lr
+}
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param uint32_t BasePriority
+ * @return none
+ *
+ * Set the base priority register
+ */
+__ASM void __set_BASEPRI(uint32_t basePri)
+{
+ msr basepri, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @param none
+ * @return uint32_t PriMask
+ *
+ * Return the state of the priority mask bit from the priority mask
+ * register
+ */
+__ASM uint32_t __get_PRIMASK(void)
+{
+ mrs r0, primask
+ bx lr
+}
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param uint32_t PriMask
+ * @return none
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+__ASM void __set_PRIMASK(uint32_t priMask)
+{
+ msr primask, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @param none
+ * @return uint32_t FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+__ASM uint32_t __get_FAULTMASK(void)
+{
+ mrs r0, faultmask
+ bx lr
+}
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param uint32_t faultMask value
+ * @return none
+ *
+ * Set the fault mask register
+ */
+__ASM void __set_FAULTMASK(uint32_t faultMask)
+{
+ msr faultmask, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @param none
+ * @return uint32_t Control value
+ *
+ * Return the content of the control register
+ */
+__ASM uint32_t __get_CONTROL(void)
+{
+ mrs r0, control
+ bx lr
+}
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param uint32_t Control value
+ * @return none
+ *
+ * Set the control register
+ */
+__ASM void __set_CONTROL(uint32_t control)
+{
+ msr control, r0
+ bx lr
+}
+
+#endif /* __ARMCC_VERSION */
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+#pragma diag_suppress=Pe940
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void)
+{
+ __ASM("mrs r0, psp");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM("msr psp, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void)
+{
+ __ASM("mrs r0, msp");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM("msr msp, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+ __ASM("rev16 r0, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+ __ASM("rbit r0, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint8_t* address
+ * @return uint8_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+ __ASM("ldrexb r0, [r0]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint16_t* address
+ * @return uint16_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+ __ASM("ldrexh r0, [r0]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint32_t* address
+ * @return uint32_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+ __ASM("ldrex r0, [r0]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint8_t *address
+ * @param uint8_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+ __ASM("strexb r0, r0, [r1]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint16_t *address
+ * @param uint16_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+ __ASM("strexh r0, r0, [r1]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint32_t *address
+ * @param uint32_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+ __ASM("strex r0, r0, [r1]");
+ __ASM("bx lr");
+}
+
+#pragma diag_default=Pe940
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void) __attribute__( ( naked ) );
+uint32_t __get_PSP(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, psp\n\t"
+ "MOV r0, %0 \n\t"
+ "BX lr \n\t" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
+void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n\t"
+ "BX lr \n\t" : : "r" (topOfProcStack) );
+}
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void) __attribute__( ( naked ) );
+uint32_t __get_MSP(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, msp\n\t"
+ "MOV r0, %0 \n\t"
+ "BX lr \n\t" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
+void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n\t"
+ "BX lr \n\t" : : "r" (topOfMainStack) );
+}
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @param none
+ * @return uint32_t BasePriority
+ *
+ * Return the content of the base priority register
+ */
+uint32_t __get_BASEPRI(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param uint32_t BasePriority
+ * @return none
+ *
+ * Set the base priority register
+ */
+void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @param none
+ * @return uint32_t PriMask
+ *
+ * Return the state of the priority mask bit from the priority mask
+ * register
+ */
+uint32_t __get_PRIMASK(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param uint32_t PriMask
+ * @return none
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @param none
+ * @return uint32_t FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param uint32_t faultMask value
+ * @return none
+ *
+ * Set the fault mask register
+ */
+void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+/**
+ * @brief Reverse byte order in integer value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in integer value
+ */
+uint32_t __REV(uint32_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param int32_t value to reverse
+ * @return int32_t reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+int32_t __REVSH(int16_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint8_t* address
+ * @return uint8_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+ uint8_t result=0;
+
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint16_t* address
+ * @return uint16_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+ uint16_t result=0;
+
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint32_t* address
+ * @return uint32_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint8_t *address
+ * @param uint8_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint16_t *address
+ * @param uint16_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint32_t *address
+ * @param uint32_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @param none
+ * @return uint32_t Control value
+ *
+ * Return the content of the control register
+ */
+uint32_t __get_CONTROL(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param uint32_t Control value
+ * @return none
+ *
+ * Set the control register
+ */
+void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
-/******************************************************************************\r
- * @file: core_cm3.h\r
- * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
- * @version: V1.20\r
- * @date: 22. May 2009\r
- *----------------------------------------------------------------------------\r
- *\r
- * Copyright (C) 2009 ARM Limited. All rights reserved.\r
- *\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-Mx \r
- * processor based microcontrollers. This file can be freely distributed \r
- * within development tools that are supporting such ARM based processors. \r
- *\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-#ifndef __CM3_CORE_H__\r
-#define __CM3_CORE_H__\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif \r
-\r
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0x03) /*!< Cortex core */\r
-\r
-/**\r
- * Lint configuration \n\r
- * ----------------------- \n\r
- *\r
- * The following Lint messages will be suppressed and not shown: \n\r
- * \n\r
- * --- Error 10: --- \n\r
- * register uint32_t __regBasePri __asm("basepri"); \n\r
- * Error 10: Expecting ';' \n\r
- * \n\r
- * --- Error 530: --- \n\r
- * return(__regBasePri); \n\r
- * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n\r
- * \n\r
- * --- Error 550: --- \n\r
- * __regBasePri = (basePri & 0x1ff); \n\r
- * } \n\r
- * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n\r
- * \n\r
- * --- Error 754: --- \n\r
- * uint32_t RESERVED0[24]; \n\r
- * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n\r
- * \n\r
- * --- Error 750: --- \n\r
- * #define __CM3_CORE_H__ \n\r
- * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n\r
- * \n\r
- * --- Error 528: --- \n\r
- * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
- * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n\r
- * \n\r
- * --- Error 751: --- \n\r
- * } InterruptType_Type; \n\r
- * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n\r
- * \n\r
- * \n\r
- * Note: To re-enable a Message, insert a space before 'lint' * \n\r
- *\r
- */\r
-\r
-/*lint -save */\r
-/*lint -e10 */\r
-/*lint -e530 */\r
-/*lint -e550 */\r
-/*lint -e754 */\r
-/*lint -e750 */\r
-/*lint -e528 */\r
-/*lint -e751 */\r
-\r
-\r
-#include <stdint.h> /* Include standard types */\r
-\r
-#if defined (__ICCARM__)\r
- #include <intrinsics.h> /* IAR Intrinsics */\r
-#endif\r
-\r
-\r
-#ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */\r
-#endif\r
-\r
-\r
-\r
-\r
-/**\r
- * IO definitions\r
- *\r
- * define access restrictions to peripheral registers\r
- */\r
-\r
-#ifdef __cplusplus\r
-#define __I volatile /*!< defines 'read only' permissions */\r
-#else\r
-#define __I volatile const /*!< defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< defines 'write only' permissions */\r
-#define __IO volatile /*!< defines 'read / write' permissions */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- ******************************************************************************/\r
-\r
-\r
-/* System Reset */\r
-#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */\r
-#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */\r
-#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */\r
-#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */\r
-\r
-/* Core Debug */\r
-#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */\r
-#define ITM_TCR_ITMENA 1 /*!< ITM enable */\r
-\r
-\r
-\r
-\r
-/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */\r
-typedef struct\r
-{\r
- __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24];\r
- __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24];\r
- __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24];\r
- __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24];\r
- __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */\r
- uint32_t RESERVED4[56];\r
- __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */\r
- uint32_t RESERVED5[644];\r
- __O uint32_t STIR; /*!< Software Trigger Interrupt Register */\r
-} NVIC_Type;\r
-\r
-\r
-/* memory mapping struct for System Control Block */\r
-typedef struct\r
-{\r
- __I uint32_t CPUID; /*!< CPU ID Base Register */\r
- __IO uint32_t ICSR; /*!< Interrupt Control State Register */\r
- __IO uint32_t VTOR; /*!< Vector Table Offset Register */\r
- __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */\r
- __IO uint32_t SCR; /*!< System Control Register */\r
- __IO uint32_t CCR; /*!< Configuration Control Register */\r
- __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IO uint32_t SHCSR; /*!< System Handler Control and State Register */\r
- __IO uint32_t CFSR; /*!< Configurable Fault Status Register */\r
- __IO uint32_t HFSR; /*!< Hard Fault Status Register */\r
- __IO uint32_t DFSR; /*!< Debug Fault Status Register */\r
- __IO uint32_t MMFAR; /*!< Mem Manage Address Register */\r
- __IO uint32_t BFAR; /*!< Bus Fault Address Register */\r
- __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */\r
- __I uint32_t PFR[2]; /*!< Processor Feature Register */\r
- __I uint32_t DFR; /*!< Debug Feature Register */\r
- __I uint32_t ADR; /*!< Auxiliary Feature Register */\r
- __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */\r
- __I uint32_t ISAR[5]; /*!< ISA Feature Register */\r
-} SCB_Type;\r
-\r
-\r
-/* memory mapping struct for SysTick */\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /*!< SysTick Control and Status Register */\r
- __IO uint32_t LOAD; /*!< SysTick Reload Value Register */\r
- __IO uint32_t VAL; /*!< SysTick Current Value Register */\r
- __I uint32_t CALIB; /*!< SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-\r
-/* memory mapping structur for ITM */\r
-typedef struct\r
-{\r
- __O union \r
- {\r
- __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */\r
- __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */\r
- __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */\r
- } PORT [32]; /*!< ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864];\r
- __IO uint32_t TER; /*!< ITM Trace Enable Register */\r
- uint32_t RESERVED1[15];\r
- __IO uint32_t TPR; /*!< ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15];\r
- __IO uint32_t TCR; /*!< ITM Trace Control Register */\r
- uint32_t RESERVED3[29];\r
- __IO uint32_t IWR; /*!< ITM Integration Write Register */\r
- __IO uint32_t IRR; /*!< ITM Integration Read Register */\r
- __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43];\r
- __IO uint32_t LAR; /*!< ITM Lock Access Register */\r
- __IO uint32_t LSR; /*!< ITM Lock Status Register */\r
- uint32_t RESERVED5[6];\r
- __I uint32_t PID4; /*!< ITM Product ID Registers */\r
- __I uint32_t PID5;\r
- __I uint32_t PID6;\r
- __I uint32_t PID7;\r
- __I uint32_t PID0;\r
- __I uint32_t PID1;\r
- __I uint32_t PID2;\r
- __I uint32_t PID3;\r
- __I uint32_t CID0;\r
- __I uint32_t CID1;\r
- __I uint32_t CID2;\r
- __I uint32_t CID3;\r
-} ITM_Type;\r
-\r
-\r
-/* memory mapped struct for Interrupt Type */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0;\r
- __I uint32_t ICTR; /*!< Interrupt Control Type Register */\r
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
- __IO uint32_t ACTLR; /*!< Auxiliary Control Register */\r
-#else\r
- uint32_t RESERVED1;\r
-#endif\r
-} InterruptType_Type;\r
-\r
-\r
-/* Memory Protection Unit */\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
-typedef struct\r
-{\r
- __I uint32_t TYPE; /*!< MPU Type Register */\r
- __IO uint32_t CTRL; /*!< MPU Control Register */\r
- __IO uint32_t RNR; /*!< MPU Region RNRber Register */\r
- __IO uint32_t RBAR; /*!< MPU Region Base Address Register */\r
- __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */\r
- __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */\r
- __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */\r
- __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-#endif\r
-\r
-\r
-/* Core Debug Register */\r
-typedef struct\r
-{\r
- __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */\r
- __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */\r
- __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */\r
- __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-\r
-/* Memory mapping of Cortex-M3 Hardware */\r
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000) /*!< ITM Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */\r
-\r
-#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
- #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- ******************************************************************************/\r
-\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
-\r
-#endif\r
-\r
-\r
-/* ################### Compiler specific Intrinsics ########################### */\r
-\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-#define __enable_fault_irq __enable_fiq\r
-#define __disable_fault_irq __disable_fiq\r
-\r
-#define __NOP __nop\r
-#define __WFI __wfi\r
-#define __WFE __wfe\r
-#define __SEV __sev\r
-#define __ISB() __isb(0)\r
-#define __DSB() __dsb(0)\r
-#define __DMB() __dmb(0)\r
-#define __REV __rev\r
-#define __RBIT __rbit\r
-#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))\r
-#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))\r
-#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))\r
-#define __STREXB(value, ptr) __strex(value, ptr)\r
-#define __STREXH(value, ptr) __strex(value, ptr)\r
-#define __STREXW(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
-/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
-/* intrinsic void __enable_irq(); */\r
-/* intrinsic void __disable_irq(); */\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param uint32_t Process Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param uint32_t Main Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param uint16_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/*\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param int16_t value to reverse\r
- * @return int32_t reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-extern int32_t __REVSH(int16_t value);\r
-\r
-\r
-#if (__ARMCC_VERSION < 400000)\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-extern void __CLREX(void);\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @param none\r
- * @return uint32_t BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-extern uint32_t __get_BASEPRI(void);\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param uint32_t BasePriority\r
- * @return none\r
- *\r
- * Set the base priority register\r
- */\r
-extern void __set_BASEPRI(uint32_t basePri);\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @param none\r
- * @return uint32_t PriMask\r
- *\r
- * Return the state of the priority mask bit from the priority mask\r
- * register\r
- */\r
-extern uint32_t __get_PRIMASK(void);\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param uint32_t PriMask\r
- * @return none\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-extern void __set_PRIMASK(uint32_t priMask);\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @param none\r
- * @return uint32_t FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-extern uint32_t __get_FAULTMASK(void);\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param uint32_t faultMask value\r
- * @return none\r
- *\r
- * Set the fault mask register\r
- */\r
-extern void __set_FAULTMASK(uint32_t faultMask);\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- * \r
- * @param none\r
- * @return uint32_t Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-extern uint32_t __get_CONTROL(void);\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param uint32_t Control value\r
- * @return none\r
- *\r
- * Set the control register\r
- */\r
-extern void __set_CONTROL(uint32_t control);\r
-\r
-#else /* (__ARMCC_VERSION >= 400000) */\r
-\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-#define __CLREX __clrex\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @param none\r
- * @return uint32_t BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-static __INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- return(__regBasePri);\r
-}\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param uint32_t BasePriority\r
- * @return none\r
- *\r
- * Set the base priority register\r
- */\r
-static __INLINE void __set_BASEPRI(uint32_t basePri)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- __regBasePri = (basePri & 0x1ff);\r
-}\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @param none\r
- * @return uint32_t PriMask\r
- *\r
- * Return the state of the priority mask bit from the priority mask\r
- * register\r
- */\r
-static __INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- return(__regPriMask);\r
-}\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param uint32_t PriMask\r
- * @return none\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-static __INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- __regPriMask = (priMask);\r
-}\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @param none\r
- * @return uint32_t FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-static __INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- return(__regFaultMask);\r
-}\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param uint32_t faultMask value\r
- * @return none\r
- *\r
- * Set the fault mask register\r
- */\r
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- __regFaultMask = (faultMask & 1);\r
-}\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- * \r
- * @param none\r
- * @return uint32_t Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-static __INLINE uint32_t __get_CONTROL(void)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- return(__regControl);\r
-}\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param uint32_t Control value\r
- * @return none\r
- *\r
- * Set the control register\r
- */\r
-static __INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- __regControl = control;\r
-}\r
-\r
-#endif /* __ARMCC_VERSION */ \r
-\r
-\r
-\r
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-\r
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */\r
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */\r
-\r
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }\r
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }\r
-\r
-#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */ \r
-static __INLINE void __WFI() { __ASM ("wfi"); }\r
-static __INLINE void __WFE() { __ASM ("wfe"); }\r
-static __INLINE void __SEV() { __ASM ("sev"); }\r
-static __INLINE void __CLREX() { __ASM ("clrex"); }\r
-\r
-/* intrinsic void __ISB(void) */\r
-/* intrinsic void __DSB(void) */\r
-/* intrinsic void __DMB(void) */\r
-/* intrinsic void __set_PRIMASK(); */\r
-/* intrinsic void __get_PRIMASK(); */\r
-/* intrinsic void __set_FAULTMASK(); */\r
-/* intrinsic void __get_FAULTMASK(); */\r
-/* intrinsic uint32_t __REV(uint32_t value); */\r
-/* intrinsic uint32_t __REVSH(uint32_t value); */\r
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
-/* intrinsic unsigned long __LDREX(unsigned long *); */\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param uint32_t Process Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param uint32_t Main Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param uint16_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param uint32_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-extern uint32_t __RBIT(uint32_t value);\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint8_t* address\r
- * @return uint8_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint8_t __LDREXB(uint8_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint16_t* address\r
- * @return uint16_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint16_t __LDREXH(uint16_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint32_t* address\r
- * @return uint32_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint32_t __LDREXW(uint32_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint8_t *address\r
- * @param uint8_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint16_t *address\r
- * @param uint16_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint32_t *address\r
- * @param uint32_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
-\r
-\r
-\r
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }\r
-static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }\r
-\r
-static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }\r
-static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }\r
-\r
-static __INLINE void __NOP() { __ASM volatile ("nop"); }\r
-static __INLINE void __WFI() { __ASM volatile ("wfi"); }\r
-static __INLINE void __WFE() { __ASM volatile ("wfe"); }\r
-static __INLINE void __SEV() { __ASM volatile ("sev"); }\r
-static __INLINE void __ISB() { __ASM volatile ("isb"); }\r
-static __INLINE void __DSB() { __ASM volatile ("dsb"); }\r
-static __INLINE void __DMB() { __ASM volatile ("dmb"); }\r
-static __INLINE void __CLREX() { __ASM volatile ("clrex"); }\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param uint32_t Process Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param uint32_t Main Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @param none\r
- * @return uint32_t BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-extern uint32_t __get_BASEPRI(void);\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param uint32_t BasePriority\r
- * @return none\r
- *\r
- * Set the base priority register\r
- */\r
-extern void __set_BASEPRI(uint32_t basePri);\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @param none\r
- * @return uint32_t PriMask\r
- *\r
- * Return the state of the priority mask bit from the priority mask\r
- * register\r
- */\r
-extern uint32_t __get_PRIMASK(void);\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param uint32_t PriMask\r
- * @return none\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-extern void __set_PRIMASK(uint32_t priMask);\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @param none\r
- * @return uint32_t FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-extern uint32_t __get_FAULTMASK(void);\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param uint32_t faultMask value\r
- * @return none\r
- *\r
- * Set the fault mask register\r
- */\r
-extern void __set_FAULTMASK(uint32_t faultMask);\r
-\r
-/**\r
- * @brief Return the Control Register value\r
-* \r
-* @param none\r
-* @return uint32_t Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-extern uint32_t __get_CONTROL(void);\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param uint32_t Control value\r
- * @return none\r
- *\r
- * Set the control register\r
- */\r
-extern void __set_CONTROL(uint32_t control);\r
-\r
-/**\r
- * @brief Reverse byte order in integer value\r
- *\r
- * @param uint32_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in integer value\r
- */\r
-extern uint32_t __REV(uint32_t value);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param uint16_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/*\r
- * Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param int16_t value to reverse\r
- * @return int32_t reversed value\r
- *\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- */\r
-extern int32_t __REVSH(int16_t value);\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param uint32_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-extern uint32_t __RBIT(uint32_t value);\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint8_t* address\r
- * @return uint8_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint8_t __LDREXB(uint8_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint16_t* address\r
- * @return uint16_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint16_t __LDREXH(uint16_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint32_t* address\r
- * @return uint32_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint32_t __LDREXW(uint32_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint8_t *address\r
- * @param uint8_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint16_t *address\r
- * @param uint16_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint32_t *address\r
- * @param uint32_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
-\r
-\r
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all instrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-#endif\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-\r
-\r
-/**\r
- * @brief Set the Priority Grouping in NVIC Interrupt Controller\r
- *\r
- * @param uint32_t priority_grouping is priority grouping field\r
- * @return none \r
- *\r
- * Set the priority grouping field using the required unlock sequence.\r
- * The parameter priority_grouping is assigned to the field \r
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
- */\r
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- \r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */\r
- reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8))); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-/**\r
- * @brief Get the Priority Grouping from NVIC Interrupt Controller\r
- *\r
- * @param none\r
- * @return uint32_t priority grouping field \r
- *\r
- * Get the priority grouping from NVIC Interrupt Controller.\r
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
- */\r
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((SCB->AIRCR >> 8) & 0x07); /* read priority grouping field */\r
-}\r
-\r
-/**\r
- * @brief Enable Interrupt in NVIC Interrupt Controller\r
- *\r
- * @param IRQn_Type IRQn specifies the interrupt number\r
- * @return none \r
- *\r
- * Enable a device specific interupt in the NVIC interrupt controller.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
-}\r
-\r
-/**\r
- * @brief Disable the interrupt line for external interrupt specified\r
- * \r
- * @param IRQn_Type IRQn is the positive number of the external interrupt\r
- * @return none\r
- * \r
- * Disable a device specific interupt in the NVIC interrupt controller.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
-}\r
-\r
-/**\r
- * @brief Read the interrupt pending bit for a device specific interrupt source\r
- * \r
- * @param IRQn_Type IRQn is the number of the device specifc interrupt\r
- * @return uint32_t 1 if pending interrupt else 0\r
- *\r
- * Read the pending register in NVIC and return 1 if its status is pending, \r
- * otherwise it returns 0\r
- */\r
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
-}\r
-\r
-/**\r
- * @brief Set the pending bit for an external interrupt\r
- * \r
- * @param IRQn_Type IRQn is the Number of the interrupt\r
- * @return none\r
- *\r
- * Set the pending bit for the specified interrupt.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
-}\r
-\r
-/**\r
- * @brief Clear the pending bit for an external interrupt\r
- *\r
- * @param IRQn_Type IRQn is the Number of the interrupt\r
- * @return none\r
- *\r
- * Clear the pending bit for the specified interrupt. \r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
-}\r
-\r
-/**\r
- * @brief Read the active bit for an external interrupt\r
- *\r
- * @param IRQn_Type IRQn is the Number of the interrupt\r
- * @return uint32_t 1 if active else 0\r
- *\r
- * Read the active register in NVIC and returns 1 if its status is active, \r
- * otherwise it returns 0.\r
- */\r
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
-}\r
-\r
-/**\r
- * @brief Set the priority for an interrupt\r
- *\r
- * @param IRQn_Type IRQn is the Number of the interrupt\r
- * @param priority is the priority for the interrupt\r
- * @return none\r
- *\r
- * Set the priority for the specified interrupt. The interrupt \r
- * number can be positive to specify an external (device specific) \r
- * interrupt, or negative to specify an internal (core) interrupt. \n\r
- *\r
- * Note: The priority cannot be set for every core interrupt.\r
- */\r
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if(IRQn < 0) {\r
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
- else {\r
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
-}\r
-\r
-/**\r
- * @brief Read the priority for an interrupt\r
- *\r
- * @param IRQn_Type IRQn is the Number of the interrupt\r
- * @return uint32_t priority is the priority for the interrupt\r
- *\r
- * Read the priority for the specified interrupt. The interrupt \r
- * number can be positive to specify an external (device specific) \r
- * interrupt, or negative to specify an internal (core) interrupt.\r
- *\r
- * The returned priority value is automatically aligned to the implemented\r
- * priority bits of the microcontroller.\r
- *\r
- * Note: The priority cannot be set for every core interrupt.\r
- */\r
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if(IRQn < 0) {\r
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */\r
- else {\r
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
-}\r
-\r
-\r
-/**\r
- * @brief Encode the priority for an interrupt\r
- *\r
- * @param uint32_t PriorityGroup is the used priority group\r
- * @param uint32_t PreemptPriority is the preemptive priority value (starting from 0)\r
- * @param uint32_t SubPriority is the sub priority value (starting from 0)\r
- * @return uint32_t the priority for the interrupt\r
- *\r
- * Encode the priority for an interrupt with the given priority group,\r
- * preemptive priority value and sub priority value.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
- *\r
- * The returned priority value can be used for NVIC_SetPriority(...) function\r
- */\r
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
- \r
- return (\r
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
- );\r
-}\r
-\r
-\r
-/**\r
- * @brief Decode the priority of an interrupt\r
- *\r
- * @param uint32_t Priority the priority for the interrupt\r
- * @param uint32_t PrioGroup is the used priority group\r
- * @param uint32_t* pPreemptPrio is the preemptive priority value (starting from 0)\r
- * @param uint32_t* pSubPrio is the sub priority value (starting from 0)\r
- * @return none\r
- *\r
- * Decode an interrupt priority value with the given priority group to \r
- * preemptive priority value and sub priority value.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
- *\r
- * The priority value can be retrieved with NVIC_GetPriority(...) function\r
- */\r
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
- \r
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
-}\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-\r
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
-\r
-/* SysTick constants */\r
-#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */\r
-#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */\r
-#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */\r
-#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */\r
-\r
-/**\r
- * @brief Initialize and start the SysTick counter and its interrupt.\r
- *\r
- * @param uint32_t ticks is the number of ticks between two interrupts\r
- * @return none\r
- *\r
- * Initialise the system tick timer and its interrupt and start the\r
- * system tick timer / counter in free running mode to generate \r
- * periodical interrupts.\r
- */\r
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{ \r
- if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */\r
-\r
- SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
- SysTick->VAL = (0x00); /* Load the SysTick Counter Value */\r
- SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-\r
-\r
-\r
-\r
-/* ################################## Reset function ############################################ */\r
-\r
-/**\r
- * @brief Initiate a system reset request.\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * Initialize a system reset request to reset the MCU\r
- */\r
-static __INLINE void NVIC_SystemReset(void)\r
-{\r
- SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */ \r
- while(1); /* wait until reset */\r
-}\r
-\r
-\r
-/* ################################## Debug Output function ############################################ */\r
-\r
-\r
-/**\r
- * @brief Outputs a character via the ITM channel 0\r
- *\r
- * @param uint32_t character to output\r
- * @return uint32_t input character\r
- *\r
- * The function outputs a character via the ITM channel 0. \r
- * The function returns when no debugger is connected that has booked the output. \r
- * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
- */\r
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if (ch == '\n') ITM_SendChar('\r');\r
- \r
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&\r
- (ITM->TCR & ITM_TCR_ITMENA) &&\r
- (ITM->TER & (1UL << 0)) ) \r
- {\r
- while (ITM->PORT[0].u32 == 0);\r
- ITM->PORT[0].u8 = (uint8_t) ch;\r
- } \r
- return (ch);\r
-}\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CM3_CORE_H__ */\r
-\r
-/*lint -restore */\r
+/******************************************************************************
+ * @file: core_cm3.h
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version: V1.20
+ * @date: 22. May 2009
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CM3_CORE_H__
+#define __CM3_CORE_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex core */
+
+/**
+ * Lint configuration \n
+ * ----------------------- \n
+ *
+ * The following Lint messages will be suppressed and not shown: \n
+ * \n
+ * --- Error 10: --- \n
+ * register uint32_t __regBasePri __asm("basepri"); \n
+ * Error 10: Expecting ';' \n
+ * \n
+ * --- Error 530: --- \n
+ * return(__regBasePri); \n
+ * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
+ * \n
+ * --- Error 550: --- \n
+ * __regBasePri = (basePri & 0x1ff); \n
+ * } \n
+ * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
+ * \n
+ * --- Error 754: --- \n
+ * uint32_t RESERVED0[24]; \n
+ * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
+ * \n
+ * --- Error 750: --- \n
+ * #define __CM3_CORE_H__ \n
+ * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
+ * \n
+ * --- Error 528: --- \n
+ * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
+ * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
+ * \n
+ * --- Error 751: --- \n
+ * } InterruptType_Type; \n
+ * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
+ * \n
+ * \n
+ * Note: To re-enable a Message, insert a space before 'lint' * \n
+ *
+ */
+
+/*lint -save */
+/*lint -e10 */
+/*lint -e530 */
+/*lint -e550 */
+/*lint -e754 */
+/*lint -e750 */
+/*lint -e528 */
+/*lint -e751 */
+
+
+#include <stdint.h> /* Include standard types */
+
+#if defined (__ICCARM__)
+ #include <intrinsics.h> /* IAR Intrinsics */
+#endif
+
+
+#ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
+#endif
+
+
+
+
+/**
+ * IO definitions
+ *
+ * define access restrictions to peripheral registers
+ */
+
+#ifdef __cplusplus
+#define __I volatile /*!< defines 'read only' permissions */
+#else
+#define __I volatile const /*!< defines 'read only' permissions */
+#endif
+#define __O volatile /*!< defines 'write only' permissions */
+#define __IO volatile /*!< defines 'read / write' permissions */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ ******************************************************************************/
+
+
+/* System Reset */
+#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */
+#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */
+#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */
+#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */
+
+/* Core Debug */
+#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */
+#define ITM_TCR_ITMENA 1 /*!< ITM enable */
+
+
+
+
+/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Software Trigger Interrupt Register */
+} NVIC_Type;
+
+
+/* memory mapping struct for System Control Block */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< CPU ID Base Register */
+ __IO uint32_t ICSR; /*!< Interrupt Control State Register */
+ __IO uint32_t VTOR; /*!< Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */
+ __IO uint32_t SCR; /*!< System Control Register */
+ __IO uint32_t CCR; /*!< Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Hard Fault Status Register */
+ __IO uint32_t DFSR; /*!< Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Mem Manage Address Register */
+ __IO uint32_t BFAR; /*!< Bus Fault Address Register */
+ __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Processor Feature Register */
+ __I uint32_t DFR; /*!< Debug Feature Register */
+ __I uint32_t ADR; /*!< Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< ISA Feature Register */
+} SCB_Type;
+
+
+/* memory mapping struct for SysTick */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< SysTick Calibration Register */
+} SysTick_Type;
+
+
+/* memory mapping structur for ITM */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __IO uint32_t IWR; /*!< ITM Integration Write Register */
+ __IO uint32_t IRR; /*!< ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __IO uint32_t LAR; /*!< ITM Lock Access Register */
+ __IO uint32_t LSR; /*!< ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< ITM Product ID Registers */
+ __I uint32_t PID5;
+ __I uint32_t PID6;
+ __I uint32_t PID7;
+ __I uint32_t PID0;
+ __I uint32_t PID1;
+ __I uint32_t PID2;
+ __I uint32_t PID3;
+ __I uint32_t CID0;
+ __I uint32_t CID1;
+ __I uint32_t CID2;
+ __I uint32_t CID3;
+} ITM_Type;
+
+
+/* memory mapped struct for Interrupt Type */
+typedef struct
+{
+ uint32_t RESERVED0;
+ __I uint32_t ICTR; /*!< Interrupt Control Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Auxiliary Control Register */
+#else
+ uint32_t RESERVED1;
+#endif
+} InterruptType_Type;
+
+
+/* Memory Protection Unit */
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
+typedef struct
+{
+ __I uint32_t TYPE; /*!< MPU Type Register */
+ __IO uint32_t CTRL; /*!< MPU Control Register */
+ __IO uint32_t RNR; /*!< MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+#endif
+
+
+/* Core Debug Register */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000) /*!< ITM Base Address */
+#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
+
+#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
+#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
+#endif
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+
+#endif
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#define __enable_fault_irq __enable_fiq
+#define __disable_fault_irq __disable_fiq
+
+#define __NOP __nop
+#define __WFI __wfi
+#define __WFE __wfe
+#define __SEV __sev
+#define __ISB() __isb(0)
+#define __DSB() __dsb(0)
+#define __DMB() __dmb(0)
+#define __REV __rev
+#define __RBIT __rbit
+#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
+#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
+#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
+#define __STREXB(value, ptr) __strex(value, ptr)
+#define __STREXH(value, ptr) __strex(value, ptr)
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
+/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/*
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param int16_t value to reverse
+ * @return int32_t reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+extern int32_t __REVSH(int16_t value);
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief Remove the exclusive lock created by ldrex
+ *
+ * @param none
+ * @return none
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+extern void __CLREX(void);
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @param none
+ * @return uint32_t BasePriority
+ *
+ * Return the content of the base priority register
+ */
+extern uint32_t __get_BASEPRI(void);
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param uint32_t BasePriority
+ * @return none
+ *
+ * Set the base priority register
+ */
+extern void __set_BASEPRI(uint32_t basePri);
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @param none
+ * @return uint32_t PriMask
+ *
+ * Return the state of the priority mask bit from the priority mask
+ * register
+ */
+extern uint32_t __get_PRIMASK(void);
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param uint32_t PriMask
+ * @return none
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+extern void __set_PRIMASK(uint32_t priMask);
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @param none
+ * @return uint32_t FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+extern uint32_t __get_FAULTMASK(void);
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param uint32_t faultMask value
+ * @return none
+ *
+ * Set the fault mask register
+ */
+extern void __set_FAULTMASK(uint32_t faultMask);
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @param none
+ * @return uint32_t Control value
+ *
+ * Return the content of the control register
+ */
+extern uint32_t __get_CONTROL(void);
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param uint32_t Control value
+ * @return none
+ *
+ * Set the control register
+ */
+extern void __set_CONTROL(uint32_t control);
+
+#else /* (__ARMCC_VERSION >= 400000) */
+
+
+/**
+ * @brief Remove the exclusive lock created by ldrex
+ *
+ * @param none
+ * @return none
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+#define __CLREX __clrex
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @param none
+ * @return uint32_t BasePriority
+ *
+ * Return the content of the base priority register
+ */
+static __INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param uint32_t BasePriority
+ * @return none
+ *
+ * Set the base priority register
+ */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0x1ff);
+}
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @param none
+ * @return uint32_t PriMask
+ *
+ * Return the state of the priority mask bit from the priority mask
+ * register
+ */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param uint32_t PriMask
+ * @return none
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @param none
+ * @return uint32_t FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param uint32_t faultMask value
+ * @return none
+ *
+ * Set the fault mask register
+ */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & 1);
+}
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @param none
+ * @return uint32_t Control value
+ *
+ * Return the content of the control register
+ */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param uint32_t Control value
+ * @return none
+ *
+ * Set the control register
+ */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+#endif /* __ARMCC_VERSION */
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
+#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
+
+static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
+static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
+
+#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
+static __INLINE void __WFI() { __ASM ("wfi"); }
+static __INLINE void __WFE() { __ASM ("wfe"); }
+static __INLINE void __SEV() { __ASM ("sev"); }
+static __INLINE void __CLREX() { __ASM ("clrex"); }
+
+/* intrinsic void __ISB(void) */
+/* intrinsic void __DSB(void) */
+/* intrinsic void __DMB(void) */
+/* intrinsic void __set_PRIMASK(); */
+/* intrinsic void __get_PRIMASK(); */
+/* intrinsic void __set_FAULTMASK(); */
+/* intrinsic void __get_FAULTMASK(); */
+/* intrinsic uint32_t __REV(uint32_t value); */
+/* intrinsic uint32_t __REVSH(uint32_t value); */
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
+/* intrinsic unsigned long __LDREX(unsigned long *); */
+
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse bit order of value
+ */
+extern uint32_t __RBIT(uint32_t value);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint8_t* address
+ * @return uint8_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint8_t __LDREXB(uint8_t *addr);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint16_t* address
+ * @return uint16_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint16_t __LDREXH(uint16_t *addr);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint32_t* address
+ * @return uint32_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint32_t __LDREXW(uint32_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint8_t *address
+ * @param uint8_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint16_t *address
+ * @param uint16_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint32_t *address
+ * @param uint32_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
+
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
+static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
+
+static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
+static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
+
+static __INLINE void __NOP() { __ASM volatile ("nop"); }
+static __INLINE void __WFI() { __ASM volatile ("wfi"); }
+static __INLINE void __WFE() { __ASM volatile ("wfe"); }
+static __INLINE void __SEV() { __ASM volatile ("sev"); }
+static __INLINE void __ISB() { __ASM volatile ("isb"); }
+static __INLINE void __DSB() { __ASM volatile ("dsb"); }
+static __INLINE void __DMB() { __ASM volatile ("dmb"); }
+static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
+
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @param none
+ * @return uint32_t BasePriority
+ *
+ * Return the content of the base priority register
+ */
+extern uint32_t __get_BASEPRI(void);
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param uint32_t BasePriority
+ * @return none
+ *
+ * Set the base priority register
+ */
+extern void __set_BASEPRI(uint32_t basePri);
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @param none
+ * @return uint32_t PriMask
+ *
+ * Return the state of the priority mask bit from the priority mask
+ * register
+ */
+extern uint32_t __get_PRIMASK(void);
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param uint32_t PriMask
+ * @return none
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+extern void __set_PRIMASK(uint32_t priMask);
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @param none
+ * @return uint32_t FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+extern uint32_t __get_FAULTMASK(void);
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param uint32_t faultMask value
+ * @return none
+ *
+ * Set the fault mask register
+ */
+extern void __set_FAULTMASK(uint32_t faultMask);
+
+/**
+ * @brief Return the Control Register value
+*
+* @param none
+* @return uint32_t Control value
+ *
+ * Return the content of the control register
+ */
+extern uint32_t __get_CONTROL(void);
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param uint32_t Control value
+ * @return none
+ *
+ * Set the control register
+ */
+extern void __set_CONTROL(uint32_t control);
+
+/**
+ * @brief Reverse byte order in integer value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in integer value
+ */
+extern uint32_t __REV(uint32_t value);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/*
+ * Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param int16_t value to reverse
+ * @return int32_t reversed value
+ *
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ */
+extern int32_t __REVSH(int16_t value);
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse bit order of value
+ */
+extern uint32_t __RBIT(uint32_t value);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint8_t* address
+ * @return uint8_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint8_t __LDREXB(uint8_t *addr);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint16_t* address
+ * @return uint16_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint16_t __LDREXH(uint16_t *addr);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint32_t* address
+ * @return uint32_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint32_t __LDREXW(uint32_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint8_t *address
+ * @param uint8_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint16_t *address
+ * @param uint16_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint32_t *address
+ * @param uint32_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
+
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+
+
+/* ########################## NVIC functions #################################### */
+
+
+/**
+ * @brief Set the Priority Grouping in NVIC Interrupt Controller
+ *
+ * @param uint32_t priority_grouping is priority grouping field
+ * @return none
+ *
+ * Set the priority grouping field using the required unlock sequence.
+ * The parameter priority_grouping is assigned to the field
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */
+ reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8))); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+/**
+ * @brief Get the Priority Grouping from NVIC Interrupt Controller
+ *
+ * @param none
+ * @return uint32_t priority grouping field
+ *
+ * Get the priority grouping from NVIC Interrupt Controller.
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+ */
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR >> 8) & 0x07); /* read priority grouping field */
+}
+
+/**
+ * @brief Enable Interrupt in NVIC Interrupt Controller
+ *
+ * @param IRQn_Type IRQn specifies the interrupt number
+ * @return none
+ *
+ * Enable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+/**
+ * @brief Disable the interrupt line for external interrupt specified
+ *
+ * @param IRQn_Type IRQn is the positive number of the external interrupt
+ * @return none
+ *
+ * Disable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+/**
+ * @brief Read the interrupt pending bit for a device specific interrupt source
+ *
+ * @param IRQn_Type IRQn is the number of the device specifc interrupt
+ * @return uint32_t 1 if pending interrupt else 0
+ *
+ * Read the pending register in NVIC and return 1 if its status is pending,
+ * otherwise it returns 0
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+/**
+ * @brief Set the pending bit for an external interrupt
+ *
+ * @param IRQn_Type IRQn is the Number of the interrupt
+ * @return none
+ *
+ * Set the pending bit for the specified interrupt.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+/**
+ * @brief Clear the pending bit for an external interrupt
+ *
+ * @param IRQn_Type IRQn is the Number of the interrupt
+ * @return none
+ *
+ * Clear the pending bit for the specified interrupt.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+/**
+ * @brief Read the active bit for an external interrupt
+ *
+ * @param IRQn_Type IRQn is the Number of the interrupt
+ * @return uint32_t 1 if active else 0
+ *
+ * Read the active register in NVIC and returns 1 if its status is active,
+ * otherwise it returns 0.
+ */
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+/**
+ * @brief Set the priority for an interrupt
+ *
+ * @param IRQn_Type IRQn is the Number of the interrupt
+ * @param priority is the priority for the interrupt
+ * @return none
+ *
+ * Set the priority for the specified interrupt. The interrupt
+ * number can be positive to specify an external (device specific)
+ * interrupt, or negative to specify an internal (core) interrupt. \n
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+/**
+ * @brief Read the priority for an interrupt
+ *
+ * @param IRQn_Type IRQn is the Number of the interrupt
+ * @return uint32_t priority is the priority for the interrupt
+ *
+ * Read the priority for the specified interrupt. The interrupt
+ * number can be positive to specify an external (device specific)
+ * interrupt, or negative to specify an internal (core) interrupt.
+ *
+ * The returned priority value is automatically aligned to the implemented
+ * priority bits of the microcontroller.
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/**
+ * @brief Encode the priority for an interrupt
+ *
+ * @param uint32_t PriorityGroup is the used priority group
+ * @param uint32_t PreemptPriority is the preemptive priority value (starting from 0)
+ * @param uint32_t SubPriority is the sub priority value (starting from 0)
+ * @return uint32_t the priority for the interrupt
+ *
+ * Encode the priority for an interrupt with the given priority group,
+ * preemptive priority value and sub priority value.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ *
+ * The returned priority value can be used for NVIC_SetPriority(...) function
+ */
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/**
+ * @brief Decode the priority of an interrupt
+ *
+ * @param uint32_t Priority the priority for the interrupt
+ * @param uint32_t PrioGroup is the used priority group
+ * @param uint32_t* pPreemptPrio is the preemptive priority value (starting from 0)
+ * @param uint32_t* pSubPrio is the sub priority value (starting from 0)
+ * @return none
+ *
+ * Decode an interrupt priority value with the given priority group to
+ * preemptive priority value and sub priority value.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ *
+ * The priority value can be retrieved with NVIC_GetPriority(...) function
+ */
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+
+/* ################################## SysTick function ############################################ */
+
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
+
+/* SysTick constants */
+#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */
+#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */
+#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */
+#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */
+
+/**
+ * @brief Initialize and start the SysTick counter and its interrupt.
+ *
+ * @param uint32_t ticks is the number of ticks between two interrupts
+ * @return none
+ *
+ * Initialise the system tick timer and its interrupt and start the
+ * system tick timer / counter in free running mode to generate
+ * periodical interrupts.
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
+ SysTick->VAL = (0x00); /* Load the SysTick Counter Value */
+ SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+
+
+
+
+/* ################################## Reset function ############################################ */
+
+/**
+ * @brief Initiate a system reset request.
+ *
+ * @param none
+ * @return none
+ *
+ * Initialize a system reset request to reset the MCU
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+ SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+
+/* ################################## Debug Output function ############################################ */
+
+
+/**
+ * @brief Outputs a character via the ITM channel 0
+ *
+ * @param uint32_t character to output
+ * @return uint32_t input character
+ *
+ * The function outputs a character via the ITM channel 0.
+ * The function returns when no debugger is connected that has booked the output.
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted.
+ */
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (ch == '\n') ITM_SendChar('\r');
+
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
+ (ITM->TCR & ITM_TCR_ITMENA) &&
+ (ITM->TER & (1UL << 0)) )
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CM3_CORE_H__ */
+
+/*lint -restore */
-/******************************************************************************\r
- * @file: LPC17xx.h\r
- * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for \r
- * NXP LPC17xx Device Series \r
- * @version: V1.1\r
- * @date: 14th May 2009\r
- *----------------------------------------------------------------------------\r
- *\r
- * Copyright (C) 2008 ARM Limited. All rights reserved.\r
- *\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M3 \r
- * processor based microcontrollers. This file can be freely distributed \r
- * within development tools that are supporting such ARM based processors. \r
- *\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-\r
-#ifndef __LPC17xx_H__\r
-#define __LPC17xx_H__\r
-\r
-/*\r
- * ==========================================================================\r
- * ---------- Interrupt Number Definition -----------------------------------\r
- * ==========================================================================\r
- */\r
-\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** LPC17xx Specific Interrupt Numbers *******************************************************/\r
- WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */\r
- TIMER0_IRQn = 1, /*!< Timer0 Interrupt */\r
- TIMER1_IRQn = 2, /*!< Timer1 Interrupt */\r
- TIMER2_IRQn = 3, /*!< Timer2 Interrupt */\r
- TIMER3_IRQn = 4, /*!< Timer3 Interrupt */\r
- UART0_IRQn = 5, /*!< UART0 Interrupt */\r
- UART1_IRQn = 6, /*!< UART1 Interrupt */\r
- UART2_IRQn = 7, /*!< UART2 Interrupt */\r
- UART3_IRQn = 8, /*!< UART3 Interrupt */\r
- PWM1_IRQn = 9, /*!< PWM1 Interrupt */\r
- I2C0_IRQn = 10, /*!< I2C0 Interrupt */\r
- I2C1_IRQn = 11, /*!< I2C1 Interrupt */\r
- I2C2_IRQn = 12, /*!< I2C2 Interrupt */\r
- SPI_IRQn = 13, /*!< SPI Interrupt */\r
- SSP0_IRQn = 14, /*!< SSP0 Interrupt */\r
- SSP1_IRQn = 15, /*!< SSP1 Interrupt */\r
- PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */\r
- RTC_IRQn = 17, /*!< Real Time Clock Interrupt */\r
- EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */\r
- EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */\r
- EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */\r
- EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */\r
- ADC_IRQn = 22, /*!< A/D Converter Interrupt */\r
- BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */\r
- USB_IRQn = 24, /*!< USB Interrupt */\r
- CAN_IRQn = 25, /*!< CAN Interrupt */\r
- DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */\r
- I2S_IRQn = 27, /*!< I2S Interrupt */\r
- ENET_IRQn = 28, /*!< Ethernet Interrupt */\r
- RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */\r
- MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */\r
- QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */\r
- PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */\r
-} IRQn_Type;\r
-\r
-\r
-/*\r
- * ==========================================================================\r
- * ----------- Processor and Core Peripheral Section ------------------------\r
- * ==========================================================================\r
- */\r
-\r
-/* Configuration of the Cortex-M3 Processor and Core Peripherals */\r
-#define __MPU_PRESENT 1 /*!< MPU present or not */\r
-#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */\r
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
-\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_LPC17xx.h" /* System Header */\r
-\r
-\r
-\r
-/**\r
- * Initialize the system clock\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * @brief Setup the microcontroller system.\r
- * Initialize the System and update the SystemFrequency variable.\r
- */\r
-extern void SystemInit (void);\r
-\r
-\r
-/******************************************************************************/\r
-/* Device Specific Peripheral registers structures */\r
-/******************************************************************************/\r
-\r
-#pragma anon_unions\r
-\r
-/*------------- System Control (SC) ------------------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t FLASHCFG; /* Flash Accelerator Module */\r
- uint32_t RESERVED0[31];\r
- __IO uint32_t PLL0CON; /* Clocking and Power Control */\r
- __IO uint32_t PLL0CFG;\r
- __I uint32_t PLL0STAT;\r
- __O uint32_t PLL0FEED;\r
- uint32_t RESERVED1[4];\r
- __IO uint32_t PLL1CON;\r
- __IO uint32_t PLL1CFG;\r
- __I uint32_t PLL1STAT;\r
- __O uint32_t PLL1FEED;\r
- uint32_t RESERVED2[4];\r
- __IO uint32_t PCON;\r
- __IO uint32_t PCONP;\r
- uint32_t RESERVED3[15];\r
- __IO uint32_t CCLKCFG;\r
- __IO uint32_t USBCLKCFG;\r
- __IO uint32_t CLKSRCSEL;\r
- uint32_t RESERVED4[12];\r
- __IO uint32_t EXTINT; /* External Interrupts */\r
- uint32_t RESERVED5;\r
- __IO uint32_t EXTMODE;\r
- __IO uint32_t EXTPOLAR;\r
- uint32_t RESERVED6[12];\r
- __IO uint32_t RSID; /* Reset */\r
- uint32_t RESERVED7[7];\r
- __IO uint32_t SCS; /* Syscon Miscellaneous Registers */\r
- __IO uint32_t IRCTRIM; /* Clock Dividers */\r
- __IO uint32_t PCLKSEL0;\r
- __IO uint32_t PCLKSEL1;\r
- uint32_t RESERVED8[4];\r
- __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */\r
- uint32_t RESERVED9;\r
- __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */\r
- } SC_TypeDef;\r
-\r
-/*------------- Pin Connect Block (PINCON) -----------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t PINSEL0;\r
- __IO uint32_t PINSEL1;\r
- __IO uint32_t PINSEL2;\r
- __IO uint32_t PINSEL3;\r
- __IO uint32_t PINSEL4;\r
- __IO uint32_t PINSEL5;\r
- __IO uint32_t PINSEL6;\r
- __IO uint32_t PINSEL7;\r
- __IO uint32_t PINSEL8;\r
- __IO uint32_t PINSEL9;\r
- __IO uint32_t PINSEL10;\r
- uint32_t RESERVED0[5];\r
- __IO uint32_t PINMODE0;\r
- __IO uint32_t PINMODE1;\r
- __IO uint32_t PINMODE2;\r
- __IO uint32_t PINMODE3;\r
- __IO uint32_t PINMODE4;\r
- __IO uint32_t PINMODE5;\r
- __IO uint32_t PINMODE6;\r
- __IO uint32_t PINMODE7;\r
- __IO uint32_t PINMODE8;\r
- __IO uint32_t PINMODE9;\r
- __IO uint32_t PINMODE_OD0;\r
- __IO uint32_t PINMODE_OD1;\r
- __IO uint32_t PINMODE_OD2;\r
- __IO uint32_t PINMODE_OD3;\r
- __IO uint32_t PINMODE_OD4;\r
-} PINCON_TypeDef;\r
-\r
-/*------------- General Purpose Input/Output (GPIO) --------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t FIODIR;\r
- uint32_t RESERVED0[3];\r
- __IO uint32_t FIOMASK;\r
- __IO uint32_t FIOPIN;\r
- __IO uint32_t FIOSET;\r
- __O uint32_t FIOCLR;\r
-} GPIO_TypeDef;\r
-\r
-typedef struct\r
-{\r
- __I uint32_t IntStatus;\r
- __I uint32_t IO0IntStatR;\r
- __I uint32_t IO0IntStatF;\r
- __O uint32_t IO0IntClr;\r
- __IO uint32_t IO0IntEnR;\r
- __IO uint32_t IO0IntEnF;\r
- uint32_t RESERVED0[3];\r
- __I uint32_t IO2IntStatR;\r
- __I uint32_t IO2IntStatF;\r
- __O uint32_t IO2IntClr;\r
- __IO uint32_t IO2IntEnR;\r
- __IO uint32_t IO2IntEnF;\r
-} GPIOINT_TypeDef;\r
-\r
-/*------------- Timer (TIM) --------------------------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t IR;\r
- __IO uint32_t TCR;\r
- __IO uint32_t TC;\r
- __IO uint32_t PR;\r
- __IO uint32_t PC;\r
- __IO uint32_t MCR;\r
- __IO uint32_t MR0;\r
- __IO uint32_t MR1;\r
- __IO uint32_t MR2;\r
- __IO uint32_t MR3;\r
- __IO uint32_t CCR;\r
- __I uint32_t CR0;\r
- __I uint32_t CR1;\r
- uint32_t RESERVED0[2];\r
- __IO uint32_t EMR;\r
- uint32_t RESERVED1[24];\r
- __IO uint32_t CTCR;\r
-} TIM_TypeDef;\r
-\r
-/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t IR;\r
- __IO uint32_t TCR;\r
- __IO uint32_t TC;\r
- __IO uint32_t PR;\r
- __IO uint32_t PC;\r
- __IO uint32_t MCR;\r
- __IO uint32_t MR0;\r
- __IO uint32_t MR1;\r
- __IO uint32_t MR2;\r
- __IO uint32_t MR3;\r
- __IO uint32_t CCR;\r
- __I uint32_t CR0;\r
- __I uint32_t CR1;\r
- __I uint32_t CR2;\r
- __I uint32_t CR3;\r
- __IO uint32_t MR4;\r
- __IO uint32_t MR5;\r
- __IO uint32_t MR6;\r
- __IO uint32_t PCR;\r
- __IO uint32_t LER;\r
- uint32_t RESERVED0[7];\r
- __IO uint32_t CTCR;\r
-} PWM_TypeDef;\r
-\r
-/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/\r
-typedef struct\r
-{\r
- union {\r
- __I uint8_t RBR;\r
- __O uint8_t THR;\r
- __IO uint8_t DLL;\r
- uint32_t RESERVED0;\r
- };\r
- union {\r
- __IO uint8_t DLM;\r
- __IO uint32_t IER;\r
- };\r
- union {\r
- __I uint32_t IIR;\r
- __O uint8_t FCR;\r
- };\r
- __IO uint8_t LCR;\r
- uint8_t RESERVED1[7];\r
- __IO uint8_t LSR;\r
- uint8_t RESERVED2[7];\r
- __IO uint8_t SCR;\r
- uint8_t RESERVED3[3];\r
- __IO uint32_t ACR;\r
- __IO uint8_t ICR;\r
- uint8_t RESERVED4[3];\r
- __IO uint8_t FDR;\r
- uint8_t RESERVED5[7];\r
- __IO uint8_t TER;\r
- uint8_t RESERVED6[27];\r
- __IO uint8_t RS485CTRL;\r
- uint8_t RESERVED7[3];\r
- __IO uint8_t ADRMATCH;\r
-} UART_TypeDef;\r
-\r
-typedef struct\r
-{\r
- union {\r
- __I uint8_t RBR;\r
- __O uint8_t THR;\r
- __IO uint8_t DLL;\r
- uint32_t RESERVED0;\r
- };\r
- union {\r
- __IO uint8_t DLM;\r
- __IO uint32_t IER;\r
- };\r
- union {\r
- __I uint32_t IIR;\r
- __O uint8_t FCR;\r
- };\r
- __IO uint8_t LCR;\r
- uint8_t RESERVED1[3];\r
- __IO uint8_t MCR;\r
- uint8_t RESERVED2[3];\r
- __IO uint8_t LSR;\r
- uint8_t RESERVED3[3];\r
- __IO uint8_t MSR;\r
- uint8_t RESERVED4[3];\r
- __IO uint8_t SCR;\r
- uint8_t RESERVED5[3];\r
- __IO uint32_t ACR;\r
- uint32_t RESERVED6;\r
- __IO uint32_t FDR;\r
- uint32_t RESERVED7;\r
- __IO uint8_t TER;\r
- uint8_t RESERVED8[27];\r
- __IO uint8_t RS485CTRL;\r
- uint8_t RESERVED9[3];\r
- __IO uint8_t ADRMATCH;\r
- uint8_t RESERVED10[3];\r
- __IO uint8_t RS485DLY;\r
-} UART1_TypeDef;\r
-\r
-/*------------- Serial Peripheral Interface (SPI) ----------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t SPCR;\r
- __I uint32_t SPSR;\r
- __IO uint32_t SPDR;\r
- __IO uint32_t SPCCR;\r
- uint32_t RESERVED0[3];\r
- __IO uint32_t SPINT;\r
-} SPI_TypeDef;\r
-\r
-/*------------- Synchronous Serial Communication (SSP) -----------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t CR0;\r
- __IO uint32_t CR1;\r
- __IO uint32_t DR;\r
- __I uint32_t SR;\r
- __IO uint32_t CPSR;\r
- __IO uint32_t IMSC;\r
- __IO uint32_t RIS;\r
- __IO uint32_t MIS;\r
- __IO uint32_t ICR;\r
- __IO uint32_t DMACR;\r
-} SSP_TypeDef;\r
-\r
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t I2CONSET;\r
- __I uint32_t I2STAT;\r
- __IO uint32_t I2DAT;\r
- __IO uint32_t I2ADR0;\r
- __IO uint32_t I2SCLH;\r
- __IO uint32_t I2SCLL;\r
- __O uint32_t I2CONCLR;\r
- __IO uint32_t MMCTRL;\r
- __IO uint32_t I2ADR1;\r
- __IO uint32_t I2ADR2;\r
- __IO uint32_t I2ADR3;\r
- __I uint32_t I2DATA_BUFFER;\r
- __IO uint32_t I2MASK0;\r
- __IO uint32_t I2MASK1;\r
- __IO uint32_t I2MASK2;\r
- __IO uint32_t I2MASK3;\r
-} I2C_TypeDef;\r
-\r
-/*------------- Inter IC Sound (I2S) -----------------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t I2SDAO;\r
- __I uint32_t I2SDAI;\r
- __O uint32_t I2STXFIFO;\r
- __I uint32_t I2SRXFIFO;\r
- __I uint32_t I2SSTATE;\r
- __IO uint32_t I2SDMA1;\r
- __IO uint32_t I2SDMA2;\r
- __IO uint32_t I2SIRQ;\r
- __IO uint32_t I2STXRATE;\r
- __IO uint32_t I2SRXRATE;\r
- __IO uint32_t I2STXBITRATE;\r
- __IO uint32_t I2SRXBITRATE;\r
- __IO uint32_t I2STXMODE;\r
- __IO uint32_t I2SRXMODE;\r
-} I2S_TypeDef;\r
-\r
-/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t RICOMPVAL;\r
- __IO uint32_t RIMASK;\r
- __IO uint8_t RICTRL;\r
- uint8_t RESERVED0[3];\r
- __IO uint32_t RICOUNTER;\r
-} RIT_TypeDef;\r
-\r
-/*------------- Real-Time Clock (RTC) ----------------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint8_t ILR;\r
- uint8_t RESERVED0[3];\r
- __IO uint8_t CCR;\r
- uint8_t RESERVED1[3];\r
- __IO uint8_t CIIR;\r
- uint8_t RESERVED2[3];\r
- __IO uint8_t AMR;\r
- uint8_t RESERVED3[3];\r
- __I uint32_t CTIME0;\r
- __I uint32_t CTIME1;\r
- __I uint32_t CTIME2;\r
- __IO uint8_t SEC;\r
- uint8_t RESERVED4[3];\r
- __IO uint8_t MIN;\r
- uint8_t RESERVED5[3];\r
- __IO uint8_t HOUR;\r
- uint8_t RESERVED6[3];\r
- __IO uint8_t DOM;\r
- uint8_t RESERVED7[3];\r
- __IO uint8_t DOW;\r
- uint8_t RESERVED8[3];\r
- __IO uint16_t DOY;\r
- uint16_t RESERVED9;\r
- __IO uint8_t MONTH;\r
- uint8_t RESERVED10[3];\r
- __IO uint16_t YEAR;\r
- uint16_t RESERVED11;\r
- __IO uint32_t CALIBRATION;\r
- __IO uint32_t GPREG0;\r
- __IO uint32_t GPREG1;\r
- __IO uint32_t GPREG2;\r
- __IO uint32_t GPREG3;\r
- __IO uint32_t GPREG4;\r
- __IO uint8_t WAKEUPDIS;\r
- uint8_t RESERVED12[3];\r
- __IO uint8_t PWRCTRL;\r
- uint8_t RESERVED13[3];\r
- __IO uint8_t ALSEC;\r
- uint8_t RESERVED14[3];\r
- __IO uint8_t ALMIN;\r
- uint8_t RESERVED15[3];\r
- __IO uint8_t ALHOUR;\r
- uint8_t RESERVED16[3];\r
- __IO uint8_t ALDOM;\r
- uint8_t RESERVED17[3];\r
- __IO uint8_t ALDOW;\r
- uint8_t RESERVED18[3];\r
- __IO uint16_t ALDOY;\r
- uint16_t RESERVED19;\r
- __IO uint8_t ALMON;\r
- uint8_t RESERVED20[3];\r
- __IO uint16_t ALYEAR;\r
- uint16_t RESERVED21;\r
-} RTC_TypeDef;\r
-\r
-/*------------- Watchdog Timer (WDT) -----------------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint8_t WDMOD;\r
- uint8_t RESERVED0[3];\r
- __IO uint32_t WDTC;\r
- __O uint8_t WDFEED;\r
- uint8_t RESERVED1[3];\r
- __I uint32_t WDTV;\r
- __IO uint32_t WDCLKSEL;\r
-} WDT_TypeDef;\r
-\r
-/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t ADCR;\r
- __IO uint32_t ADGDR;\r
- uint32_t RESERVED0;\r
- __IO uint32_t ADINTEN;\r
- __I uint32_t ADDR0;\r
- __I uint32_t ADDR1;\r
- __I uint32_t ADDR2;\r
- __I uint32_t ADDR3;\r
- __I uint32_t ADDR4;\r
- __I uint32_t ADDR5;\r
- __I uint32_t ADDR6;\r
- __I uint32_t ADDR7;\r
- __I uint32_t ADSTAT;\r
- __IO uint32_t ADTRM;\r
-} ADC_TypeDef;\r
-\r
-/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t DACR;\r
- __IO uint32_t DACCTRL;\r
- __IO uint16_t DACCNTVAL;\r
-} DAC_TypeDef;\r
-\r
-/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/\r
-typedef struct\r
-{\r
- __I uint32_t MCCON;\r
- __O uint32_t MCCON_SET;\r
- __O uint32_t MCCON_CLR;\r
- __I uint32_t MCCAPCON;\r
- __O uint32_t MCCAPCON_SET;\r
- __O uint32_t MCCAPCON_CLR;\r
- __IO uint32_t MCTIM0;\r
- __IO uint32_t MCTIM1;\r
- __IO uint32_t MCTIM2;\r
- __IO uint32_t MCPER0;\r
- __IO uint32_t MCPER1;\r
- __IO uint32_t MCPER2;\r
- __IO uint32_t MCPW0;\r
- __IO uint32_t MCPW1;\r
- __IO uint32_t MCPW2;\r
- __IO uint32_t MCDEADTIME;\r
- __IO uint32_t MCCCP;\r
- __IO uint32_t MCCR0;\r
- __IO uint32_t MCCR1;\r
- __IO uint32_t MCCR2;\r
- __I uint32_t MCINTEN;\r
- __O uint32_t MCINTEN_SET;\r
- __O uint32_t MCINTEN_CLR;\r
- __I uint32_t MCCNTCON;\r
- __O uint32_t MCCNTCON_SET;\r
- __O uint32_t MCCNTCON_CLR;\r
- __I uint32_t MCINTFLAG;\r
- __O uint32_t MCINTFLAG_SET;\r
- __O uint32_t MCINTFLAG_CLR;\r
- __O uint32_t MCCAP_CLR;\r
-} MCPWM_TypeDef;\r
-\r
-/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/\r
-typedef struct\r
-{\r
- __O uint32_t QEICON;\r
- __I uint32_t QEISTAT;\r
- __IO uint32_t QEICONF;\r
- __I uint32_t QEIPOS;\r
- __IO uint32_t QEIMAXPOS;\r
- __IO uint32_t CMPOS0;\r
- __IO uint32_t CMPOS1;\r
- __IO uint32_t CMPOS2;\r
- __I uint32_t INXCNT;\r
- __IO uint32_t INXCMP;\r
- __IO uint32_t QEILOAD;\r
- __I uint32_t QEITIME;\r
- __I uint32_t QEIVEL;\r
- __I uint32_t QEICAP;\r
- __IO uint32_t VELCOMP;\r
- __IO uint32_t FILTER;\r
- uint32_t RESERVED0[998];\r
- __O uint32_t QEIIEC;\r
- __O uint32_t QEIIES;\r
- __I uint32_t QEIINTSTAT;\r
- __I uint32_t QEIIE;\r
- __O uint32_t QEICLR;\r
- __O uint32_t QEISET;\r
-} QEI_TypeDef;\r
-\r
-/*------------- Controller Area Network (CAN) --------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t mask[512]; /* ID Masks */\r
-} CANAF_RAM_TypeDef;\r
-\r
-typedef struct /* Acceptance Filter Registers */\r
-{\r
- __IO uint32_t AFMR;\r
- __IO uint32_t SFF_sa;\r
- __IO uint32_t SFF_GRP_sa;\r
- __IO uint32_t EFF_sa;\r
- __IO uint32_t EFF_GRP_sa;\r
- __IO uint32_t ENDofTable;\r
- __I uint32_t LUTerrAd;\r
- __I uint32_t LUTerr;\r
-} CANAF_TypeDef;\r
-\r
-typedef struct /* Central Registers */\r
-{\r
- __I uint32_t CANTxSR;\r
- __I uint32_t CANRxSR;\r
- __I uint32_t CANMSR;\r
-} CANCR_TypeDef;\r
-\r
-typedef struct /* Controller Registers */\r
-{\r
- __IO uint32_t MOD;\r
- __O uint32_t CMR;\r
- __IO uint32_t GSR;\r
- __I uint32_t ICR;\r
- __IO uint32_t IER;\r
- __IO uint32_t BTR;\r
- __IO uint32_t EWL;\r
- __I uint32_t SR;\r
- __IO uint32_t RFS;\r
- __IO uint32_t RID;\r
- __IO uint32_t RDA;\r
- __IO uint32_t RDB;\r
- __IO uint32_t TFI1;\r
- __IO uint32_t TID1;\r
- __IO uint32_t TDA1;\r
- __IO uint32_t TDB1;\r
- __IO uint32_t TFI2;\r
- __IO uint32_t TID2;\r
- __IO uint32_t TDA2;\r
- __IO uint32_t TDB2;\r
- __IO uint32_t TFI3;\r
- __IO uint32_t TID3;\r
- __IO uint32_t TDA3;\r
- __IO uint32_t TDB3;\r
-} CAN_TypeDef;\r
-\r
-/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/\r
-typedef struct /* Common Registers */\r
-{\r
- __I uint32_t DMACIntStat;\r
- __I uint32_t DMACIntTCStat;\r
- __O uint32_t DMACIntTCClear;\r
- __I uint32_t DMACIntErrStat;\r
- __O uint32_t DMACIntErrClr;\r
- __I uint32_t DMACRawIntTCStat;\r
- __I uint32_t DMACRawIntErrStat;\r
- __I uint32_t DMACEnbldChns;\r
- __IO uint32_t DMACSoftBReq;\r
- __IO uint32_t DMACSoftSReq;\r
- __IO uint32_t DMACSoftLBReq;\r
- __IO uint32_t DMACSoftLSReq;\r
- __IO uint32_t DMACConfig;\r
- __IO uint32_t DMACSync;\r
-} GPDMA_TypeDef;\r
-\r
-typedef struct /* Channel Registers */\r
-{\r
- __IO uint32_t DMACCSrcAddr;\r
- __IO uint32_t DMACCDestAddr;\r
- __IO uint32_t DMACCLLI;\r
- __IO uint32_t DMACCControl;\r
- __IO uint32_t DMACCConfig;\r
-} GPDMACH_TypeDef;\r
-\r
-/*------------- Universal Serial Bus (USB) -----------------------------------*/\r
-typedef struct\r
-{\r
- __I uint32_t HcRevision; /* USB Host Registers */\r
- __IO uint32_t HcControl;\r
- __IO uint32_t HcCommandStatus;\r
- __IO uint32_t HcInterruptStatus;\r
- __IO uint32_t HcInterruptEnable;\r
- __IO uint32_t HcInterruptDisable;\r
- __IO uint32_t HcHCCA;\r
- __I uint32_t HcPeriodCurrentED;\r
- __IO uint32_t HcControlHeadED;\r
- __IO uint32_t HcControlCurrentED;\r
- __IO uint32_t HcBulkHeadED;\r
- __IO uint32_t HcBulkCurrentED;\r
- __I uint32_t HcDoneHead;\r
- __IO uint32_t HcFmInterval;\r
- __I uint32_t HcFmRemaining;\r
- __I uint32_t HcFmNumber;\r
- __IO uint32_t HcPeriodicStart;\r
- __IO uint32_t HcLSTreshold;\r
- __IO uint32_t HcRhDescriptorA;\r
- __IO uint32_t HcRhDescriptorB;\r
- __IO uint32_t HcRhStatus;\r
- __IO uint32_t HcRhPortStatus1;\r
- __IO uint32_t HcRhPortStatus2;\r
- uint32_t RESERVED0[40];\r
- __I uint32_t Module_ID;\r
-\r
- __I uint32_t OTGIntSt; /* USB On-The-Go Registers */\r
- __IO uint32_t OTGIntEn;\r
- __O uint32_t OTGIntSet;\r
- __O uint32_t OTGIntClr;\r
- __IO uint32_t OTGStCtrl;\r
- __IO uint32_t OTGTmr;\r
- uint32_t RESERVED1[58];\r
-\r
- __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */\r
- __IO uint32_t USBDevIntEn;\r
- __O uint32_t USBDevIntClr;\r
- __O uint32_t USBDevIntSet;\r
-\r
- __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */\r
- __I uint32_t USBCmdData;\r
-\r
- __I uint32_t USBRxData; /* USB Device Transfer Registers */\r
- __O uint32_t USBTxData;\r
- __I uint32_t USBRxPLen;\r
- __O uint32_t USBTxPLen;\r
- __IO uint32_t USBCtrl;\r
- __O uint32_t USBDevIntPri;\r
-\r
- __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */\r
- __IO uint32_t USBEpIntEn;\r
- __O uint32_t USBEpIntClr;\r
- __O uint32_t USBEpIntSet;\r
- __O uint32_t USBEpIntPri;\r
-\r
- __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/\r
- __O uint32_t USBEpInd;\r
- __IO uint32_t USBMaxPSize;\r
-\r
- __I uint32_t USBDMARSt; /* USB Device DMA Registers */\r
- __O uint32_t USBDMARClr;\r
- __O uint32_t USBDMARSet;\r
- uint32_t RESERVED2[9];\r
- __IO uint32_t USBUDCAH;\r
- __I uint32_t USBEpDMASt;\r
- __O uint32_t USBEpDMAEn;\r
- __O uint32_t USBEpDMADis;\r
- __I uint32_t USBDMAIntSt;\r
- __IO uint32_t USBDMAIntEn;\r
- uint32_t RESERVED3[2];\r
- __I uint32_t USBEoTIntSt;\r
- __O uint32_t USBEoTIntClr;\r
- __O uint32_t USBEoTIntSet;\r
- __I uint32_t USBNDDRIntSt;\r
- __O uint32_t USBNDDRIntClr;\r
- __O uint32_t USBNDDRIntSet;\r
- __I uint32_t USBSysErrIntSt;\r
- __O uint32_t USBSysErrIntClr;\r
- __O uint32_t USBSysErrIntSet;\r
- uint32_t RESERVED4[15];\r
-\r
- __I uint32_t I2C_RX; /* USB OTG I2C Registers */\r
- __O uint32_t I2C_WO;\r
- __I uint32_t I2C_STS;\r
- __IO uint32_t I2C_CTL;\r
- __IO uint32_t I2C_CLKHI;\r
- __O uint32_t I2C_CLKLO;\r
- uint32_t RESERVED5[823];\r
-\r
- union {\r
- __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */\r
- __IO uint32_t OTGClkCtrl;\r
- };\r
- union {\r
- __I uint32_t USBClkSt;\r
- __I uint32_t OTGClkSt;\r
- };\r
-} USB_TypeDef;\r
-\r
-/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t MAC1; /* MAC Registers */\r
- __IO uint32_t MAC2;\r
- __IO uint32_t IPGT;\r
- __IO uint32_t IPGR;\r
- __IO uint32_t CLRT;\r
- __IO uint32_t MAXF;\r
- __IO uint32_t SUPP;\r
- __IO uint32_t TEST;\r
- __IO uint32_t MCFG;\r
- __IO uint32_t MCMD;\r
- __IO uint32_t MADR;\r
- __O uint32_t MWTD;\r
- __I uint32_t MRDD;\r
- __I uint32_t MIND;\r
- uint32_t RESERVED0[2];\r
- __IO uint32_t SA0;\r
- __IO uint32_t SA1;\r
- __IO uint32_t SA2;\r
- uint32_t RESERVED1[45];\r
- __IO uint32_t Command; /* Control Registers */\r
- __I uint32_t Status;\r
- __IO uint32_t RxDescriptor;\r
- __IO uint32_t RxStatus;\r
- __IO uint32_t RxDescriptorNumber;\r
- __I uint32_t RxProduceIndex;\r
- __IO uint32_t RxConsumeIndex;\r
- __IO uint32_t TxDescriptor;\r
- __IO uint32_t TxStatus;\r
- __IO uint32_t TxDescriptorNumber;\r
- __IO uint32_t TxProduceIndex;\r
- __I uint32_t TxConsumeIndex;\r
- uint32_t RESERVED2[10];\r
- __I uint32_t TSV0;\r
- __I uint32_t TSV1;\r
- __I uint32_t RSV;\r
- uint32_t RESERVED3[3];\r
- __IO uint32_t FlowControlCounter;\r
- __I uint32_t FlowControlStatus;\r
- uint32_t RESERVED4[34];\r
- __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */\r
- __IO uint32_t RxFilterWoLStatus;\r
- __IO uint32_t RxFilterWoLClear;\r
- uint32_t RESERVED5;\r
- __IO uint32_t HashFilterL;\r
- __IO uint32_t HashFilterH;\r
- uint32_t RESERVED6[882];\r
- __I uint32_t IntStatus; /* Module Control Registers */\r
- __IO uint32_t IntEnable;\r
- __O uint32_t IntClear;\r
- __O uint32_t IntSet;\r
- uint32_t RESERVED7;\r
- __IO uint32_t PowerDown;\r
- uint32_t RESERVED8;\r
- __IO uint32_t Module_ID;\r
-} EMAC_TypeDef;\r
-\r
-#pragma no_anon_unions\r
-\r
-\r
-/******************************************************************************/\r
-/* Peripheral memory map */\r
-/******************************************************************************/\r
-/* Base addresses */\r
-#define FLASH_BASE (0x00000000UL)\r
-#define RAM_BASE (0x10000000UL)\r
-#define GPIO_BASE (0x2009C000UL)\r
-#define APB0_BASE (0x40000000UL)\r
-#define APB1_BASE (0x40080000UL)\r
-#define AHB_BASE (0x50000000UL)\r
-#define CM3_BASE (0xE0000000UL)\r
-\r
-/* APB0 peripherals */\r
-#define WDT_BASE (APB0_BASE + 0x00000)\r
-#define TIM0_BASE (APB0_BASE + 0x04000)\r
-#define TIM1_BASE (APB0_BASE + 0x08000)\r
-#define UART0_BASE (APB0_BASE + 0x0C000)\r
-#define UART1_BASE (APB0_BASE + 0x10000)\r
-#define PWM1_BASE (APB0_BASE + 0x18000)\r
-#define I2C0_BASE (APB0_BASE + 0x1C000)\r
-#define SPI_BASE (APB0_BASE + 0x20000)\r
-#define RTC_BASE (APB0_BASE + 0x24000)\r
-#define GPIOINT_BASE (APB0_BASE + 0x28080)\r
-#define PINCON_BASE (APB0_BASE + 0x2C000)\r
-#define SSP1_BASE (APB0_BASE + 0x30000)\r
-#define ADC_BASE (APB0_BASE + 0x34000)\r
-#define CANAF_RAM_BASE (APB0_BASE + 0x38000)\r
-#define CANAF_BASE (APB0_BASE + 0x3C000)\r
-#define CANCR_BASE (APB0_BASE + 0x40000)\r
-#define CAN1_BASE (APB0_BASE + 0x44000)\r
-#define CAN2_BASE (APB0_BASE + 0x48000)\r
-#define I2C1_BASE (APB0_BASE + 0x5C000)\r
-\r
-/* APB1 peripherals */\r
-#define SSP0_BASE (APB1_BASE + 0x08000)\r
-#define DAC_BASE (APB1_BASE + 0x0C000)\r
-#define TIM2_BASE (APB1_BASE + 0x10000)\r
-#define TIM3_BASE (APB1_BASE + 0x14000)\r
-#define UART2_BASE (APB1_BASE + 0x18000)\r
-#define UART3_BASE (APB1_BASE + 0x1C000)\r
-#define I2C2_BASE (APB1_BASE + 0x20000)\r
-#define I2S_BASE (APB1_BASE + 0x28000)\r
-#define RIT_BASE (APB1_BASE + 0x30000)\r
-#define MCPWM_BASE (APB1_BASE + 0x38000)\r
-#define QEI_BASE (APB1_BASE + 0x3C000)\r
-#define SC_BASE (APB1_BASE + 0x7C000)\r
-\r
-/* AHB peripherals */\r
-#define EMAC_BASE (AHB_BASE + 0x00000)\r
-#define GPDMA_BASE (AHB_BASE + 0x04000)\r
-#define GPDMACH0_BASE (AHB_BASE + 0x04100)\r
-#define GPDMACH1_BASE (AHB_BASE + 0x04120)\r
-#define GPDMACH2_BASE (AHB_BASE + 0x04140)\r
-#define GPDMACH3_BASE (AHB_BASE + 0x04160)\r
-#define GPDMACH4_BASE (AHB_BASE + 0x04180)\r
-#define GPDMACH5_BASE (AHB_BASE + 0x041A0)\r
-#define GPDMACH6_BASE (AHB_BASE + 0x041C0)\r
-#define GPDMACH7_BASE (AHB_BASE + 0x041E0)\r
-#define USB_BASE (AHB_BASE + 0x0C000)\r
-\r
-/* GPIOs */\r
-#define GPIO0_BASE (GPIO_BASE + 0x00000)\r
-#define GPIO1_BASE (GPIO_BASE + 0x00020)\r
-#define GPIO2_BASE (GPIO_BASE + 0x00040)\r
-#define GPIO3_BASE (GPIO_BASE + 0x00060)\r
-#define GPIO4_BASE (GPIO_BASE + 0x00080)\r
-\r
-\r
-/******************************************************************************/\r
-/* Peripheral declaration */\r
-/******************************************************************************/\r
-#define SC (( SC_TypeDef *) SC_BASE)\r
-#define GPIO0 (( GPIO_TypeDef *) GPIO0_BASE)\r
-#define GPIO1 (( GPIO_TypeDef *) GPIO1_BASE)\r
-#define GPIO2 (( GPIO_TypeDef *) GPIO2_BASE)\r
-#define GPIO3 (( GPIO_TypeDef *) GPIO3_BASE)\r
-#define GPIO4 (( GPIO_TypeDef *) GPIO4_BASE)\r
-#define WDT (( WDT_TypeDef *) WDT_BASE)\r
-#define TIM0 (( TIM_TypeDef *) TIM0_BASE)\r
-#define TIM1 (( TIM_TypeDef *) TIM1_BASE)\r
-#define TIM2 (( TIM_TypeDef *) TIM2_BASE)\r
-#define TIM3 (( TIM_TypeDef *) TIM3_BASE)\r
-#define RIT (( RIT_TypeDef *) RIT_BASE)\r
-#define UART0 (( UART_TypeDef *) UART0_BASE)\r
-#define UART1 (( UART1_TypeDef *) UART1_BASE)\r
-#define UART2 (( UART_TypeDef *) UART2_BASE)\r
-#define UART3 (( UART_TypeDef *) UART3_BASE)\r
-#define PWM1 (( PWM_TypeDef *) PWM1_BASE)\r
-#define I2C0 (( I2C_TypeDef *) I2C0_BASE)\r
-#define I2C1 (( I2C_TypeDef *) I2C1_BASE)\r
-#define I2C2 (( I2C_TypeDef *) I2C2_BASE)\r
-#define I2S (( I2S_TypeDef *) I2S_BASE)\r
-#define SPI (( SPI_TypeDef *) SPI_BASE)\r
-#define RTC (( RTC_TypeDef *) RTC_BASE)\r
-#define GPIOINT (( GPIOINT_TypeDef *) GPIOINT_BASE)\r
-#define PINCON (( PINCON_TypeDef *) PINCON_BASE)\r
-#define SSP0 (( SSP_TypeDef *) SSP0_BASE)\r
-#define SSP1 (( SSP_TypeDef *) SSP1_BASE)\r
-#define ADC (( ADC_TypeDef *) ADC_BASE)\r
-#define DAC (( DAC_TypeDef *) DAC_BASE)\r
-#define CANAF_RAM ((CANAF_RAM_TypeDef *) CANAF_RAM_BASE)\r
-#define CANAF (( CANAF_TypeDef *) CANAF_BASE)\r
-#define CANCR (( CANCR_TypeDef *) CANCR_BASE)\r
-#define CAN1 (( CAN_TypeDef *) CAN1_BASE)\r
-#define CAN2 (( CAN_TypeDef *) CAN2_BASE)\r
-#define MCPWM (( MCPWM_TypeDef *) MCPWM_BASE)\r
-#define QEI (( QEI_TypeDef *) QEI_BASE)\r
-#define EMAC (( EMAC_TypeDef *) EMAC_BASE)\r
-#define GPDMA (( GPDMA_TypeDef *) GPDMA_BASE)\r
-#define GPDMACH0 (( GPDMACH_TypeDef *) GPDMACH0_BASE)\r
-#define GPDMACH1 (( GPDMACH_TypeDef *) GPDMACH1_BASE)\r
-#define GPDMACH2 (( GPDMACH_TypeDef *) GPDMACH2_BASE)\r
-#define GPDMACH3 (( GPDMACH_TypeDef *) GPDMACH3_BASE)\r
-#define GPDMACH4 (( GPDMACH_TypeDef *) GPDMACH4_BASE)\r
-#define GPDMACH5 (( GPDMACH_TypeDef *) GPDMACH5_BASE)\r
-#define GPDMACH6 (( GPDMACH_TypeDef *) GPDMACH6_BASE)\r
-#define GPDMACH7 (( GPDMACH_TypeDef *) GPDMACH7_BASE)\r
-#define USB (( USB_TypeDef *) USB_BASE)\r
-\r
-#endif // __LPC17xx_H__\r
+/******************************************************************************
+ * @file: LPC17xx.h
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
+ * NXP LPC17xx Device Series
+ * @version: V1.1
+ * @date: 14th May 2009
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2008 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __LPC17xx_H__
+#define __LPC17xx_H__
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** LPC17xx Specific Interrupt Numbers *******************************************************/
+ WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
+ TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
+ TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
+ TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
+ TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
+ UART0_IRQn = 5, /*!< UART0 Interrupt */
+ UART1_IRQn = 6, /*!< UART1 Interrupt */
+ UART2_IRQn = 7, /*!< UART2 Interrupt */
+ UART3_IRQn = 8, /*!< UART3 Interrupt */
+ PWM1_IRQn = 9, /*!< PWM1 Interrupt */
+ I2C0_IRQn = 10, /*!< I2C0 Interrupt */
+ I2C1_IRQn = 11, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 12, /*!< I2C2 Interrupt */
+ SPI_IRQn = 13, /*!< SPI Interrupt */
+ SSP0_IRQn = 14, /*!< SSP0 Interrupt */
+ SSP1_IRQn = 15, /*!< SSP1 Interrupt */
+ PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
+ RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
+ EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
+ EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
+ EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
+ EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
+ ADC_IRQn = 22, /*!< A/D Converter Interrupt */
+ BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
+ USB_IRQn = 24, /*!< USB Interrupt */
+ CAN_IRQn = 25, /*!< CAN Interrupt */
+ DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
+ I2S_IRQn = 27, /*!< I2S Interrupt */
+ ENET_IRQn = 28, /*!< Ethernet Interrupt */
+ RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
+ MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
+ QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
+ PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+
+#include "../cortex_m3/core_cm3.h" /* Cortex-M3 processor and core peripherals */
+#include "system.h" /* System Header */
+
+
+
+/**
+ * Initialize the system clock
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemFrequency variable.
+ */
+extern void SystemInit (void);
+
+
+/******************************************************************************/
+/* Device Specific Peripheral registers structures */
+/******************************************************************************/
+
+#pragma anon_unions
+
+/*------------- System Control (SC) ------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
+ uint32_t RESERVED0[31];
+ __IO uint32_t PLL0CON; /* Clocking and Power Control */
+ __IO uint32_t PLL0CFG;
+ __I uint32_t PLL0STAT;
+ __O uint32_t PLL0FEED;
+ uint32_t RESERVED1[4];
+ __IO uint32_t PLL1CON;
+ __IO uint32_t PLL1CFG;
+ __I uint32_t PLL1STAT;
+ __O uint32_t PLL1FEED;
+ uint32_t RESERVED2[4];
+ __IO uint32_t PCON;
+ __IO uint32_t PCONP;
+ uint32_t RESERVED3[15];
+ __IO uint32_t CCLKCFG;
+ __IO uint32_t USBCLKCFG;
+ __IO uint32_t CLKSRCSEL;
+ uint32_t RESERVED4[12];
+ __IO uint32_t EXTINT; /* External Interrupts */
+ uint32_t RESERVED5;
+ __IO uint32_t EXTMODE;
+ __IO uint32_t EXTPOLAR;
+ uint32_t RESERVED6[12];
+ __IO uint32_t RSID; /* Reset */
+ uint32_t RESERVED7[7];
+ __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
+ __IO uint32_t IRCTRIM; /* Clock Dividers */
+ __IO uint32_t PCLKSEL0;
+ __IO uint32_t PCLKSEL1;
+ uint32_t RESERVED8[4];
+ __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
+ uint32_t RESERVED9;
+ __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
+ } SC_TypeDef;
+
+/*------------- Pin Connect Block (PINCON) -----------------------------------*/
+typedef struct
+{
+ __IO uint32_t PINSEL0;
+ __IO uint32_t PINSEL1;
+ __IO uint32_t PINSEL2;
+ __IO uint32_t PINSEL3;
+ __IO uint32_t PINSEL4;
+ __IO uint32_t PINSEL5;
+ __IO uint32_t PINSEL6;
+ __IO uint32_t PINSEL7;
+ __IO uint32_t PINSEL8;
+ __IO uint32_t PINSEL9;
+ __IO uint32_t PINSEL10;
+ uint32_t RESERVED0[5];
+ __IO uint32_t PINMODE0;
+ __IO uint32_t PINMODE1;
+ __IO uint32_t PINMODE2;
+ __IO uint32_t PINMODE3;
+ __IO uint32_t PINMODE4;
+ __IO uint32_t PINMODE5;
+ __IO uint32_t PINMODE6;
+ __IO uint32_t PINMODE7;
+ __IO uint32_t PINMODE8;
+ __IO uint32_t PINMODE9;
+ __IO uint32_t PINMODE_OD0;
+ __IO uint32_t PINMODE_OD1;
+ __IO uint32_t PINMODE_OD2;
+ __IO uint32_t PINMODE_OD3;
+ __IO uint32_t PINMODE_OD4;
+} PINCON_TypeDef;
+
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+typedef struct
+{
+ __IO uint32_t FIODIR;
+ uint32_t RESERVED0[3];
+ __IO uint32_t FIOMASK;
+ __IO uint32_t FIOPIN;
+ __IO uint32_t FIOSET;
+ __O uint32_t FIOCLR;
+} GPIO_TypeDef;
+
+typedef struct
+{
+ __I uint32_t IntStatus;
+ __I uint32_t IO0IntStatR;
+ __I uint32_t IO0IntStatF;
+ __O uint32_t IO0IntClr;
+ __IO uint32_t IO0IntEnR;
+ __IO uint32_t IO0IntEnF;
+ uint32_t RESERVED0[3];
+ __I uint32_t IO2IntStatR;
+ __I uint32_t IO2IntStatF;
+ __O uint32_t IO2IntClr;
+ __IO uint32_t IO2IntEnR;
+ __IO uint32_t IO2IntEnF;
+} GPIOINT_TypeDef;
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR;
+ __IO uint32_t TCR;
+ __IO uint32_t TC;
+ __IO uint32_t PR;
+ __IO uint32_t PC;
+ __IO uint32_t MCR;
+ __IO uint32_t MR0;
+ __IO uint32_t MR1;
+ __IO uint32_t MR2;
+ __IO uint32_t MR3;
+ __IO uint32_t CCR;
+ __I uint32_t CR0;
+ __I uint32_t CR1;
+ uint32_t RESERVED0[2];
+ __IO uint32_t EMR;
+ uint32_t RESERVED1[24];
+ __IO uint32_t CTCR;
+} TIM_TypeDef;
+
+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR;
+ __IO uint32_t TCR;
+ __IO uint32_t TC;
+ __IO uint32_t PR;
+ __IO uint32_t PC;
+ __IO uint32_t MCR;
+ __IO uint32_t MR0;
+ __IO uint32_t MR1;
+ __IO uint32_t MR2;
+ __IO uint32_t MR3;
+ __IO uint32_t CCR;
+ __I uint32_t CR0;
+ __I uint32_t CR1;
+ __I uint32_t CR2;
+ __I uint32_t CR3;
+ __IO uint32_t MR4;
+ __IO uint32_t MR5;
+ __IO uint32_t MR6;
+ __IO uint32_t PCR;
+ __IO uint32_t LER;
+ uint32_t RESERVED0[7];
+ __IO uint32_t CTCR;
+} PWM_TypeDef;
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];
+ __IO uint8_t LSR;
+ uint8_t RESERVED2[7];
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];
+ __IO uint8_t TER;
+ uint8_t RESERVED6[27];
+ __IO uint8_t RS485CTRL;
+ uint8_t RESERVED7[3];
+ __IO uint8_t ADRMATCH;
+} UART_TypeDef;
+
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t MCR;
+ uint8_t RESERVED2[3];
+ __IO uint8_t LSR;
+ uint8_t RESERVED3[3];
+ __IO uint8_t MSR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t SCR;
+ uint8_t RESERVED5[3];
+ __IO uint32_t ACR;
+ uint32_t RESERVED6;
+ __IO uint32_t FDR;
+ uint32_t RESERVED7;
+ __IO uint8_t TER;
+ uint8_t RESERVED8[27];
+ __IO uint8_t RS485CTRL;
+ uint8_t RESERVED9[3];
+ __IO uint8_t ADRMATCH;
+ uint8_t RESERVED10[3];
+ __IO uint8_t RS485DLY;
+} UART1_TypeDef;
+
+/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t SPCR;
+ __I uint32_t SPSR;
+ __IO uint32_t SPDR;
+ __IO uint32_t SPCCR;
+ uint32_t RESERVED0[3];
+ __IO uint32_t SPINT;
+} SPI_TypeDef;
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+typedef struct
+{
+ __IO uint32_t CR0;
+ __IO uint32_t CR1;
+ __IO uint32_t DR;
+ __I uint32_t SR;
+ __IO uint32_t CPSR;
+ __IO uint32_t IMSC;
+ __IO uint32_t RIS;
+ __IO uint32_t MIS;
+ __IO uint32_t ICR;
+ __IO uint32_t DMACR;
+} SSP_TypeDef;
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+typedef struct
+{
+ __IO uint32_t I2CONSET;
+ __I uint32_t I2STAT;
+ __IO uint32_t I2DAT;
+ __IO uint32_t I2ADR0;
+ __IO uint32_t I2SCLH;
+ __IO uint32_t I2SCLL;
+ __O uint32_t I2CONCLR;
+ __IO uint32_t MMCTRL;
+ __IO uint32_t I2ADR1;
+ __IO uint32_t I2ADR2;
+ __IO uint32_t I2ADR3;
+ __I uint32_t I2DATA_BUFFER;
+ __IO uint32_t I2MASK0;
+ __IO uint32_t I2MASK1;
+ __IO uint32_t I2MASK2;
+ __IO uint32_t I2MASK3;
+} I2C_TypeDef;
+
+/*------------- Inter IC Sound (I2S) -----------------------------------------*/
+typedef struct
+{
+ __IO uint32_t I2SDAO;
+ __I uint32_t I2SDAI;
+ __O uint32_t I2STXFIFO;
+ __I uint32_t I2SRXFIFO;
+ __I uint32_t I2SSTATE;
+ __IO uint32_t I2SDMA1;
+ __IO uint32_t I2SDMA2;
+ __IO uint32_t I2SIRQ;
+ __IO uint32_t I2STXRATE;
+ __IO uint32_t I2SRXRATE;
+ __IO uint32_t I2STXBITRATE;
+ __IO uint32_t I2SRXBITRATE;
+ __IO uint32_t I2STXMODE;
+ __IO uint32_t I2SRXMODE;
+} I2S_TypeDef;
+
+/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
+typedef struct
+{
+ __IO uint32_t RICOMPVAL;
+ __IO uint32_t RIMASK;
+ __IO uint8_t RICTRL;
+ uint8_t RESERVED0[3];
+ __IO uint32_t RICOUNTER;
+} RIT_TypeDef;
+
+/*------------- Real-Time Clock (RTC) ----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t ILR;
+ uint8_t RESERVED0[3];
+ __IO uint8_t CCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t CIIR;
+ uint8_t RESERVED2[3];
+ __IO uint8_t AMR;
+ uint8_t RESERVED3[3];
+ __I uint32_t CTIME0;
+ __I uint32_t CTIME1;
+ __I uint32_t CTIME2;
+ __IO uint8_t SEC;
+ uint8_t RESERVED4[3];
+ __IO uint8_t MIN;
+ uint8_t RESERVED5[3];
+ __IO uint8_t HOUR;
+ uint8_t RESERVED6[3];
+ __IO uint8_t DOM;
+ uint8_t RESERVED7[3];
+ __IO uint8_t DOW;
+ uint8_t RESERVED8[3];
+ __IO uint16_t DOY;
+ uint16_t RESERVED9;
+ __IO uint8_t MONTH;
+ uint8_t RESERVED10[3];
+ __IO uint16_t YEAR;
+ uint16_t RESERVED11;
+ __IO uint32_t CALIBRATION;
+ __IO uint32_t GPREG0;
+ __IO uint32_t GPREG1;
+ __IO uint32_t GPREG2;
+ __IO uint32_t GPREG3;
+ __IO uint32_t GPREG4;
+ __IO uint8_t WAKEUPDIS;
+ uint8_t RESERVED12[3];
+ __IO uint8_t PWRCTRL;
+ uint8_t RESERVED13[3];
+ __IO uint8_t ALSEC;
+ uint8_t RESERVED14[3];
+ __IO uint8_t ALMIN;
+ uint8_t RESERVED15[3];
+ __IO uint8_t ALHOUR;
+ uint8_t RESERVED16[3];
+ __IO uint8_t ALDOM;
+ uint8_t RESERVED17[3];
+ __IO uint8_t ALDOW;
+ uint8_t RESERVED18[3];
+ __IO uint16_t ALDOY;
+ uint16_t RESERVED19;
+ __IO uint8_t ALMON;
+ uint8_t RESERVED20[3];
+ __IO uint16_t ALYEAR;
+ uint16_t RESERVED21;
+} RTC_TypeDef;
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t WDMOD;
+ uint8_t RESERVED0[3];
+ __IO uint32_t WDTC;
+ __O uint8_t WDFEED;
+ uint8_t RESERVED1[3];
+ __I uint32_t WDTV;
+ __IO uint32_t WDCLKSEL;
+} WDT_TypeDef;
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t ADCR;
+ __IO uint32_t ADGDR;
+ uint32_t RESERVED0;
+ __IO uint32_t ADINTEN;
+ __I uint32_t ADDR0;
+ __I uint32_t ADDR1;
+ __I uint32_t ADDR2;
+ __I uint32_t ADDR3;
+ __I uint32_t ADDR4;
+ __I uint32_t ADDR5;
+ __I uint32_t ADDR6;
+ __I uint32_t ADDR7;
+ __I uint32_t ADSTAT;
+ __IO uint32_t ADTRM;
+} ADC_TypeDef;
+
+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t DACR;
+ __IO uint32_t DACCTRL;
+ __IO uint16_t DACCNTVAL;
+} DAC_TypeDef;
+
+/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
+typedef struct
+{
+ __I uint32_t MCCON;
+ __O uint32_t MCCON_SET;
+ __O uint32_t MCCON_CLR;
+ __I uint32_t MCCAPCON;
+ __O uint32_t MCCAPCON_SET;
+ __O uint32_t MCCAPCON_CLR;
+ __IO uint32_t MCTIM0;
+ __IO uint32_t MCTIM1;
+ __IO uint32_t MCTIM2;
+ __IO uint32_t MCPER0;
+ __IO uint32_t MCPER1;
+ __IO uint32_t MCPER2;
+ __IO uint32_t MCPW0;
+ __IO uint32_t MCPW1;
+ __IO uint32_t MCPW2;
+ __IO uint32_t MCDEADTIME;
+ __IO uint32_t MCCCP;
+ __IO uint32_t MCCR0;
+ __IO uint32_t MCCR1;
+ __IO uint32_t MCCR2;
+ __I uint32_t MCINTEN;
+ __O uint32_t MCINTEN_SET;
+ __O uint32_t MCINTEN_CLR;
+ __I uint32_t MCCNTCON;
+ __O uint32_t MCCNTCON_SET;
+ __O uint32_t MCCNTCON_CLR;
+ __I uint32_t MCINTFLAG;
+ __O uint32_t MCINTFLAG_SET;
+ __O uint32_t MCINTFLAG_CLR;
+ __O uint32_t MCCAP_CLR;
+} MCPWM_TypeDef;
+
+/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
+typedef struct
+{
+ __O uint32_t QEICON;
+ __I uint32_t QEISTAT;
+ __IO uint32_t QEICONF;
+ __I uint32_t QEIPOS;
+ __IO uint32_t QEIMAXPOS;
+ __IO uint32_t CMPOS0;
+ __IO uint32_t CMPOS1;
+ __IO uint32_t CMPOS2;
+ __I uint32_t INXCNT;
+ __IO uint32_t INXCMP;
+ __IO uint32_t QEILOAD;
+ __I uint32_t QEITIME;
+ __I uint32_t QEIVEL;
+ __I uint32_t QEICAP;
+ __IO uint32_t VELCOMP;
+ __IO uint32_t FILTER;
+ uint32_t RESERVED0[998];
+ __O uint32_t QEIIEC;
+ __O uint32_t QEIIES;
+ __I uint32_t QEIINTSTAT;
+ __I uint32_t QEIIE;
+ __O uint32_t QEICLR;
+ __O uint32_t QEISET;
+} QEI_TypeDef;
+
+/*------------- Controller Area Network (CAN) --------------------------------*/
+typedef struct
+{
+ __IO uint32_t mask[512]; /* ID Masks */
+} CANAF_RAM_TypeDef;
+
+typedef struct /* Acceptance Filter Registers */
+{
+ __IO uint32_t AFMR;
+ __IO uint32_t SFF_sa;
+ __IO uint32_t SFF_GRP_sa;
+ __IO uint32_t EFF_sa;
+ __IO uint32_t EFF_GRP_sa;
+ __IO uint32_t ENDofTable;
+ __I uint32_t LUTerrAd;
+ __I uint32_t LUTerr;
+} CANAF_TypeDef;
+
+typedef struct /* Central Registers */
+{
+ __I uint32_t CANTxSR;
+ __I uint32_t CANRxSR;
+ __I uint32_t CANMSR;
+} CANCR_TypeDef;
+
+typedef struct /* Controller Registers */
+{
+ __IO uint32_t MOD;
+ __O uint32_t CMR;
+ __IO uint32_t GSR;
+ __I uint32_t ICR;
+ __IO uint32_t IER;
+ __IO uint32_t BTR;
+ __IO uint32_t EWL;
+ __I uint32_t SR;
+ __IO uint32_t RFS;
+ __IO uint32_t RID;
+ __IO uint32_t RDA;
+ __IO uint32_t RDB;
+ __IO uint32_t TFI1;
+ __IO uint32_t TID1;
+ __IO uint32_t TDA1;
+ __IO uint32_t TDB1;
+ __IO uint32_t TFI2;
+ __IO uint32_t TID2;
+ __IO uint32_t TDA2;
+ __IO uint32_t TDB2;
+ __IO uint32_t TFI3;
+ __IO uint32_t TID3;
+ __IO uint32_t TDA3;
+ __IO uint32_t TDB3;
+} CAN_TypeDef;
+
+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
+typedef struct /* Common Registers */
+{
+ __I uint32_t DMACIntStat;
+ __I uint32_t DMACIntTCStat;
+ __O uint32_t DMACIntTCClear;
+ __I uint32_t DMACIntErrStat;
+ __O uint32_t DMACIntErrClr;
+ __I uint32_t DMACRawIntTCStat;
+ __I uint32_t DMACRawIntErrStat;
+ __I uint32_t DMACEnbldChns;
+ __IO uint32_t DMACSoftBReq;
+ __IO uint32_t DMACSoftSReq;
+ __IO uint32_t DMACSoftLBReq;
+ __IO uint32_t DMACSoftLSReq;
+ __IO uint32_t DMACConfig;
+ __IO uint32_t DMACSync;
+} GPDMA_TypeDef;
+
+typedef struct /* Channel Registers */
+{
+ __IO uint32_t DMACCSrcAddr;
+ __IO uint32_t DMACCDestAddr;
+ __IO uint32_t DMACCLLI;
+ __IO uint32_t DMACCControl;
+ __IO uint32_t DMACCConfig;
+} GPDMACH_TypeDef;
+
+/*------------- Universal Serial Bus (USB) -----------------------------------*/
+typedef struct
+{
+ __I uint32_t HcRevision; /* USB Host Registers */
+ __IO uint32_t HcControl;
+ __IO uint32_t HcCommandStatus;
+ __IO uint32_t HcInterruptStatus;
+ __IO uint32_t HcInterruptEnable;
+ __IO uint32_t HcInterruptDisable;
+ __IO uint32_t HcHCCA;
+ __I uint32_t HcPeriodCurrentED;
+ __IO uint32_t HcControlHeadED;
+ __IO uint32_t HcControlCurrentED;
+ __IO uint32_t HcBulkHeadED;
+ __IO uint32_t HcBulkCurrentED;
+ __I uint32_t HcDoneHead;
+ __IO uint32_t HcFmInterval;
+ __I uint32_t HcFmRemaining;
+ __I uint32_t HcFmNumber;
+ __IO uint32_t HcPeriodicStart;
+ __IO uint32_t HcLSTreshold;
+ __IO uint32_t HcRhDescriptorA;
+ __IO uint32_t HcRhDescriptorB;
+ __IO uint32_t HcRhStatus;
+ __IO uint32_t HcRhPortStatus1;
+ __IO uint32_t HcRhPortStatus2;
+ uint32_t RESERVED0[40];
+ __I uint32_t Module_ID;
+
+ __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
+ __IO uint32_t OTGIntEn;
+ __O uint32_t OTGIntSet;
+ __O uint32_t OTGIntClr;
+ __IO uint32_t OTGStCtrl;
+ __IO uint32_t OTGTmr;
+ uint32_t RESERVED1[58];
+
+ __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
+ __IO uint32_t USBDevIntEn;
+ __O uint32_t USBDevIntClr;
+ __O uint32_t USBDevIntSet;
+
+ __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
+ __I uint32_t USBCmdData;
+
+ __I uint32_t USBRxData; /* USB Device Transfer Registers */
+ __O uint32_t USBTxData;
+ __I uint32_t USBRxPLen;
+ __O uint32_t USBTxPLen;
+ __IO uint32_t USBCtrl;
+ __O uint32_t USBDevIntPri;
+
+ __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
+ __IO uint32_t USBEpIntEn;
+ __O uint32_t USBEpIntClr;
+ __O uint32_t USBEpIntSet;
+ __O uint32_t USBEpIntPri;
+
+ __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
+ __O uint32_t USBEpInd;
+ __IO uint32_t USBMaxPSize;
+
+ __I uint32_t USBDMARSt; /* USB Device DMA Registers */
+ __O uint32_t USBDMARClr;
+ __O uint32_t USBDMARSet;
+ uint32_t RESERVED2[9];
+ __IO uint32_t USBUDCAH;
+ __I uint32_t USBEpDMASt;
+ __O uint32_t USBEpDMAEn;
+ __O uint32_t USBEpDMADis;
+ __I uint32_t USBDMAIntSt;
+ __IO uint32_t USBDMAIntEn;
+ uint32_t RESERVED3[2];
+ __I uint32_t USBEoTIntSt;
+ __O uint32_t USBEoTIntClr;
+ __O uint32_t USBEoTIntSet;
+ __I uint32_t USBNDDRIntSt;
+ __O uint32_t USBNDDRIntClr;
+ __O uint32_t USBNDDRIntSet;
+ __I uint32_t USBSysErrIntSt;
+ __O uint32_t USBSysErrIntClr;
+ __O uint32_t USBSysErrIntSet;
+ uint32_t RESERVED4[15];
+
+ __I uint32_t I2C_RX; /* USB OTG I2C Registers */
+ __O uint32_t I2C_WO;
+ __I uint32_t I2C_STS;
+ __IO uint32_t I2C_CTL;
+ __IO uint32_t I2C_CLKHI;
+ __O uint32_t I2C_CLKLO;
+ uint32_t RESERVED5[823];
+
+ union {
+ __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
+ __IO uint32_t OTGClkCtrl;
+ };
+ union {
+ __I uint32_t USBClkSt;
+ __I uint32_t OTGClkSt;
+ };
+} USB_TypeDef;
+
+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
+typedef struct
+{
+ __IO uint32_t MAC1; /* MAC Registers */
+ __IO uint32_t MAC2;
+ __IO uint32_t IPGT;
+ __IO uint32_t IPGR;
+ __IO uint32_t CLRT;
+ __IO uint32_t MAXF;
+ __IO uint32_t SUPP;
+ __IO uint32_t TEST;
+ __IO uint32_t MCFG;
+ __IO uint32_t MCMD;
+ __IO uint32_t MADR;
+ __O uint32_t MWTD;
+ __I uint32_t MRDD;
+ __I uint32_t MIND;
+ uint32_t RESERVED0[2];
+ __IO uint32_t SA0;
+ __IO uint32_t SA1;
+ __IO uint32_t SA2;
+ uint32_t RESERVED1[45];
+ __IO uint32_t Command; /* Control Registers */
+ __I uint32_t Status;
+ __IO uint32_t RxDescriptor;
+ __IO uint32_t RxStatus;
+ __IO uint32_t RxDescriptorNumber;
+ __I uint32_t RxProduceIndex;
+ __IO uint32_t RxConsumeIndex;
+ __IO uint32_t TxDescriptor;
+ __IO uint32_t TxStatus;
+ __IO uint32_t TxDescriptorNumber;
+ __IO uint32_t TxProduceIndex;
+ __I uint32_t TxConsumeIndex;
+ uint32_t RESERVED2[10];
+ __I uint32_t TSV0;
+ __I uint32_t TSV1;
+ __I uint32_t RSV;
+ uint32_t RESERVED3[3];
+ __IO uint32_t FlowControlCounter;
+ __I uint32_t FlowControlStatus;
+ uint32_t RESERVED4[34];
+ __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
+ __IO uint32_t RxFilterWoLStatus;
+ __IO uint32_t RxFilterWoLClear;
+ uint32_t RESERVED5;
+ __IO uint32_t HashFilterL;
+ __IO uint32_t HashFilterH;
+ uint32_t RESERVED6[882];
+ __I uint32_t IntStatus; /* Module Control Registers */
+ __IO uint32_t IntEnable;
+ __O uint32_t IntClear;
+ __O uint32_t IntSet;
+ uint32_t RESERVED7;
+ __IO uint32_t PowerDown;
+ uint32_t RESERVED8;
+ __IO uint32_t Module_ID;
+} EMAC_TypeDef;
+
+#pragma no_anon_unions
+
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Base addresses */
+#define FLASH_BASE (0x00000000UL)
+#define RAM_BASE (0x10000000UL)
+#define GPIO_BASE (0x2009C000UL)
+#define APB0_BASE (0x40000000UL)
+#define APB1_BASE (0x40080000UL)
+#define AHB_BASE (0x50000000UL)
+#define CM3_BASE (0xE0000000UL)
+
+/* APB0 peripherals */
+#define WDT_BASE (APB0_BASE + 0x00000)
+#define TIM0_BASE (APB0_BASE + 0x04000)
+#define TIM1_BASE (APB0_BASE + 0x08000)
+#define UART0_BASE (APB0_BASE + 0x0C000)
+#define UART1_BASE (APB0_BASE + 0x10000)
+#define PWM1_BASE (APB0_BASE + 0x18000)
+#define I2C0_BASE (APB0_BASE + 0x1C000)
+#define SPI_BASE (APB0_BASE + 0x20000)
+#define RTC_BASE (APB0_BASE + 0x24000)
+#define GPIOINT_BASE (APB0_BASE + 0x28080)
+#define PINCON_BASE (APB0_BASE + 0x2C000)
+#define SSP1_BASE (APB0_BASE + 0x30000)
+#define ADC_BASE (APB0_BASE + 0x34000)
+#define CANAF_RAM_BASE (APB0_BASE + 0x38000)
+#define CANAF_BASE (APB0_BASE + 0x3C000)
+#define CANCR_BASE (APB0_BASE + 0x40000)
+#define CAN1_BASE (APB0_BASE + 0x44000)
+#define CAN2_BASE (APB0_BASE + 0x48000)
+#define I2C1_BASE (APB0_BASE + 0x5C000)
+
+/* APB1 peripherals */
+#define SSP0_BASE (APB1_BASE + 0x08000)
+#define DAC_BASE (APB1_BASE + 0x0C000)
+#define TIM2_BASE (APB1_BASE + 0x10000)
+#define TIM3_BASE (APB1_BASE + 0x14000)
+#define UART2_BASE (APB1_BASE + 0x18000)
+#define UART3_BASE (APB1_BASE + 0x1C000)
+#define I2C2_BASE (APB1_BASE + 0x20000)
+#define I2S_BASE (APB1_BASE + 0x28000)
+#define RIT_BASE (APB1_BASE + 0x30000)
+#define MCPWM_BASE (APB1_BASE + 0x38000)
+#define QEI_BASE (APB1_BASE + 0x3C000)
+#define SC_BASE (APB1_BASE + 0x7C000)
+
+/* AHB peripherals */
+#define EMAC_BASE (AHB_BASE + 0x00000)
+#define GPDMA_BASE (AHB_BASE + 0x04000)
+#define GPDMACH0_BASE (AHB_BASE + 0x04100)
+#define GPDMACH1_BASE (AHB_BASE + 0x04120)
+#define GPDMACH2_BASE (AHB_BASE + 0x04140)
+#define GPDMACH3_BASE (AHB_BASE + 0x04160)
+#define GPDMACH4_BASE (AHB_BASE + 0x04180)
+#define GPDMACH5_BASE (AHB_BASE + 0x041A0)
+#define GPDMACH6_BASE (AHB_BASE + 0x041C0)
+#define GPDMACH7_BASE (AHB_BASE + 0x041E0)
+#define USB_BASE (AHB_BASE + 0x0C000)
+
+/* GPIOs */
+#define GPIO0_BASE (GPIO_BASE + 0x00000)
+#define GPIO1_BASE (GPIO_BASE + 0x00020)
+#define GPIO2_BASE (GPIO_BASE + 0x00040)
+#define GPIO3_BASE (GPIO_BASE + 0x00060)
+#define GPIO4_BASE (GPIO_BASE + 0x00080)
+
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+#define SC (( SC_TypeDef *) SC_BASE)
+#define GPIO0 (( GPIO_TypeDef *) GPIO0_BASE)
+#define GPIO1 (( GPIO_TypeDef *) GPIO1_BASE)
+#define GPIO2 (( GPIO_TypeDef *) GPIO2_BASE)
+#define GPIO3 (( GPIO_TypeDef *) GPIO3_BASE)
+#define GPIO4 (( GPIO_TypeDef *) GPIO4_BASE)
+#define WDT (( WDT_TypeDef *) WDT_BASE)
+#define TIM0 (( TIM_TypeDef *) TIM0_BASE)
+#define TIM1 (( TIM_TypeDef *) TIM1_BASE)
+#define TIM2 (( TIM_TypeDef *) TIM2_BASE)
+#define TIM3 (( TIM_TypeDef *) TIM3_BASE)
+#define RIT (( RIT_TypeDef *) RIT_BASE)
+#define UART0 (( UART_TypeDef *) UART0_BASE)
+#define UART1 (( UART1_TypeDef *) UART1_BASE)
+#define UART2 (( UART_TypeDef *) UART2_BASE)
+#define UART3 (( UART_TypeDef *) UART3_BASE)
+#define PWM1 (( PWM_TypeDef *) PWM1_BASE)
+#define I2C0 (( I2C_TypeDef *) I2C0_BASE)
+#define I2C1 (( I2C_TypeDef *) I2C1_BASE)
+#define I2C2 (( I2C_TypeDef *) I2C2_BASE)
+#define I2S (( I2S_TypeDef *) I2S_BASE)
+#define SPI (( SPI_TypeDef *) SPI_BASE)
+#define RTC (( RTC_TypeDef *) RTC_BASE)
+#define GPIOINT (( GPIOINT_TypeDef *) GPIOINT_BASE)
+#define PINCON (( PINCON_TypeDef *) PINCON_BASE)
+#define SSP0 (( SSP_TypeDef *) SSP0_BASE)
+#define SSP1 (( SSP_TypeDef *) SSP1_BASE)
+#define ADC (( ADC_TypeDef *) ADC_BASE)
+#define DAC (( DAC_TypeDef *) DAC_BASE)
+#define CANAF_RAM ((CANAF_RAM_TypeDef *) CANAF_RAM_BASE)
+#define CANAF (( CANAF_TypeDef *) CANAF_BASE)
+#define CANCR (( CANCR_TypeDef *) CANCR_BASE)
+#define CAN1 (( CAN_TypeDef *) CAN1_BASE)
+#define CAN2 (( CAN_TypeDef *) CAN2_BASE)
+#define MCPWM (( MCPWM_TypeDef *) MCPWM_BASE)
+#define QEI (( QEI_TypeDef *) QEI_BASE)
+#define EMAC (( EMAC_TypeDef *) EMAC_BASE)
+#define GPDMA (( GPDMA_TypeDef *) GPDMA_BASE)
+#define GPDMACH0 (( GPDMACH_TypeDef *) GPDMACH0_BASE)
+#define GPDMACH1 (( GPDMACH_TypeDef *) GPDMACH1_BASE)
+#define GPDMACH2 (( GPDMACH_TypeDef *) GPDMACH2_BASE)
+#define GPDMACH3 (( GPDMACH_TypeDef *) GPDMACH3_BASE)
+#define GPDMACH4 (( GPDMACH_TypeDef *) GPDMACH4_BASE)
+#define GPDMACH5 (( GPDMACH_TypeDef *) GPDMACH5_BASE)
+#define GPDMACH6 (( GPDMACH_TypeDef *) GPDMACH6_BASE)
+#define GPDMACH7 (( GPDMACH_TypeDef *) GPDMACH7_BASE)
+#define USB (( USB_TypeDef *) USB_BASE)
+
+#endif // __LPC17xx_H__
/*
* This is the NXP LPC1768 linker file for code running from flash.
*
- * TODO:
+ * TODO:
* - handle the exotic input sections (e.g. glue and veneer, C++ sections)
* - add additional Ethernet and USB RAM memory regions (2x16k)
* - add boot ROM memory regions
. = ALIGN(4);
_ebss = .;
} > ram
-
+
_sstack = ORIGIN(ram) + LENGTH(ram);
}
-//*****************************************************************************\r
-//\r
-// startup_gcc.c - Startup code for use with GNU tools.\r
-//\r
-// Copyright (c) 2009 Luminary Micro, Inc. All rights reserved.\r
-// Software License Agreement\r
-// \r
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
-// exclusively on LMI's microcontroller products.\r
-// \r
-// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. You may not combine\r
-// this software with "viral" open-source software in order to form a larger\r
-// program. Any use in violation of the foregoing restrictions may subject\r
-// the user to criminal sanctions under applicable laws, as well as to civil\r
-// liability for the breach of the terms and conditions of this license.\r
-// \r
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
-// \r
-// This is part of revision 32 of the Stellaris CMSIS Package.\r
-//\r
-//*****************************************************************************\r
-\r
-#define WEAK __attribute__ ((weak))\r
-\r
-//*****************************************************************************\r
-//\r
-// Forward declaration of the default fault handlers.\r
-//\r
-//*****************************************************************************\r
-void WEAK Reset_Handler(void);\r
-static void Default_Handler(void);\r
-void WEAK NMI_Handler(void);\r
-void WEAK HardFault_Handler(void);\r
-void WEAK MemManage_Handler(void);\r
-void WEAK BusFault_Handler(void);\r
-void WEAK UsageFault_Handler(void);\r
-void WEAK MemManage_Handler(void);\r
-void WEAK SVC_Handler(void);\r
-void WEAK DebugMon_Handler(void);\r
-void WEAK PendSV_Handler(void);\r
-void WEAK SysTick_Handler(void);\r
-void WEAK GPIOPortA_IRQHandler(void);\r
-void WEAK GPIOPortB_IRQHandler(void);\r
-void WEAK GPIOPortC_IRQHandler(void);\r
-void WEAK GPIOPortD_IRQHandler(void);\r
-void WEAK GPIOPortE_IRQHandler(void);\r
-void WEAK UART0_IRQHandler(void);\r
-void WEAK UART1_IRQHandler(void);\r
-void WEAK SSI0_IRQHandler(void);\r
-void WEAK I2C0_IRQHandler(void);\r
-void WEAK PWMFault_IRQHandler(void);\r
-void WEAK PWMGen0_IRQHandler(void);\r
-void WEAK PWMGen1_IRQHandler(void);\r
-void WEAK PWMGen2_IRQHandler(void);\r
-void WEAK QEI0_IRQHandler(void);\r
-void WEAK ADCSeq0_IRQHandler(void);\r
-void WEAK ADCSeq1_IRQHandler(void);\r
-void WEAK ADCSeq2_IRQHandler(void);\r
-void WEAK ADCSeq3_IRQHandler(void);\r
-void WEAK Watchdog_IRQHandler(void);\r
-void WEAK Timer0A_IRQHandler(void);\r
-void WEAK Timer0B_IRQHandler(void);\r
-void WEAK Timer1A_IRQHandler(void);\r
-void WEAK Timer1B_IRQHandler(void);\r
-void WEAK Timer2A_IRQHandler(void);\r
-void WEAK Timer2B_IRQHandler(void);\r
-void WEAK Comp0_IRQHandler(void);\r
-void WEAK Comp1_IRQHandler(void);\r
-void WEAK Comp2_IRQHandler(void);\r
-void WEAK SysCtrl_IRQHandler(void);\r
-void WEAK FlashCtrl_IRQHandler(void);\r
-void WEAK GPIOPortF_IRQHandler(void);\r
-void WEAK GPIOPortG_IRQHandler(void);\r
-void WEAK GPIOPortH_IRQHandler(void);\r
-void WEAK UART2_IRQHandler(void);\r
-void WEAK SSI1_IRQHandler(void);\r
-void WEAK Timer3A_IRQHandler(void);\r
-void WEAK Timer3B_IRQHandler(void);\r
-void WEAK I2C1_IRQHandler(void);\r
-void WEAK QEI1_IRQHandler(void);\r
-void WEAK CAN0_IRQHandler(void);\r
-void WEAK CAN1_IRQHandler(void);\r
-void WEAK CAN2_IRQHandler(void);\r
-void WEAK Ethernet_IRQHandler(void);\r
-void WEAK Hibernate_IRQHandler(void);\r
-\r
-//*****************************************************************************\r
-//\r
-// The entry point for the application.\r
-//\r
-//*****************************************************************************\r
-extern int main(void);\r
-\r
-//*****************************************************************************\r
-//\r
-// Reserve space for the system stack.\r
-//\r
-//*****************************************************************************\r
-static unsigned long pulStack[64];\r
-\r
-//*****************************************************************************\r
-//\r
-// The vector table. Note that the proper constructs must be placed on this to\r
-// ensure that it ends up at physical address 0x0000.0000.\r
-//\r
-//*****************************************************************************\r
-__attribute__ ((section(".isr_vector")))\r
-void (* const g_pfnVectors[])(void) =\r
-{\r
- (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)),\r
- // The initial stack pointer\r
- Reset_Handler, // The reset handler\r
- NMI_Handler, // The NMI handler\r
- HardFault_Handler, // The hard fault handler\r
- MemManage_Handler, // The MPU fault handler\r
- BusFault_Handler, // The bus fault handler\r
- UsageFault_Handler, // The usage fault handler\r
- 0xeffff74e, // Reserved\r
- 0, // Reserved\r
- 0, // Reserved\r
- 0, // Reserved\r
- SVC_Handler, // SVCall handler\r
- DebugMon_Handler, // Debug monitor handler\r
- 0, // Reserved\r
- PendSV_Handler, // The PendSV handler\r
- SysTick_Handler, // The SysTick handler\r
-\r
- //\r
- // External Interrupts\r
- //\r
- GPIOPortA_IRQHandler, // GPIO Port A\r
- GPIOPortB_IRQHandler, // GPIO Port B\r
- GPIOPortC_IRQHandler, // GPIO Port C\r
- GPIOPortD_IRQHandler, // GPIO Port D\r
- GPIOPortE_IRQHandler, // GPIO Port E\r
- UART0_IRQHandler, // UART0 Rx and Tx\r
- UART1_IRQHandler, // UART1 Rx and Tx\r
- SSI0_IRQHandler, // SSI0 Rx and Tx\r
- I2C0_IRQHandler, // I2C0 Master and Slave\r
- PWMFault_IRQHandler, // PWM Fault\r
- PWMGen0_IRQHandler, // PWM Generator 0\r
- PWMGen1_IRQHandler, // PWM Generator 1\r
- PWMGen2_IRQHandler, // PWM Generator 2\r
- QEI0_IRQHandler, // Quadrature Encoder 0\r
- ADCSeq0_IRQHandler, // ADC Sequence 0\r
- ADCSeq1_IRQHandler, // ADC Sequence 1\r
- ADCSeq2_IRQHandler, // ADC Sequence 2\r
- ADCSeq3_IRQHandler, // ADC Sequence 3\r
- Watchdog_IRQHandler, // Watchdog timer\r
- Timer0A_IRQHandler, // Timer 0 subtimer A\r
- Timer0B_IRQHandler, // Timer 0 subtimer B\r
- Timer1A_IRQHandler, // Timer 1 subtimer A\r
- Timer1B_IRQHandler, // Timer 1 subtimer B\r
- Timer2A_IRQHandler, // Timer 2 subtimer A\r
- Timer2B_IRQHandler, // Timer 2 subtimer B\r
- Comp0_IRQHandler, // Analog Comparator 0\r
- Comp1_IRQHandler, // Analog Comparator 1\r
- Comp2_IRQHandler, // Analog Comparator 2\r
- SysCtrl_IRQHandler, // System Control (PLL, OSC, BO)\r
- FlashCtrl_IRQHandler, // FLASH Control\r
- GPIOPortF_IRQHandler, // GPIO Port F\r
- GPIOPortG_IRQHandler, // GPIO Port G\r
- GPIOPortH_IRQHandler, // GPIO Port H\r
- UART2_IRQHandler, // UART2 Rx and Tx\r
- SSI1_IRQHandler, // SSI1 Rx and Tx\r
- Timer3A_IRQHandler, // Timer 3 subtimer A\r
- Timer3B_IRQHandler, // Timer 3 subtimer B\r
- I2C1_IRQHandler, // I2C1 Master and Slave\r
- QEI1_IRQHandler, // Quadrature Encoder 1\r
- CAN0_IRQHandler, // CAN0\r
- CAN1_IRQHandler, // CAN1\r
- CAN2_IRQHandler, // CAN2\r
- Ethernet_IRQHandler, // Ethernet\r
- Hibernate_IRQHandler // Hibernate\r
-};\r
-\r
-//*****************************************************************************\r
-//\r
-// The following are constructs created by the linker, indicating where the\r
-// the "data" and "bss" segments reside in memory. The initializers for the\r
-// for the "data" segment resides immediately following the "text" segment.\r
-//\r
-//*****************************************************************************\r
-extern unsigned long _etext;\r
-extern unsigned long _sdata;\r
-extern unsigned long _edata;\r
-extern unsigned long _sbss;\r
-extern unsigned long _ebss;\r
-\r
-//*****************************************************************************\r
-//\r
-// This is the code that gets called when the processor first starts execution\r
-// following a reset event. Only the absolutely necessary set is performed,\r
-// after which the application supplied entry() routine is called. Any fancy\r
-// actions (such as making decisions based on the reset cause register, and\r
-// resetting the bits in that register) are left solely in the hands of the\r
-// application.\r
-//\r
-//*****************************************************************************\r
-void\r
-Reset_Handler(void)\r
-{\r
- unsigned long *pulSrc, *pulDest;\r
-\r
- //\r
- // Copy the data segment initializers from flash to SRAM.\r
- //\r
- pulSrc = &_etext;\r
- for(pulDest = &_sdata; pulDest < &_edata; )\r
- {\r
- *pulDest++ = *pulSrc++;\r
- }\r
-\r
- //\r
- // Zero fill the bss segment. This is done with inline assembly since this\r
- // will clear the value of pulDest if it is not kept in a register.\r
- //\r
- __asm(" ldr r0, =_sbss\n"\r
- " ldr r1, =_ebss\n"\r
- " mov r2, #0\n"\r
- " .thumb_func\n"\r
- "zero_loop:\n"\r
- " cmp r0, r1\n"\r
- " it lt\n"\r
- " strlt r2, [r0], #4\n"\r
- " blt zero_loop");\r
-\r
- //\r
- // Call the application's entry point.\r
- //\r
- main();\r
-}\r
-\r
-//*****************************************************************************\r
-//\r
-// Provide weak aliases for each Exception handler to the Default_Handler.\r
-// As they are weak aliases, any function with the same name will override\r
-// this definition.\r
-//\r
-//*****************************************************************************\r
-#pragma weak NMI_Handler = Default_Handler\r
-#pragma weak HardFault_Handler = Default_Handler\r
-#pragma weak MemManage_Handler = Default_Handler\r
-#pragma weak BusFault_Handler = Default_Handler\r
-#pragma weak UsageFault_Handler = Default_Handler\r
-#pragma weak SVC_Handler = Default_Handler\r
-#pragma weak DebugMon_Handler = Default_Handler\r
-#pragma weak PendSV_Handler = Default_Handler\r
-#pragma weak SysTick_Handler = Default_Handler\r
-#pragma weak GPIOPortA_IRQHandler = Default_Handler\r
-#pragma weak GPIOPortB_IRQHandler = Default_Handler\r
-#pragma weak GPIOPortC_IRQHandler = Default_Handler\r
-#pragma weak GPIOPortD_IRQHandler = Default_Handler\r
-#pragma weak GPIOPortE_IRQHandler = Default_Handler\r
-#pragma weak UART0_IRQHandler = Default_Handler\r
-#pragma weak UART1_IRQHandler = Default_Handler\r
-#pragma weak SSI0_IRQHandler = Default_Handler\r
-#pragma weak I2C0_IRQHandler = Default_Handler\r
-#pragma weak PWMFault_IRQHandler = Default_Handler\r
-#pragma weak PWMGen0_IRQHandler = Default_Handler\r
-#pragma weak PWMGen1_IRQHandler = Default_Handler\r
-#pragma weak PWMGen2_IRQHandler = Default_Handler\r
-#pragma weak QEI0_IRQHandler = Default_Handler\r
-#pragma weak ADCSeq0_IRQHandler = Default_Handler\r
-#pragma weak ADCSeq1_IRQHandler = Default_Handler\r
-#pragma weak ADCSeq2_IRQHandler = Default_Handler\r
-#pragma weak ADCSeq3_IRQHandler = Default_Handler\r
-#pragma weak Watchdog_IRQHandler = Default_Handler\r
-#pragma weak Timer0A_IRQHandler = Default_Handler\r
-#pragma weak Timer0B_IRQHandler = Default_Handler\r
-#pragma weak Timer1A_IRQHandler = Default_Handler\r
-#pragma weak Timer1B_IRQHandler = Default_Handler\r
-#pragma weak Timer2A_IRQHandler = Default_Handler\r
-#pragma weak Timer2B_IRQHandler = Default_Handler\r
-#pragma weak Comp0_IRQHandler = Default_Handler\r
-#pragma weak Comp1_IRQHandler = Default_Handler\r
-#pragma weak Comp2_IRQHandler = Default_Handler\r
-#pragma weak SysCtrl_IRQHandler = Default_Handler\r
-#pragma weak FlashCtrl_IRQHandler = Default_Handler\r
-#pragma weak GPIOPortF_IRQHandler = Default_Handler\r
-#pragma weak GPIOPortG_IRQHandler = Default_Handler\r
-#pragma weak GPIOPortH_IRQHandler = Default_Handler\r
-#pragma weak UART2_IRQHandler = Default_Handler\r
-#pragma weak SSI1_IRQHandler = Default_Handler\r
-#pragma weak Timer3A_IRQHandler = Default_Handler\r
-#pragma weak Timer3B_IRQHandler = Default_Handler\r
-#pragma weak I2C1_IRQHandler = Default_Handler\r
-#pragma weak QEI1_IRQHandler = Default_Handler\r
-#pragma weak CAN0_IRQHandler = Default_Handler\r
-#pragma weak CAN1_IRQHandler = Default_Handler\r
-#pragma weak CAN2_IRQHandler = Default_Handler\r
-#pragma weak Ethernet_IRQHandler = Default_Handler\r
-#pragma weak Hibernate_IRQHandler = Default_Handler\r
-\r
-//*****************************************************************************\r
-//\r
-// This is the code that gets called when the processor receives an unexpected\r
-// interrupt. This simply enters an infinite loop, preserving the system state\r
-// for examination by a debugger.\r
-//\r
-//*****************************************************************************\r
-static void\r
-Default_Handler(void)\r
-{\r
- //\r
- // Go into an infinite loop.\r
- //\r
- while(1)\r
- {\r
- }\r
-}\r
+//*****************************************************************************
+//
+// startup_gcc.c - Startup code for use with GNU tools.
+//
+// Copyright (c) 2009 Luminary Micro, Inc. All rights reserved.
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program. Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 32 of the Stellaris CMSIS Package.
+//
+//*****************************************************************************
+
+#define WEAK __attribute__ ((weak))
+
+//*****************************************************************************
+//
+// Forward declaration of the default fault handlers.
+//
+//*****************************************************************************
+void WEAK Reset_Handler(void);
+static void Default_Handler(void);
+void WEAK NMI_Handler(void);
+void WEAK HardFault_Handler(void);
+void WEAK MemManage_Handler(void);
+void WEAK BusFault_Handler(void);
+void WEAK UsageFault_Handler(void);
+void WEAK MemManage_Handler(void);
+void WEAK SVC_Handler(void);
+void WEAK DebugMon_Handler(void);
+void WEAK PendSV_Handler(void);
+void WEAK SysTick_Handler(void);
+
+void WEAK WDT_IRQHandler(void);
+void WEAK TIMER0_IRQHandler(void);
+void WEAK TIMER1_IRQHandler(void);
+void WEAK TIMER2_IRQHandler(void);
+void WEAK TIMER3_IRQHandler(void);
+void WEAK UART0_IRQHandler(void);
+void WEAK UART1_IRQHandler(void);
+void WEAK UART2_IRQHandler(void);
+void WEAK UART3_IRQHandler(void);
+void WEAK PWM1_IRQHandler(void);
+void WEAK I2C0_IRQHandler(void);
+void WEAK I2C1_IRQHandler(void);
+void WEAK I2C2_IRQHandler(void);
+void WEAK SPI_IRQHandler(void);
+void WEAK SSP0_IRQHandler(void);
+void WEAK SSP1_IRQHandler(void);
+void WEAK PLL0_IRQHandler(void);
+void WEAK RTC_IRQHandler(void);
+void WEAK EINT0_IRQHandler(void);
+void WEAK EINT1_IRQHandler(void);
+void WEAK EINT2_IRQHandler(void);
+void WEAK EINT3_IRQHandler(void);
+void WEAK ADC_IRQHandler(void);
+void WEAK BOD_IRQHandler(void);
+void WEAK USB_IRQHandler(void);
+void WEAK CAN_IRQHandler(void);
+void WEAK DMA_IRQHandler(void);
+void WEAK I2S_IRQHandler(void);
+void WEAK ENET_IRQHandler(void);
+void WEAK RIT_IRQHandler(void);
+void WEAK MCPWM_IRQHandler(void);
+void WEAK QEI_IRQHandler(void);
+void WEAK PLL1_IRQHandler(void);
+void WEAK USBActivity_IRQHandler(void);
+void WEAK CANActivity_IRQHandler(void);
+
+//*****************************************************************************
+//
+// The entry point for the application.
+//
+//*****************************************************************************
+extern int main(void);
+
+//*****************************************************************************
+//
+// Reserve space for the system stack.
+//
+//*****************************************************************************
+static unsigned long pulStack[64];
+
+//*****************************************************************************
+//
+// The vector table. Note that the proper constructs must be placed on this to
+// ensure that it ends up at physical address 0x0000.0000.
+//
+//*****************************************************************************
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) =
+{
+ (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)),
+ // The initial stack pointer
+ Reset_Handler, // The reset handler
+ NMI_Handler, // The NMI handler
+ HardFault_Handler, // The hard fault handler
+ MemManage_Handler, // The MPU fault handler
+ BusFault_Handler, // The bus fault handler
+ UsageFault_Handler, // The usage fault handler
+ 0xeffffcbf, // Interrupt CRC
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ SVC_Handler, // SVCall handler
+ DebugMon_Handler, // Debug monitor handler
+ 0, // Reserved
+ PendSV_Handler, // The PendSV handler
+ SysTick_Handler, // The SysTick handler
+
+ //
+ // External Interrupts
+ //
+ WDT_IRQHandler, /* 16: Watchdog Timer */
+ TIMER0_IRQHandler, /* 17: Timer0 */
+ TIMER1_IRQHandler, /* 18: Timer1 */
+ TIMER2_IRQHandler, /* 19: Timer2 */
+ TIMER3_IRQHandler, /* 20: Timer3 */
+ UART0_IRQHandler, /* 21: UART0 */
+ UART1_IRQHandler, /* 22: UART1 */
+ UART2_IRQHandler, /* 23: UART2 */
+ UART3_IRQHandler, /* 24: UART3 */
+ PWM1_IRQHandler, /* 25: PWM1 */
+ I2C0_IRQHandler, /* 26: I2C0 */
+ I2C1_IRQHandler, /* 27: I2C1 */
+ I2C2_IRQHandler, /* 28: I2C2 */
+ SPI_IRQHandler, /* 29: SPI */
+ SSP0_IRQHandler, /* 30: SSP0 */
+ SSP1_IRQHandler, /* 31: SSP1 */
+ PLL0_IRQHandler, /* 32: PLL0 Lock (Main PLL) */
+ RTC_IRQHandler, /* 33: Real Time Clock */
+ EINT0_IRQHandler, /* 34: External Interrupt 0 */
+ EINT1_IRQHandler, /* 35: External Interrupt 1 */
+ EINT2_IRQHandler, /* 36: External Interrupt 2 */
+ EINT3_IRQHandler, /* 37: External Interrupt 3 */
+ ADC_IRQHandler, /* 38: A/D Converter */
+ BOD_IRQHandler, /* 39: Brown-Out Detect */
+ USB_IRQHandler, /* 40: USB */
+ CAN_IRQHandler, /* 41: CAN */
+ DMA_IRQHandler, /* 42: General Purpose DMA */
+ I2S_IRQHandler, /* 43: I2S */
+ ENET_IRQHandler, /* 44: Ethernet */
+ RIT_IRQHandler, /* 45: Repetitive Interrupt Timer */
+ MCPWM_IRQHandler, /* 46: Motor Control PWM */
+ QEI_IRQHandler, /* 47: Quadrature Encoder Interface */
+ PLL1_IRQHandler, /* 48: PLL1 Lock (USB PLL) */
+ USBActivity_IRQHandler, /* 49: USB Activity interrupt to wakeup */
+ CANActivity_IRQHandler /* 50: CAN Activity interrupt to wakeup */
+};
+
+//*****************************************************************************
+//
+// The following are constructs created by the linker, indicating where the
+// the "data" and "bss" segments reside in memory. The initializers for the
+// for the "data" segment resides immediately following the "text" segment.
+//
+//*****************************************************************************
+extern unsigned long _etext;
+extern unsigned long _sdata;
+extern unsigned long _edata;
+extern unsigned long _sbss;
+extern unsigned long _ebss;
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor first starts execution
+// following a reset event. Only the absolutely necessary set is performed,
+// after which the application supplied entry() routine is called. Any fancy
+// actions (such as making decisions based on the reset cause register, and
+// resetting the bits in that register) are left solely in the hands of the
+// application.
+//
+//*****************************************************************************
+void
+Reset_Handler(void)
+{
+ unsigned long *pulSrc, *pulDest;
+
+ //
+ // Copy the data segment initializers from flash to SRAM.
+ //
+ pulSrc = &_etext;
+ for(pulDest = &_sdata; pulDest < &_edata; )
+ {
+ *pulDest++ = *pulSrc++;
+ }
+
+ //
+ // Zero fill the bss segment. This is done with inline assembly since this
+ // will clear the value of pulDest if it is not kept in a register.
+ //
+ __asm(" ldr r0, =_sbss\n"
+ " ldr r1, =_ebss\n"
+ " mov r2, #0\n"
+ " .thumb_func\n"
+ "zero_loop:\n"
+ " cmp r0, r1\n"
+ " it lt\n"
+ " strlt r2, [r0], #4\n"
+ " blt zero_loop");
+
+ //
+ // Call the application's entry point.
+ //
+ main();
+}
+
+//*****************************************************************************
+//
+// Provide weak aliases for each Exception handler to the Default_Handler.
+// As they are weak aliases, any function with the same name will override
+// this definition.
+//
+//*****************************************************************************
+#pragma weak WDT_IRQHandler = Default_Handler
+#pragma weak TIMER0_IRQHandler = Default_Handler
+#pragma weak TIMER1_IRQHandler = Default_Handler
+#pragma weak TIMER2_IRQHandler = Default_Handler
+#pragma weak TIMER3_IRQHandler = Default_Handler
+#pragma weak UART0_IRQHandler = Default_Handler
+#pragma weak UART1_IRQHandler = Default_Handler
+#pragma weak UART2_IRQHandler = Default_Handler
+#pragma weak UART3_IRQHandler = Default_Handler
+#pragma weak PWM1_IRQHandler = Default_Handler
+#pragma weak I2C0_IRQHandler = Default_Handler
+#pragma weak I2C1_IRQHandler = Default_Handler
+#pragma weak I2C2_IRQHandler = Default_Handler
+#pragma weak SPI_IRQHandler = Default_Handler
+#pragma weak SSP0_IRQHandler = Default_Handler
+#pragma weak SSP1_IRQHandler = Default_Handler
+#pragma weak PLL0_IRQHandler = Default_Handler
+#pragma weak RTC_IRQHandler = Default_Handler
+#pragma weak EINT0_IRQHandler = Default_Handler
+#pragma weak EINT1_IRQHandler = Default_Handler
+#pragma weak EINT2_IRQHandler = Default_Handler
+#pragma weak EINT3_IRQHandler = Default_Handler
+#pragma weak ADC_IRQHandler = Default_Handler
+#pragma weak BOD_IRQHandler = Default_Handler
+#pragma weak USB_IRQHandler = Default_Handler
+#pragma weak CAN_IRQHandler = Default_Handler
+#pragma weak DMA_IRQHandler = Default_Handler
+#pragma weak I2S_IRQHandler = Default_Handler
+#pragma weak ENET_IRQHandler = Default_Handler
+#pragma weak RIT_IRQHandler = Default_Handler
+#pragma weak MCPWM_IRQHandler = Default_Handler
+#pragma weak QEI_IRQHandler = Default_Handler
+#pragma weak PPL1_IRQHandler = Default_Handler
+#pragma weak USBActivity_IRQHandler = Default_Handler
+#pragma weak CANActivity_IRQHandler = Default_Handler
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives an unexpected
+// interrupt. This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+static void
+Default_Handler(void)
+{
+ //
+ // Go into an infinite loop.
+ //
+ while(1)
+ {
+ }
+}
-/******************************************************************************\r
- * @file: system_LPC17xx.c\r
- * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Source File\r
- * for the NXP LPC17xx Device Series \r
- * @version: V1.1\r
- * @date: 18th May 2009\r
- *----------------------------------------------------------------------------\r
- *\r
- * Copyright (C) 2008 ARM Limited. All rights reserved.\r
- *\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M3 \r
- * processor based microcontrollers. This file can be freely distributed \r
- * within development tools that are supporting such ARM based processors. \r
- *\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-\r
-#include <stdint.h>\r
-#include "LPC17xx.h"\r
-\r
-/*\r
-//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
-*/\r
-\r
-/*--------------------- Clock Configuration ----------------------------------\r
-//\r
-// <e> Clock Configuration\r
-// <h> System Controls and Status Register (SCS)\r
-// <o1.4> OSCRANGE: Main Oscillator Range Select\r
-// <0=> 1 MHz to 20 MHz\r
-// <1=> 15 MHz to 24 MHz\r
-// <e1.5> OSCEN: Main Oscillator Enable\r
-// </e>\r
-// </h>\r
-//\r
-// <h> Clock Source Select Register (CLKSRCSEL)\r
-// <o2.0..1> CLKSRC: PLL Clock Source Selection\r
-// <0=> Internal RC oscillator\r
-// <1=> Main oscillator\r
-// <2=> RTC oscillator\r
-// </h>\r
-//\r
-// <e3> PLL0 Configuration (Main PLL)\r
-// <h> PLL0 Configuration Register (PLL0CFG)\r
-// <i> F_cco0 = (2 * M * F_in) / N\r
-// <i> F_in must be in the range of 32 kHz to 50 MHz\r
-// <i> F_cco0 must be in the range of 275 MHz to 550 MHz\r
-// <o4.0..14> MSEL: PLL Multiplier Selection\r
-// <6-32768><#-1>\r
-// <i> M Value\r
-// <o4.16..23> NSEL: PLL Divider Selection\r
-// <1-256><#-1>\r
-// <i> N Value\r
-// </h>\r
-// </e>\r
-//\r
-// <e5> PLL1 Configuration (USB PLL)\r
-// <h> PLL1 Configuration Register (PLL1CFG)\r
-// <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)\r
-// <i> F_cco1 = F_osc * M * 2 * P\r
-// <i> F_cco1 must be in the range of 156 MHz to 320 MHz\r
-// <o6.0..4> MSEL: PLL Multiplier Selection\r
-// <1-32><#-1>\r
-// <i> M Value (for USB maximum value is 4)\r
-// <o6.5..6> PSEL: PLL Divider Selection\r
-// <0=> 1\r
-// <1=> 2\r
-// <2=> 4\r
-// <3=> 8\r
-// <i> P Value\r
-// </h>\r
-// </e>\r
-//\r
-// <h> CPU Clock Configuration Register (CCLKCFG)\r
-// <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0\r
-// <2-256:2><#-1>\r
-// </h>\r
-//\r
-// <h> USB Clock Configuration Register (USBCLKCFG)\r
-// <o8.0..3> USBSEL: Divide Value for USB Clock from PLL1\r
-// <0-15>\r
-// <i> Divide is USBSEL + 1\r
-// </h>\r
-//\r
-// <h> Peripheral Clock Selection Register 0 (PCLKSEL0)\r
-// <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 6\r
-// <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 6\r
-// <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 6\r
-// </h>\r
-//\r
-// <h> Peripheral Clock Selection Register 1 (PCLKSEL1)\r
-// <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// </h>\r
-//\r
-// <h> Power Control for Peripherals Register (PCONP)\r
-// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable\r
-// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable\r
-// <o11.3> PCUART0: UART 0 power/clock enable\r
-// <o11.4> PCUART1: UART 1 power/clock enable\r
-// <o11.6> PCPWM1: PWM 1 power/clock enable\r
-// <o11.7> PCI2C0: I2C interface 0 power/clock enable\r
-// <o11.8> PCSPI: SPI interface power/clock enable\r
-// <o11.9> PCRTC: RTC power/clock enable\r
-// <o11.10> PCSSP1: SSP interface 1 power/clock enable\r
-// <o11.12> PCAD: A/D converter power/clock enable\r
-// <o11.13> PCCAN1: CAN controller 1 power/clock enable\r
-// <o11.14> PCCAN2: CAN controller 2 power/clock enable\r
-// <o11.15> PCGPIO: GPIOs power/clock enable\r
-// <o11.16> PCRIT: Repetitive interrupt timer power/clock enable\r
-// <o11.17> PCMC: Motor control PWM power/clock enable\r
-// <o11.18> PCQEI: Quadrature encoder interface power/clock enable\r
-// <o11.19> PCI2C1: I2C interface 1 power/clock enable\r
-// <o11.21> PCSSP0: SSP interface 0 power/clock enable\r
-// <o11.22> PCTIM2: Timer 2 power/clock enable\r
-// <o11.23> PCTIM3: Timer 3 power/clock enable\r
-// <o11.24> PCUART2: UART 2 power/clock enable\r
-// <o11.25> PCUART3: UART 3 power/clock enable\r
-// <o11.26> PCI2C2: I2C interface 2 power/clock enable\r
-// <o11.27> PCI2S: I2S interface power/clock enable\r
-// <o11.29> PCGPDMA: GP DMA function power/clock enable\r
-// <o11.30> PCENET: Ethernet block power/clock enable\r
-// <o11.31> PCUSB: USB interface power/clock enable\r
-// </h>\r
-//\r
-// <h> Clock Output Configuration Register (CLKOUTCFG)\r
-// <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT\r
-// <0=> CPU clock\r
-// <1=> Main oscillator\r
-// <2=> Internal RC oscillator\r
-// <3=> USB clock\r
-// <4=> RTC oscillator\r
-// <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT\r
-// <1-16><#-1>\r
-// <o12.8> CLKOUT_EN: CLKOUT enable control\r
-// </h>\r
-//\r
-// </e>\r
-*/\r
-#define CLOCK_SETUP 1\r
-#define SCS_Val 0x00000020\r
-#define CLKSRCSEL_Val 0x00000001\r
-#define PLL0_SETUP 1\r
-#define PLL0CFG_Val 0x0000000B\r
-#define PLL1_SETUP 0\r
-#define PLL1CFG_Val 0x00000000\r
-#define CCLKCFG_Val 0x00000003\r
-#define USBCLKCFG_Val 0x00000000\r
-#define PCLKSEL0_Val 0x00000000\r
-#define PCLKSEL1_Val 0x00000000\r
-#define PCONP_Val 0x042887DE\r
-#define CLKOUTCFG_Val 0x00000000\r
-\r
-\r
-/*--------------------- Flash Accelerator Configuration ----------------------\r
-//\r
-// <e> Flash Accelerator Configuration\r
-// <o1.0..1> FETCHCFG: Fetch Configuration\r
-// <0=> Instruction fetches from flash are not buffered\r
-// <1=> One buffer is used for all instruction fetch buffering\r
-// <2=> All buffers may be used for instruction fetch buffering\r
-// <3=> Reserved (do not use this setting)\r
-// <o1.2..3> DATACFG: Data Configuration\r
-// <0=> Data accesses from flash are not buffered\r
-// <1=> One buffer is used for all data access buffering\r
-// <2=> All buffers may be used for data access buffering\r
-// <3=> Reserved (do not use this setting)\r
-// <o1.4> ACCEL: Acceleration Enable\r
-// <o1.5> PREFEN: Prefetch Enable\r
-// <o1.6> PREFOVR: Prefetch Override\r
-// <o1.12..15> FLASHTIM: Flash Access Time\r
-// <0=> 1 CPU clock (for CPU clock up to 20 MHz)\r
-// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)\r
-// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)\r
-// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)\r
-// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)\r
-// <5=> 6 CPU clocks (for any CPU clock)\r
-// </e>\r
-*/\r
-#define FLASH_SETUP 1\r
-#define FLASHCFG_Val 0x0000303A\r
-\r
-/*\r
-//-------- <<< end of configuration section >>> ------------------------------\r
-*/\r
-\r
-/*----------------------------------------------------------------------------\r
- Check the register settings\r
- *----------------------------------------------------------------------------*/\r
-#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))\r
-#define CHECK_RSVD(val, mask) (val & mask)\r
-\r
-/* Clock Configuration -------------------------------------------------------*/\r
-#if (CHECK_RSVD((SCS_Val), ~0x00000030))\r
- #error "SCS: Invalid values of reserved bits!"\r
-#endif\r
-\r
-#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))\r
- #error "CLKSRCSEL: Value out of range!"\r
-#endif\r
-\r
-#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))\r
- #error "PLL0CFG: Invalid values of reserved bits!"\r
-#endif\r
-\r
-#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))\r
- #error "PLL1CFG: Invalid values of reserved bits!"\r
-#endif\r
-\r
-#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))\r
- #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"\r
-#endif\r
-\r
-#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))\r
- #error "USBCLKCFG: Invalid values of reserved bits!"\r
-#endif\r
-\r
-#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))\r
- #error "PCLKSEL0: Invalid values of reserved bits!"\r
-#endif\r
-\r
-#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))\r
- #error "PCLKSEL1: Invalid values of reserved bits!"\r
-#endif\r
-\r
-#if (CHECK_RSVD((PCONP_Val), 0x10100821))\r
- #error "PCONP: Invalid values of reserved bits!"\r
-#endif\r
-\r
-#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))\r
- #error "CLKOUTCFG: Invalid values of reserved bits!"\r
-#endif\r
-\r
-/* Flash Accelerator Configuration -------------------------------------------*/\r
-#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))\r
- #error "FLASHCFG: Invalid values of reserved bits!"\r
-#endif\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- DEFINES\r
- *----------------------------------------------------------------------------*/\r
- \r
-/*----------------------------------------------------------------------------\r
- Define clocks\r
- *----------------------------------------------------------------------------*/\r
-#define XTAL (12000000UL) /* Oscillator frequency */\r
-#define OSC_CLK ( XTAL) /* Main oscillator frequency */\r
-#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */\r
-#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- Clock Variable definitions\r
- *----------------------------------------------------------------------------*/\r
-uint32_t SystemFrequency = IRC_OSC; /*!< System Clock Frequency (Core Clock) */\r
-\r
-\r
-/**\r
- * Initialize the system\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * @brief Setup the microcontroller system.\r
- * Initialize the System and update the SystemFrequency variable.\r
- */\r
-void SystemInit (void)\r
-{\r
-#if (CLOCK_SETUP) /* Clock Setup */\r
- SC->SCS = SCS_Val;\r
- if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */\r
- while ((SC->SCS & (1 << 6)) == 0); /* Wait for Oscillator to be ready */\r
- }\r
-\r
- SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */\r
-\r
-#if (PLL0_SETUP)\r
- SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */\r
- SC->PLL0CFG = PLL0CFG_Val;\r
- SC->PLL0CON = 0x01; /* PLL0 Enable */\r
- SC->PLL0FEED = 0xAA;\r
- SC->PLL0FEED = 0x55;\r
- while (!(SC->PLL0STAT & (1 << 26))); /* Wait for PLOCK0 */\r
-\r
- SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */\r
- SC->PLL0FEED = 0xAA;\r
- SC->PLL0FEED = 0x55;\r
-#endif\r
-\r
-#if (PLL1_SETUP)\r
- SC->PLL1CFG = PLL1CFG_Val;\r
- SC->PLL1CON = 0x01; /* PLL1 Enable */\r
- SC->PLL1FEED = 0xAA;\r
- SC->PLL1FEED = 0x55;\r
- while (!(SC->PLL1STAT & (1 << 10))); /* Wait for PLOCK1 */\r
-\r
- SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */\r
- SC->PLL1FEED = 0xAA;\r
- SC->PLL1FEED = 0x55;\r
-#else\r
- SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */\r
-#endif\r
-\r
- SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */\r
- SC->PCLKSEL1 = PCLKSEL1_Val;\r
-\r
- SC->PCONP = PCONP_Val; /* Power Control for Peripherals */\r
-\r
- SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */\r
-#endif\r
-\r
- /* Determine clock frequency according to clock register values */\r
- if (((SC->PLL0STAT >> 24) & 3) == 3) {/* If PLL0 enabled and connected */\r
- switch (SC->CLKSRCSEL & 0x03) {\r
- case 0: /* Internal RC oscillator => PLL0 */\r
- case 3: /* Reserved, default to Internal RC */\r
- SystemFrequency = (IRC_OSC * \r
- (((2 * ((SC->PLL0STAT & 0x7FFF) + 1))) /\r
- (((SC->PLL0STAT >> 16) & 0xFF) + 1)) /\r
- ((SC->CCLKCFG & 0xFF)+ 1));\r
- break;\r
- case 1: /* Main oscillator => PLL0 */\r
- SystemFrequency = (OSC_CLK * \r
- (((2 * ((SC->PLL0STAT & 0x7FFF) + 1))) /\r
- (((SC->PLL0STAT >> 16) & 0xFF) + 1)) /\r
- ((SC->CCLKCFG & 0xFF)+ 1));\r
- break;\r
- case 2: /* RTC oscillator => PLL0 */\r
- SystemFrequency = (RTC_CLK * \r
- (((2 * ((SC->PLL0STAT & 0x7FFF) + 1))) /\r
- (((SC->PLL0STAT >> 16) & 0xFF) + 1)) /\r
- ((SC->CCLKCFG & 0xFF)+ 1));\r
- break;\r
- }\r
- } else {\r
- switch (SC->CLKSRCSEL & 0x03) {\r
- case 0: /* Internal RC oscillator => PLL0 */\r
- case 3: /* Reserved, default to Internal RC */\r
- SystemFrequency = IRC_OSC / ((SC->CCLKCFG & 0xFF)+ 1);\r
- break;\r
- case 1: /* Main oscillator => PLL0 */\r
- SystemFrequency = OSC_CLK / ((SC->CCLKCFG & 0xFF)+ 1);\r
- break;\r
- case 2: /* RTC oscillator => PLL0 */\r
- SystemFrequency = RTC_CLK / ((SC->CCLKCFG & 0xFF)+ 1);\r
- break;\r
- }\r
- }\r
-\r
-#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */\r
- SC->FLASHCFG = FLASHCFG_Val;\r
-#endif\r
-}\r
+/******************************************************************************
+ * @file: system_LPC17xx.c
+ * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Source File
+ * for the NXP LPC17xx Device Series
+ * @version: V1.1
+ * @date: 18th May 2009
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2008 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+#include <board.h>
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+// <h> System Controls and Status Register (SCS)
+// <o1.4> OSCRANGE: Main Oscillator Range Select
+// <0=> 1 MHz to 20 MHz
+// <1=> 15 MHz to 24 MHz
+// <e1.5> OSCEN: Main Oscillator Enable
+// </e>
+// </h>
+//
+// <h> Clock Source Select Register (CLKSRCSEL)
+// <o2.0..1> CLKSRC: PLL Clock Source Selection
+// <0=> Internal RC oscillator
+// <1=> Main oscillator
+// <2=> RTC oscillator
+// </h>
+//
+// <e3> PLL0 Configuration (Main PLL)
+// <h> PLL0 Configuration Register (PLL0CFG)
+// <i> F_cco0 = (2 * M * F_in) / N
+// <i> F_in must be in the range of 32 kHz to 50 MHz
+// <i> F_cco0 must be in the range of 275 MHz to 550 MHz
+// <o4.0..14> MSEL: PLL Multiplier Selection
+// <6-32768><#-1>
+// <i> M Value
+// <o4.16..23> NSEL: PLL Divider Selection
+// <1-256><#-1>
+// <i> N Value
+// </h>
+// </e>
+//
+// <e5> PLL1 Configuration (USB PLL)
+// <h> PLL1 Configuration Register (PLL1CFG)
+// <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
+// <i> F_cco1 = F_osc * M * 2 * P
+// <i> F_cco1 must be in the range of 156 MHz to 320 MHz
+// <o6.0..4> MSEL: PLL Multiplier Selection
+// <1-32><#-1>
+// <i> M Value (for USB maximum value is 4)
+// <o6.5..6> PSEL: PLL Divider Selection
+// <0=> 1
+// <1=> 2
+// <2=> 4
+// <3=> 8
+// <i> P Value
+// </h>
+// </e>
+//
+// <h> CPU Clock Configuration Register (CCLKCFG)
+// <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
+// <2-256:2><#-1>
+// </h>
+//
+// <h> USB Clock Configuration Register (USBCLKCFG)
+// <o8.0..3> USBSEL: Divide Value for USB Clock from PLL1
+// <0-15>
+// <i> Divide is USBSEL + 1
+// </h>
+//
+// <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
+// <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 6
+// <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 6
+// <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 6
+// </h>
+//
+// <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
+// <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// </h>
+//
+// <h> Power Control for Peripherals Register (PCONP)
+// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
+// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
+// <o11.3> PCUART0: UART 0 power/clock enable
+// <o11.4> PCUART1: UART 1 power/clock enable
+// <o11.6> PCPWM1: PWM 1 power/clock enable
+// <o11.7> PCI2C0: I2C interface 0 power/clock enable
+// <o11.8> PCSPI: SPI interface power/clock enable
+// <o11.9> PCRTC: RTC power/clock enable
+// <o11.10> PCSSP1: SSP interface 1 power/clock enable
+// <o11.12> PCAD: A/D converter power/clock enable
+// <o11.13> PCCAN1: CAN controller 1 power/clock enable
+// <o11.14> PCCAN2: CAN controller 2 power/clock enable
+// <o11.15> PCGPIO: GPIOs power/clock enable
+// <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
+// <o11.17> PCMC: Motor control PWM power/clock enable
+// <o11.18> PCQEI: Quadrature encoder interface power/clock enable
+// <o11.19> PCI2C1: I2C interface 1 power/clock enable
+// <o11.21> PCSSP0: SSP interface 0 power/clock enable
+// <o11.22> PCTIM2: Timer 2 power/clock enable
+// <o11.23> PCTIM3: Timer 3 power/clock enable
+// <o11.24> PCUART2: UART 2 power/clock enable
+// <o11.25> PCUART3: UART 3 power/clock enable
+// <o11.26> PCI2C2: I2C interface 2 power/clock enable
+// <o11.27> PCI2S: I2S interface power/clock enable
+// <o11.29> PCGPDMA: GP DMA function power/clock enable
+// <o11.30> PCENET: Ethernet block power/clock enable
+// <o11.31> PCUSB: USB interface power/clock enable
+// </h>
+//
+// 0x842887DE =
+// 1000 0100 0010 1000 1000 0111 1101 1110
+//
+// <h> Clock Output Configuration Register (CLKOUTCFG)
+// <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
+// <0=> CPU clock
+// <1=> Main oscillator
+// <2=> Internal RC oscillator
+// <3=> USB clock
+// <4=> RTC oscillator
+// <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
+// <1-16><#-1>
+// <o12.8> CLKOUT_EN: CLKOUT enable control
+// </h>
+//
+// </e>
+*/
+#define CLOCK_SETUP 1
+#define SCS_Val 0x00000020
+#define CLKSRCSEL_Val 0x00000001
+#define PLL0_SETUP 1
+#define PLL0CFG_Val 0x0000000B
+#define PLL1_SETUP 1
+#define PLL1CFG_Val 0x00000023
+#define CCLKCFG_Val 0x00000003
+#define USBCLKCFG_Val 0x00000000
+#define PCLKSEL0_Val 0x00000000
+#define PCLKSEL1_Val 0x00000000
+#define PCONP_Val 0x842887DE
+#define CLKOUTCFG_Val 0x00000000
+
+
+/*--------------------- Flash Accelerator Configuration ----------------------
+//
+// <e> Flash Accelerator Configuration
+// <o1.0..1> FETCHCFG: Fetch Configuration
+// <0=> Instruction fetches from flash are not buffered
+// <1=> One buffer is used for all instruction fetch buffering
+// <2=> All buffers may be used for instruction fetch buffering
+// <3=> Reserved (do not use this setting)
+// <o1.2..3> DATACFG: Data Configuration
+// <0=> Data accesses from flash are not buffered
+// <1=> One buffer is used for all data access buffering
+// <2=> All buffers may be used for data access buffering
+// <3=> Reserved (do not use this setting)
+// <o1.4> ACCEL: Acceleration Enable
+// <o1.5> PREFEN: Prefetch Enable
+// <o1.6> PREFOVR: Prefetch Override
+// <o1.12..15> FLASHTIM: Flash Access Time
+// <0=> 1 CPU clock (for CPU clock up to 20 MHz)
+// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
+// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
+// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
+// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
+// <5=> 6 CPU clocks (for any CPU clock)
+// </e>
+*/
+#define FLASH_SETUP 1
+#define FLASHCFG_Val 0x0000303A
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SCS_Val), ~0x00000030))
+ #error "SCS: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
+ #error "CLKSRCSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
+ #error "PLL0CFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
+ #error "PLL1CFG: Invalid values of reserved bits!"
+#endif
+
+#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
+ #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
+#endif
+
+#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
+ #error "USBCLKCFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
+ #error "PCLKSEL0: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
+ #error "PCLKSEL1: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCONP_Val), 0x10100821))
+ #error "PCONP: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
+ #error "CLKOUTCFG: Invalid values of reserved bits!"
+#endif
+
+/* Flash Accelerator Configuration -------------------------------------------*/
+#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
+ #error "FLASHCFG: Invalid values of reserved bits!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (12000000UL) /* Oscillator frequency */
+#define OSC_CLK ( XTAL) /* Main oscillator frequency */
+#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
+#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemFrequency = IRC_OSC; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemFrequency variable.
+ */
+void SystemInit (void)
+{
+#if (CLOCK_SETUP) /* Clock Setup */
+ SC->SCS = SCS_Val;
+ if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
+ while ((SC->SCS & (1 << 6)) == 0); /* Wait for Oscillator to be ready */
+ }
+
+ SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
+
+#if (PLL0_SETUP)
+ SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
+ SC->PLL0CFG = PLL0CFG_Val;
+ SC->PLL0CON = 0x01; /* PLL0 Enable */
+ SC->PLL0FEED = 0xAA;
+ SC->PLL0FEED = 0x55;
+ while (!(SC->PLL0STAT & (1 << 26))); /* Wait for PLOCK0 */
+
+ SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
+ SC->PLL0FEED = 0xAA;
+ SC->PLL0FEED = 0x55;
+#endif
+
+#if (PLL1_SETUP)
+ SC->PLL1CFG = PLL1CFG_Val;
+ SC->PLL1CON = 0x01; /* PLL1 Enable */
+ SC->PLL1FEED = 0xAA;
+ SC->PLL1FEED = 0x55;
+ while (!(SC->PLL1STAT & (1 << 10))); /* Wait for PLOCK1 */
+
+ SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
+ SC->PLL1FEED = 0xAA;
+ SC->PLL1FEED = 0x55;
+#else
+ SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
+#endif
+
+ SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
+ SC->PCLKSEL1 = PCLKSEL1_Val;
+
+ SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
+
+ SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
+#endif
+
+ /* Determine clock frequency according to clock register values */
+ if (((SC->PLL0STAT >> 24) & 3) == 3) {/* If PLL0 enabled and connected */
+ switch (SC->CLKSRCSEL & 0x03) {
+ case 0: /* Internal RC oscillator => PLL0 */
+ case 3: /* Reserved, default to Internal RC */
+ SystemFrequency = (IRC_OSC *
+ (((2 * ((SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((SC->PLL0STAT >> 16) & 0xFF) + 1)) /
+ ((SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ case 1: /* Main oscillator => PLL0 */
+ SystemFrequency = (OSC_CLK *
+ (((2 * ((SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((SC->PLL0STAT >> 16) & 0xFF) + 1)) /
+ ((SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ case 2: /* RTC oscillator => PLL0 */
+ SystemFrequency = (RTC_CLK *
+ (((2 * ((SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((SC->PLL0STAT >> 16) & 0xFF) + 1)) /
+ ((SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ }
+ } else {
+ switch (SC->CLKSRCSEL & 0x03) {
+ case 0: /* Internal RC oscillator => PLL0 */
+ case 3: /* Reserved, default to Internal RC */
+ SystemFrequency = IRC_OSC / ((SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ case 1: /* Main oscillator => PLL0 */
+ SystemFrequency = OSC_CLK / ((SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ case 2: /* RTC oscillator => PLL0 */
+ SystemFrequency = RTC_CLK / ((SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ }
+ }
+
+#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
+ SC->FLASHCFG = FLASHCFG_Val;
+#endif
+}
-/******************************************************************************\r
- * @file: system_LPC17xx.h\r
- * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File\r
- * for the NXP LPC17xx Device Series \r
- * @version: V1.0\r
- * @date: 25. Nov. 2008\r
- *----------------------------------------------------------------------------\r
- *\r
- * Copyright (C) 2008 ARM Limited. All rights reserved.\r
- *\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M3 \r
- * processor based microcontrollers. This file can be freely distributed \r
- * within development tools that are supporting such ARM based processors. \r
- *\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-\r
-#ifndef __SYSTEM_LPC17xx_H\r
-#define __SYSTEM_LPC17xx_H\r
-\r
-extern uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */\r
-\r
-\r
-/**\r
- * Initialize the system\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * @brief Setup the microcontroller system.\r
- * Initialize the System and update the SystemFrequency variable.\r
- */\r
-extern void SystemInit (void);\r
-#endif\r
+/******************************************************************************
+ * @file: system_LPC17xx.h
+ * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File
+ * for the NXP LPC17xx Device Series
+ * @version: V1.0
+ * @date: 25. Nov. 2008
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2008 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC17xx_H
+#define __SYSTEM_LPC17xx_H
+
+extern uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemFrequency variable.
+ */
+extern void SystemInit (void);
+#endif
--- /dev/null
+#ifndef LED_H
+#define LED_H
+
+#include <board.h>
+
+extern uint32_t msTicks; /* counts 1ms timeTicks */
+
+/*------------------------------------------------------------------------------
+ delays number of tick Systicks (happens every 1 ms)
+ *------------------------------------------------------------------------------*/
+__inline static void Delay (uint32_t dlyTicks) {
+ uint32_t curTicks;
+
+ curTicks = msTicks;
+ while ((msTicks - curTicks) < dlyTicks);
+}
+
+/*------------------------------------------------------------------------------
+ configer LED pins
+ *------------------------------------------------------------------------------*/
+__inline static void LED_Config(void) {
+
+ GPIO1->FIODIR = (1<<29)|(1<<18); /* LEDs on PORT1 18 & 29 are Output */
+}
+
+/*------------------------------------------------------------------------------
+ Switch on LEDs
+ *------------------------------------------------------------------------------*/
+__inline static void LED_On (uint32_t led) {
+
+ GPIO1->FIOPIN |= (led); /* Turn On LED */
+}
+
+
+/*------------------------------------------------------------------------------
+ Switch off LEDs
+ *------------------------------------------------------------------------------*/
+__inline static void LED_Off (uint32_t led) {
+
+ GPIO1->FIOPIN &= ~(led); /* Turn Off LED */
+}
+
+#endif
-/******************************************************************************\r
- * @file: main.c\r
- * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File\r
- * Blink a LED using CM3 SysTick\r
- * @version: V1.0\r
- * @date: 22. May 2009\r
- *----------------------------------------------------------------------------\r
- *\r
- * Copyright (C) 2008 ARM Limited. All rights reserved.\r
- *\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M3\r
- * processor based microcontrollers. This file can be freely distributed\r
- * within development tools that are supporting such ARM based processors.\r
- *\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-#include "LPC17xx.h"\r
-\r
-\r
-uint32_t msTicks; /* counts 1ms timeTicks */\r
-/*----------------------------------------------------------------------------\r
- SysTick_Handler\r
- *----------------------------------------------------------------------------*/\r
-void SysTick_Handler(void) {\r
- msTicks++; /* increment counter necessary in Delay() */\r
-}\r
-\r
-/*------------------------------------------------------------------------------\r
- delays number of tick Systicks (happens every 1 ms)\r
- *------------------------------------------------------------------------------*/\r
-__inline static void Delay (uint32_t dlyTicks) {\r
- uint32_t curTicks;\r
-\r
- curTicks = msTicks;\r
- while ((msTicks - curTicks) < dlyTicks);\r
-}\r
-\r
-/*------------------------------------------------------------------------------\r
- configer LED pins\r
- *------------------------------------------------------------------------------*/\r
-__inline static void LED_Config(void) {\r
-\r
- GPIO1->FIODIR = (1<<29)|(1<<18); /* LEDs on PORT1 18 & 29 are Output */\r
-}\r
-\r
-/*------------------------------------------------------------------------------\r
- Switch on LEDs\r
- *------------------------------------------------------------------------------*/\r
-__inline static void LED_On (uint32_t led) {\r
-\r
- GPIO1->FIOPIN |= (led); /* Turn On LED */\r
-}\r
-\r
-\r
-/*------------------------------------------------------------------------------\r
- Switch off LEDs\r
- *------------------------------------------------------------------------------*/\r
-__inline static void LED_Off (uint32_t led) {\r
-\r
- GPIO1->FIOPIN &= ~(led); /* Turn Off LED */\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
- MAIN function\r
- *----------------------------------------------------------------------------*/\r
-int main (void) {\r
-\r
- SystemInit(); /* setup clocks */\r
- if (SysTick_Config(SystemFrequency / 1000)) { /* Setup SysTick Timer for 1 msec interrupts */\r
- while (1); /* Capture error */\r
- }\r
-\r
- LED_Config();\r
-\r
- while(1) {\r
- LED_On ((1<<29)); /* Turn on the LED. */\r
- LED_On ((1<<18)); /* Turn on the LED. */\r
- Delay (100); /* delay 100 Msec */\r
- LED_Off ((1<<29)); /* Turn on the LED. */\r
- Delay (100); /* delay 100 Msec */\r
- LED_Off ((1<<18)); /* Turn on the LED. */\r
- LED_On ((1<<29)); /* Turn on the LED. */\r
- Delay (100); /* delay 100 Msec */\r
- }\r
-\r
-}\r
-\r
+/******************************************************************************
+ * @file: main.c
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File
+ * Blink a LED using CM3 SysTick
+ * @version: V1.0
+ * @date: 22. May 2009
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2008 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include <board.h>
+#include "usb.h"
+
+uint32_t msTicks; /* counts 1ms timeTicks */
+/*----------------------------------------------------------------------------
+ SysTick_Handler
+ *----------------------------------------------------------------------------*/
+void SysTick_Handler(void) {
+ msTicks++; /* increment counter necessary in Delay() */
+}
+
+/*------------------------------------------------------------------------------
+ delays number of tick Systicks (happens every 1 ms)
+ *------------------------------------------------------------------------------*/
+__inline static void Delay (uint32_t dlyTicks) {
+ uint32_t curTicks;
+
+ curTicks = msTicks;
+ while ((msTicks - curTicks) < dlyTicks);
+}
+
+/*------------------------------------------------------------------------------
+ configer LED pins
+ *------------------------------------------------------------------------------*/
+__inline static void LED_Config(void) {
+
+ GPIO1->FIODIR = (1<<29)|(1<<18); /* LEDs on PORT1 18 & 29 are Output */
+}
+
+/*------------------------------------------------------------------------------
+ Switch on LEDs
+ *------------------------------------------------------------------------------*/
+__inline static void LED_On (uint32_t led) {
+
+ GPIO1->FIOPIN |= (led); /* Turn On LED */
+}
+
+
+/*------------------------------------------------------------------------------
+ Switch off LEDs
+ *------------------------------------------------------------------------------*/
+__inline static void LED_Off (uint32_t led) {
+
+ GPIO1->FIOPIN &= ~(led); /* Turn Off LED */
+}
+
+void lightshow() {
+ while (1) {
+ LED_On ((1<<29)); /* Turn on the LED. */
+ LED_On ((1<<18)); /* Turn on the LED. */
+ Delay (100); /* delay 100 Msec */
+ LED_Off ((1<<29)); /* Turn on the LED. */
+ Delay (100); /* delay 100 Msec */
+ LED_Off ((1<<18)); /* Turn on the LED. */
+ LED_On ((1<<29)); /* Turn on the LED. */
+ Delay (100); /* delay 100 Msec */
+ }
+}
+
+/*----------------------------------------------------------------------------
+ MAIN function
+ *----------------------------------------------------------------------------*/
+int main (void) {
+
+ SystemInit(); /* setup clocks */
+
+ if (SysTick_Config(SystemFrequency / 1000)) { /* Setup SysTick Timer for 1 msec interrupts */
+ while (1); /* Capture error */
+ }
+
+ LED_Config();
+
+ VCOM_Init(); // VCOM Initialization
+
+ USB_Init(); // USB Initialization
+
+ USB_Connect(TRUE); // USB Connect
+ //lightshow();
+
+ while (!USB_Configuration) ; // wait until USB is configured
+
+ while (1) { // Loop forever
+ VCOM_Serial2Usb(); // read serial port and initiate USB event
+ VCOM_CheckSerialState();
+ VCOM_Usb2Serial();
+ } // end while
+}
+
--- /dev/null
+#include "usb/usb.h"
+#include "usb/cfg.h"
+#include "usb/hw.h"
+#include "usb/core.h"
+#include "usb/cdc.h"
+#include "usb/cdcuser.h"
+#include "usb/serial.h"
+#include "usb/vcom.h"
+
+++ /dev/null
-/*
- * This is the NXP LPC1768 linker file for code running from flash.
- *
- * TODO:
- * - handle the exotic input sections (e.g. glue and veneer, C++ sections)
- * - add additional Ethernet and USB RAM memory regions (2x16k)
- * - add boot ROM memory regions
- *
- * See also: http://bitbucket.org/jpc/lpc1768/
- *
- * Copyright (c) 2010 LoEE - Jakub Piotr Cłapa
- * This program is released under the new BSD license.
- */
-OUTPUT_FORMAT("elf32-littlearm")
-OUTPUT_ARCH(arm)
-
-ENTRY(Reset_Handler)
-
-MEMORY {
- flash (rx) : ORIGIN = 0x00000000, LENGTH = 512K
- ram (rwx) : ORIGIN = 0x10000000, LENGTH = 32K
-}
-
-SECTIONS {
- . = 0;
-
- .text : {
- _stext = .;
- KEEP(*(.isr_vector))
- *(.text*)
- *(.rodata*)
- . = ALIGN(4);
- _etext = .;
- } > flash
-
- .data : {
- _sdata = .;
- *(.data*)
- _edata = .;
- } > ram AT > flash
-
- .bss : {
- _sbss = .;
- *(.bss*)
- . = ALIGN(4);
- _ebss = .;
- } > ram
-
- _sstack = ORIGIN(ram) + LENGTH(ram);
-}
+++ /dev/null
-PROJECT=usbdemo\r
-PLATFORM ?= arm-none-eabi\r
-LDFLAGS=--gc-sections -g -T LPC1768-flash.ld\r
-CFLAGS=-W -Wall --std=gnu99 -fgnu89-inline -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -I. -g\r
-#CFLAGS+=-Os\r
-\r
-# objects are separated by space\r
-OBJECTS=serial.o usbcore.o usbdesc.o usbhw.o usbuser.o vcomdemo.o startup.o cdcuser.o ../system_LPC17xx.o\r
-\r
-\r
-all: $(PROJECT).elf\r
-\r
-$(PROJECT).elf: $(OBJECTS)\r
- $(PLATFORM)-ld -Map $(PROJECT).map $(LDFLAGS) $(OBJECTS) -o $@\r
-\r
-%.o: %.c\r
- $(PLATFORM)-gcc -MM $< -MF $(patsubst %.o,%.d,$@) -MP\r
- $(PLATFORM)-gcc $(CFLAGS) -c $< -o $@\r
-\r
-.PHONY: clean gdb\r
-\r
-clean:\r
- rm -f $(PROJECT).elf $(OBJECTS) $(OBJECTS:.o=.d) $(PROJECT).map\r
-\r
-gdb:\r
- $(PLATFORM)-gdb $(PROJECT).elf\r
-/*----------------------------------------------------------------------------\r
- * U S B - K e r n e l\r
- *----------------------------------------------------------------------------\r
- * Name: CDC.h\r
- * Purpose: USB Communication Device Class Definitions\r
- * Version: V1.20\r
- *----------------------------------------------------------------------------\r
- * This software is supplied "AS IS" without any warranties, express,\r
- * implied or statutory, including but not limited to the implied\r
- * warranties of fitness for purpose, satisfactory quality and\r
- * noninfringement. Keil extends you a royalty-free right to reproduce\r
- * and distribute executable files created using this software for use\r
- * on NXP Semiconductors LPC family microcontroller devices only. Nothing\r
- * else gives you the right to use this software.\r
- *\r
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
- *---------------------------------------------------------------------------*/\r
-\r
-#ifndef __CDC_H\r
-#define __CDC_H\r
-#include "lpc_types.h"\r
-\r
-#if defined ( __GNUC__ )\r
-#define __packed __attribute__((__packed__))\r
-#endif\r
-/*----------------------------------------------------------------------------\r
- * Definitions based on usbcdc11.pdf (www.usb.org)\r
- *---------------------------------------------------------------------------*/\r
-// Communication device class specification version 1.10\r
-#define CDC_V1_10 0x0110\r
-\r
-// Communication interface class code\r
-// (usbcdc11.pdf, 4.2, Table 15)\r
-#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02\r
-\r
-// Communication interface class subclass codes\r
-// (usbcdc11.pdf, 4.3, Table 16)\r
-#define CDC_DIRECT_LINE_CONTROL_MODEL 0x01\r
-#define CDC_ABSTRACT_CONTROL_MODEL 0x02\r
-#define CDC_TELEPHONE_CONTROL_MODEL 0x03\r
-#define CDC_MULTI_CHANNEL_CONTROL_MODEL 0x04\r
-#define CDC_CAPI_CONTROL_MODEL 0x05\r
-#define CDC_ETHERNET_NETWORKING_CONTROL_MODEL 0x06\r
-#define CDC_ATM_NETWORKING_CONTROL_MODEL 0x07\r
-\r
-// Communication interface class control protocol codes\r
-// (usbcdc11.pdf, 4.4, Table 17)\r
-#define CDC_PROTOCOL_COMMON_AT_COMMANDS 0x01\r
-\r
-// Data interface class code\r
-// (usbcdc11.pdf, 4.5, Table 18)\r
-#define CDC_DATA_INTERFACE_CLASS 0x0A\r
-\r
-// Data interface class protocol codes\r
-// (usbcdc11.pdf, 4.7, Table 19)\r
-#define CDC_PROTOCOL_ISDN_BRI 0x30\r
-#define CDC_PROTOCOL_HDLC 0x31\r
-#define CDC_PROTOCOL_TRANSPARENT 0x32\r
-#define CDC_PROTOCOL_Q921_MANAGEMENT 0x50\r
-#define CDC_PROTOCOL_Q921_DATA_LINK 0x51\r
-#define CDC_PROTOCOL_Q921_MULTIPLEXOR 0x52\r
-#define CDC_PROTOCOL_V42 0x90\r
-#define CDC_PROTOCOL_EURO_ISDN 0x91\r
-#define CDC_PROTOCOL_V24_RATE_ADAPTATION 0x92\r
-#define CDC_PROTOCOL_CAPI 0x93\r
-#define CDC_PROTOCOL_HOST_BASED_DRIVER 0xFD\r
-#define CDC_PROTOCOL_DESCRIBED_IN_PUFD 0xFE\r
-\r
-// Type values for bDescriptorType field of functional descriptors\r
-// (usbcdc11.pdf, 5.2.3, Table 24)\r
-#define CDC_CS_INTERFACE 0x24\r
-#define CDC_CS_ENDPOINT 0x25\r
-\r
-// Type values for bDescriptorSubtype field of functional descriptors\r
-// (usbcdc11.pdf, 5.2.3, Table 25)\r
-#define CDC_HEADER 0x00\r
-#define CDC_CALL_MANAGEMENT 0x01\r
-#define CDC_ABSTRACT_CONTROL_MANAGEMENT 0x02\r
-#define CDC_DIRECT_LINE_MANAGEMENT 0x03\r
-#define CDC_TELEPHONE_RINGER 0x04\r
-#define CDC_REPORTING_CAPABILITIES 0x05\r
-#define CDC_UNION 0x06\r
-#define CDC_COUNTRY_SELECTION 0x07\r
-#define CDC_TELEPHONE_OPERATIONAL_MODES 0x08\r
-#define CDC_USB_TERMINAL 0x09\r
-#define CDC_NETWORK_CHANNEL 0x0A\r
-#define CDC_PROTOCOL_UNIT 0x0B\r
-#define CDC_EXTENSION_UNIT 0x0C\r
-#define CDC_MULTI_CHANNEL_MANAGEMENT 0x0D\r
-#define CDC_CAPI_CONTROL_MANAGEMENT 0x0E\r
-#define CDC_ETHERNET_NETWORKING 0x0F\r
-#define CDC_ATM_NETWORKING 0x10\r
-\r
-// CDC class-specific request codes\r
-// (usbcdc11.pdf, 6.2, Table 46)\r
-// see Table 45 for info about the specific requests.\r
-#define CDC_SEND_ENCAPSULATED_COMMAND 0x00\r
-#define CDC_GET_ENCAPSULATED_RESPONSE 0x01\r
-#define CDC_SET_COMM_FEATURE 0x02\r
-#define CDC_GET_COMM_FEATURE 0x03\r
-#define CDC_CLEAR_COMM_FEATURE 0x04\r
-#define CDC_SET_AUX_LINE_STATE 0x10\r
-#define CDC_SET_HOOK_STATE 0x11\r
-#define CDC_PULSE_SETUP 0x12\r
-#define CDC_SEND_PULSE 0x13\r
-#define CDC_SET_PULSE_TIME 0x14\r
-#define CDC_RING_AUX_JACK 0x15\r
-#define CDC_SET_LINE_CODING 0x20\r
-#define CDC_GET_LINE_CODING 0x21\r
-#define CDC_SET_CONTROL_LINE_STATE 0x22\r
-#define CDC_SEND_BREAK 0x23\r
-#define CDC_SET_RINGER_PARMS 0x30\r
-#define CDC_GET_RINGER_PARMS 0x31\r
-#define CDC_SET_OPERATION_PARMS 0x32\r
-#define CDC_GET_OPERATION_PARMS 0x33\r
-#define CDC_SET_LINE_PARMS 0x34\r
-#define CDC_GET_LINE_PARMS 0x35\r
-#define CDC_DIAL_DIGITS 0x36\r
-#define CDC_SET_UNIT_PARAMETER 0x37\r
-#define CDC_GET_UNIT_PARAMETER 0x38\r
-#define CDC_CLEAR_UNIT_PARAMETER 0x39\r
-#define CDC_GET_PROFILE 0x3A\r
-#define CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40\r
-#define CDC_SET_ETHERNET_PMP_FILTER 0x41\r
-#define CDC_GET_ETHERNET_PMP_FILTER 0x42\r
-#define CDC_SET_ETHERNET_PACKET_FILTER 0x43\r
-#define CDC_GET_ETHERNET_STATISTIC 0x44\r
-#define CDC_SET_ATM_DATA_FORMAT 0x50\r
-#define CDC_GET_ATM_DEVICE_STATISTICS 0x51\r
-#define CDC_SET_ATM_DEFAULT_VC 0x52\r
-#define CDC_GET_ATM_VC_STATISTICS 0x53\r
-\r
-// Communication feature selector codes\r
-// (usbcdc11.pdf, 6.2.2..6.2.4, Table 47)\r
-#define CDC_ABSTRACT_STATE 0x01\r
-#define CDC_COUNTRY_SETTING 0x02\r
-\r
-// Feature Status returned for ABSTRACT_STATE Selector\r
-// (usbcdc11.pdf, 6.2.3, Table 48)\r
-#define CDC_IDLE_SETTING (1 << 0)\r
-#define CDC_DATA_MULTPLEXED_STATE (1 << 1)\r
-\r
-\r
-// Control signal bitmap values for the SetControlLineState request\r
-// (usbcdc11.pdf, 6.2.14, Table 51)\r
-#define CDC_DTE_PRESENT (1 << 0)\r
-#define CDC_ACTIVATE_CARRIER (1 << 1)\r
-\r
-// CDC class-specific notification codes\r
-// (usbcdc11.pdf, 6.3, Table 68)\r
-// see Table 67 for Info about class-specific notifications\r
-#define CDC_NOTIFICATION_NETWORK_CONNECTION 0x00\r
-#define CDC_RESPONSE_AVAILABLE 0x01\r
-#define CDC_AUX_JACK_HOOK_STATE 0x08\r
-#define CDC_RING_DETECT 0x09\r
-#define CDC_NOTIFICATION_SERIAL_STATE 0x20\r
-#define CDC_CALL_STATE_CHANGE 0x28\r
-#define CDC_LINE_STATE_CHANGE 0x29\r
-#define CDC_CONNECTION_SPEED_CHANGE 0x2A\r
-\r
-// UART state bitmap values (Serial state notification).\r
-// (usbcdc11.pdf, 6.3.5, Table 69)\r
-#define CDC_SERIAL_STATE_OVERRUN (1 << 6) // receive data overrun error has occurred\r
-#define CDC_SERIAL_STATE_PARITY (1 << 5) // parity error has occurred\r
-#define CDC_SERIAL_STATE_FRAMING (1 << 4) // framing error has occurred\r
-#define CDC_SERIAL_STATE_RING (1 << 3) // state of ring signal detection\r
-#define CDC_SERIAL_STATE_BREAK (1 << 2) // state of break detection\r
-#define CDC_SERIAL_STATE_TX_CARRIER (1 << 1) // state of transmission carrier\r
-#define CDC_SERIAL_STATE_RX_CARRIER (1 << 0) // state of receiver carrier\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- * Structures based on usbcdc11.pdf (www.usb.org)\r
- *---------------------------------------------------------------------------*/\r
-\r
-// Header functional descriptor\r
-// (usbcdc11.pdf, 5.2.3.1)\r
-// This header must precede any list of class-specific descriptors.\r
-\r
-#if defined ( __CC_ARM )\r
-typedef __packed struct _CDC_HEADER_DESCRIPTOR{\r
-#elif defined ( __GNUC__ )\r
-typedef struct __packed _CDC_HEADER_DESCRIPTOR{\r
-#elif defined ( __IAR_SYSTEMS_ICC__ )\r
-#pragma pack(1)\r
-typedef struct _CDC_HEADER_DESCRIPTOR {\r
-#endif\r
- uint8_t bFunctionLength; // size of this descriptor in bytes\r
- uint8_t bDescriptorType; // CS_INTERFACE descriptor type\r
- uint8_t bDescriptorSubtype; // Header functional descriptor subtype\r
- uint16_t bcdCDC; // USB CDC specification release version\r
-} CDC_HEADER_DESCRIPTOR;\r
-\r
-//Call management functional descriptor\r
-// (usbcdc11.pdf, 5.2.3.2)\r
-// Describes the processing of calls for the communication class interface.\r
-#if defined ( __CC_ARM )\r
-typedef __packed struct _CDC_CALL_MANAGEMENT_DESCRIPTOR{\r
-#elif defined ( __GNUC__ )\r
-typedef struct __packed _CDC_CALL_MANAGEMENT_DESCRIPTOR{\r
-#elif defined ( __IAR_SYSTEMS_ICC__ )\r
-#pragma pack(1)\r
-typedef struct _CDC_CALL_MANAGEMENT_DESCRIPTOR {\r
-#endif\r
- uint8_t bFunctionLength; // size of this descriptor in bytes\r
- uint8_t bDescriptorType; // CS_INTERFACE descriptor type\r
- uint8_t bDescriptorSubtype; // call management functional descriptor subtype\r
- uint8_t bmCapabilities; // capabilities that this configuration supports\r
- uint8_t bDataInterface; // interface number of the data class interface used for call management (optional)\r
-} CDC_CALL_MANAGEMENT_DESCRIPTOR;\r
-\r
-// Abstract control management functional descriptor\r
-// (usbcdc11.pdf, 5.2.3.3)\r
-// Describes the command supported by the communication interface class with the Abstract Control Model subclass code.\r
-#if defined ( __CC_ARM )\r
-typedef __packed struct _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR{\r
-#elif defined ( __GNUC__ )\r
-typedef struct __packed _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR{\r
-#elif defined ( __IAR_SYSTEMS_ICC__ )\r
-#pragma pack(1)\r
-typedef struct _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR {\r
-#endif\r
- uint8_t bFunctionLength; // size of this descriptor in bytes\r
- uint8_t bDescriptorType; // CS_INTERFACE descriptor type\r
- uint8_t bDescriptorSubtype; // abstract control management functional descriptor subtype\r
- uint8_t bmCapabilities; // capabilities supported by this configuration\r
-} CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR;\r
-\r
-// Union functional descriptors\r
-// (usbcdc11.pdf, 5.2.3.8)\r
-// Describes the relationship between a group of interfaces that can be considered to form a functional unit.\r
-#if defined ( __CC_ARM )\r
-typedef __packed struct _CDC_UNION_DESCRIPTOR{\r
-#elif defined ( __GNUC__ )\r
-typedef struct __packed _CDC_UNION_DESCRIPTOR{\r
-#elif defined ( __IAR_SYSTEMS_ICC__ )\r
-#pragma pack(1)\r
-typedef struct _CDC_UNION_DESCRIPTOR {\r
-#endif\r
- uint8_t bFunctionLength; // size of this descriptor in bytes\r
- uint8_t bDescriptorType; // CS_INTERFACE descriptor type\r
- uint8_t bDescriptorSubtype; // union functional descriptor subtype\r
- uint8_t bMasterInterface; // interface number designated as master\r
-} CDC_UNION_DESCRIPTOR;\r
-\r
-// Union functional descriptors with one slave interface\r
-// (usbcdc11.pdf, 5.2.3.8)\r
-#if defined ( __CC_ARM )\r
-typedef __packed struct _CDC_UNION_1SLAVE_DESCRIPTOR{\r
-#elif defined ( __GNUC__ )\r
-typedef struct __packed _CDC_UNION_1SLAVE_DESCRIPTOR{\r
-#elif defined ( __IAR_SYSTEMS_ICC__ )\r
-#pragma pack(1)\r
-typedef struct _CDC_UNION_1SLAVE_DESCRIPTOR {\r
-#endif\r
- CDC_UNION_DESCRIPTOR sUnion; // Union functional descriptor\r
- uint8_t bSlaveInterfaces[1]; // Slave interface 0\r
-} CDC_UNION_1SLAVE_DESCRIPTOR;\r
-\r
-// Line coding structure\r
-// Format of the data returned when a GetLineCoding request is received\r
-// (usbcdc11.pdf, 6.2.13)\r
-#if defined ( __CC_ARM )\r
-typedef __packed struct _CDC_LINE_CODING{\r
-#elif defined ( __GNUC__ )\r
-typedef struct __packed _CDC_LINE_CODING{\r
-#elif defined ( __IAR_SYSTEMS_ICC__ )\r
-#pragma pack(1)\r
-typedef struct _CDC_LINE_CODING {\r
-#endif\r
- uint32_t dwDTERate; // Data terminal rate in bits per second\r
- uint8_t bCharFormat; // Number of stop bits\r
- uint8_t bParityType; // Parity bit type\r
- uint8_t bDataBits; // Number of data bits\r
-} CDC_LINE_CODING;\r
-\r
-// Notification header\r
-// Data sent on the notification endpoint must follow this header.\r
-// see USB_SETUP_PACKET in file usb.h\r
-typedef USB_SETUP_PACKET CDC_NOTIFICATION_HEADER;\r
-\r
-#endif /* __CDC_H */\r
-\r
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: CDC.h
+ * Purpose: USB Communication Device Class Definitions
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC family microcontroller devices only. Nothing
+ * else gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#ifndef __CDC_H
+#define __CDC_H
+#include "lpc_types.h"
+
+#if defined ( __GNUC__ )
+#define __packed __attribute__((__packed__))
+#endif
+/*----------------------------------------------------------------------------
+ * Definitions based on usbcdc11.pdf (www.usb.org)
+ *---------------------------------------------------------------------------*/
+// Communication device class specification version 1.10
+#define CDC_V1_10 0x0110
+
+// Communication interface class code
+// (usbcdc11.pdf, 4.2, Table 15)
+#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02
+
+// Communication interface class subclass codes
+// (usbcdc11.pdf, 4.3, Table 16)
+#define CDC_DIRECT_LINE_CONTROL_MODEL 0x01
+#define CDC_ABSTRACT_CONTROL_MODEL 0x02
+#define CDC_TELEPHONE_CONTROL_MODEL 0x03
+#define CDC_MULTI_CHANNEL_CONTROL_MODEL 0x04
+#define CDC_CAPI_CONTROL_MODEL 0x05
+#define CDC_ETHERNET_NETWORKING_CONTROL_MODEL 0x06
+#define CDC_ATM_NETWORKING_CONTROL_MODEL 0x07
+
+// Communication interface class control protocol codes
+// (usbcdc11.pdf, 4.4, Table 17)
+#define CDC_PROTOCOL_COMMON_AT_COMMANDS 0x01
+
+// Data interface class code
+// (usbcdc11.pdf, 4.5, Table 18)
+#define CDC_DATA_INTERFACE_CLASS 0x0A
+
+// Data interface class protocol codes
+// (usbcdc11.pdf, 4.7, Table 19)
+#define CDC_PROTOCOL_ISDN_BRI 0x30
+#define CDC_PROTOCOL_HDLC 0x31
+#define CDC_PROTOCOL_TRANSPARENT 0x32
+#define CDC_PROTOCOL_Q921_MANAGEMENT 0x50
+#define CDC_PROTOCOL_Q921_DATA_LINK 0x51
+#define CDC_PROTOCOL_Q921_MULTIPLEXOR 0x52
+#define CDC_PROTOCOL_V42 0x90
+#define CDC_PROTOCOL_EURO_ISDN 0x91
+#define CDC_PROTOCOL_V24_RATE_ADAPTATION 0x92
+#define CDC_PROTOCOL_CAPI 0x93
+#define CDC_PROTOCOL_HOST_BASED_DRIVER 0xFD
+#define CDC_PROTOCOL_DESCRIBED_IN_PUFD 0xFE
+
+// Type values for bDescriptorType field of functional descriptors
+// (usbcdc11.pdf, 5.2.3, Table 24)
+#define CDC_CS_INTERFACE 0x24
+#define CDC_CS_ENDPOINT 0x25
+
+// Type values for bDescriptorSubtype field of functional descriptors
+// (usbcdc11.pdf, 5.2.3, Table 25)
+#define CDC_HEADER 0x00
+#define CDC_CALL_MANAGEMENT 0x01
+#define CDC_ABSTRACT_CONTROL_MANAGEMENT 0x02
+#define CDC_DIRECT_LINE_MANAGEMENT 0x03
+#define CDC_TELEPHONE_RINGER 0x04
+#define CDC_REPORTING_CAPABILITIES 0x05
+#define CDC_UNION 0x06
+#define CDC_COUNTRY_SELECTION 0x07
+#define CDC_TELEPHONE_OPERATIONAL_MODES 0x08
+#define CDC_USB_TERMINAL 0x09
+#define CDC_NETWORK_CHANNEL 0x0A
+#define CDC_PROTOCOL_UNIT 0x0B
+#define CDC_EXTENSION_UNIT 0x0C
+#define CDC_MULTI_CHANNEL_MANAGEMENT 0x0D
+#define CDC_CAPI_CONTROL_MANAGEMENT 0x0E
+#define CDC_ETHERNET_NETWORKING 0x0F
+#define CDC_ATM_NETWORKING 0x10
+
+// CDC class-specific request codes
+// (usbcdc11.pdf, 6.2, Table 46)
+// see Table 45 for info about the specific requests.
+#define CDC_SEND_ENCAPSULATED_COMMAND 0x00
+#define CDC_GET_ENCAPSULATED_RESPONSE 0x01
+#define CDC_SET_COMM_FEATURE 0x02
+#define CDC_GET_COMM_FEATURE 0x03
+#define CDC_CLEAR_COMM_FEATURE 0x04
+#define CDC_SET_AUX_LINE_STATE 0x10
+#define CDC_SET_HOOK_STATE 0x11
+#define CDC_PULSE_SETUP 0x12
+#define CDC_SEND_PULSE 0x13
+#define CDC_SET_PULSE_TIME 0x14
+#define CDC_RING_AUX_JACK 0x15
+#define CDC_SET_LINE_CODING 0x20
+#define CDC_GET_LINE_CODING 0x21
+#define CDC_SET_CONTROL_LINE_STATE 0x22
+#define CDC_SEND_BREAK 0x23
+#define CDC_SET_RINGER_PARMS 0x30
+#define CDC_GET_RINGER_PARMS 0x31
+#define CDC_SET_OPERATION_PARMS 0x32
+#define CDC_GET_OPERATION_PARMS 0x33
+#define CDC_SET_LINE_PARMS 0x34
+#define CDC_GET_LINE_PARMS 0x35
+#define CDC_DIAL_DIGITS 0x36
+#define CDC_SET_UNIT_PARAMETER 0x37
+#define CDC_GET_UNIT_PARAMETER 0x38
+#define CDC_CLEAR_UNIT_PARAMETER 0x39
+#define CDC_GET_PROFILE 0x3A
+#define CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40
+#define CDC_SET_ETHERNET_PMP_FILTER 0x41
+#define CDC_GET_ETHERNET_PMP_FILTER 0x42
+#define CDC_SET_ETHERNET_PACKET_FILTER 0x43
+#define CDC_GET_ETHERNET_STATISTIC 0x44
+#define CDC_SET_ATM_DATA_FORMAT 0x50
+#define CDC_GET_ATM_DEVICE_STATISTICS 0x51
+#define CDC_SET_ATM_DEFAULT_VC 0x52
+#define CDC_GET_ATM_VC_STATISTICS 0x53
+
+// Communication feature selector codes
+// (usbcdc11.pdf, 6.2.2..6.2.4, Table 47)
+#define CDC_ABSTRACT_STATE 0x01
+#define CDC_COUNTRY_SETTING 0x02
+
+// Feature Status returned for ABSTRACT_STATE Selector
+// (usbcdc11.pdf, 6.2.3, Table 48)
+#define CDC_IDLE_SETTING (1 << 0)
+#define CDC_DATA_MULTPLEXED_STATE (1 << 1)
+
+
+// Control signal bitmap values for the SetControlLineState request
+// (usbcdc11.pdf, 6.2.14, Table 51)
+#define CDC_DTE_PRESENT (1 << 0)
+#define CDC_ACTIVATE_CARRIER (1 << 1)
+
+// CDC class-specific notification codes
+// (usbcdc11.pdf, 6.3, Table 68)
+// see Table 67 for Info about class-specific notifications
+#define CDC_NOTIFICATION_NETWORK_CONNECTION 0x00
+#define CDC_RESPONSE_AVAILABLE 0x01
+#define CDC_AUX_JACK_HOOK_STATE 0x08
+#define CDC_RING_DETECT 0x09
+#define CDC_NOTIFICATION_SERIAL_STATE 0x20
+#define CDC_CALL_STATE_CHANGE 0x28
+#define CDC_LINE_STATE_CHANGE 0x29
+#define CDC_CONNECTION_SPEED_CHANGE 0x2A
+
+// UART state bitmap values (Serial state notification).
+// (usbcdc11.pdf, 6.3.5, Table 69)
+#define CDC_SERIAL_STATE_OVERRUN (1 << 6) // receive data overrun error has occurred
+#define CDC_SERIAL_STATE_PARITY (1 << 5) // parity error has occurred
+#define CDC_SERIAL_STATE_FRAMING (1 << 4) // framing error has occurred
+#define CDC_SERIAL_STATE_RING (1 << 3) // state of ring signal detection
+#define CDC_SERIAL_STATE_BREAK (1 << 2) // state of break detection
+#define CDC_SERIAL_STATE_TX_CARRIER (1 << 1) // state of transmission carrier
+#define CDC_SERIAL_STATE_RX_CARRIER (1 << 0) // state of receiver carrier
+
+
+/*----------------------------------------------------------------------------
+ * Structures based on usbcdc11.pdf (www.usb.org)
+ *---------------------------------------------------------------------------*/
+
+// Header functional descriptor
+// (usbcdc11.pdf, 5.2.3.1)
+// This header must precede any list of class-specific descriptors.
+
+#if defined ( __CC_ARM )
+typedef __packed struct _CDC_HEADER_DESCRIPTOR{
+#elif defined ( __GNUC__ )
+typedef struct __packed _CDC_HEADER_DESCRIPTOR{
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _CDC_HEADER_DESCRIPTOR {
+#endif
+ uint8_t bFunctionLength; // size of this descriptor in bytes
+ uint8_t bDescriptorType; // CS_INTERFACE descriptor type
+ uint8_t bDescriptorSubtype; // Header functional descriptor subtype
+ uint16_t bcdCDC; // USB CDC specification release version
+} CDC_HEADER_DESCRIPTOR;
+
+//Call management functional descriptor
+// (usbcdc11.pdf, 5.2.3.2)
+// Describes the processing of calls for the communication class interface.
+#if defined ( __CC_ARM )
+typedef __packed struct _CDC_CALL_MANAGEMENT_DESCRIPTOR{
+#elif defined ( __GNUC__ )
+typedef struct __packed _CDC_CALL_MANAGEMENT_DESCRIPTOR{
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _CDC_CALL_MANAGEMENT_DESCRIPTOR {
+#endif
+ uint8_t bFunctionLength; // size of this descriptor in bytes
+ uint8_t bDescriptorType; // CS_INTERFACE descriptor type
+ uint8_t bDescriptorSubtype; // call management functional descriptor subtype
+ uint8_t bmCapabilities; // capabilities that this configuration supports
+ uint8_t bDataInterface; // interface number of the data class interface used for call management (optional)
+} CDC_CALL_MANAGEMENT_DESCRIPTOR;
+
+// Abstract control management functional descriptor
+// (usbcdc11.pdf, 5.2.3.3)
+// Describes the command supported by the communication interface class with the Abstract Control Model subclass code.
+#if defined ( __CC_ARM )
+typedef __packed struct _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR{
+#elif defined ( __GNUC__ )
+typedef struct __packed _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR{
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR {
+#endif
+ uint8_t bFunctionLength; // size of this descriptor in bytes
+ uint8_t bDescriptorType; // CS_INTERFACE descriptor type
+ uint8_t bDescriptorSubtype; // abstract control management functional descriptor subtype
+ uint8_t bmCapabilities; // capabilities supported by this configuration
+} CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR;
+
+// Union functional descriptors
+// (usbcdc11.pdf, 5.2.3.8)
+// Describes the relationship between a group of interfaces that can be considered to form a functional unit.
+#if defined ( __CC_ARM )
+typedef __packed struct _CDC_UNION_DESCRIPTOR{
+#elif defined ( __GNUC__ )
+typedef struct __packed _CDC_UNION_DESCRIPTOR{
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _CDC_UNION_DESCRIPTOR {
+#endif
+ uint8_t bFunctionLength; // size of this descriptor in bytes
+ uint8_t bDescriptorType; // CS_INTERFACE descriptor type
+ uint8_t bDescriptorSubtype; // union functional descriptor subtype
+ uint8_t bMasterInterface; // interface number designated as master
+} CDC_UNION_DESCRIPTOR;
+
+// Union functional descriptors with one slave interface
+// (usbcdc11.pdf, 5.2.3.8)
+#if defined ( __CC_ARM )
+typedef __packed struct _CDC_UNION_1SLAVE_DESCRIPTOR{
+#elif defined ( __GNUC__ )
+typedef struct __packed _CDC_UNION_1SLAVE_DESCRIPTOR{
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _CDC_UNION_1SLAVE_DESCRIPTOR {
+#endif
+ CDC_UNION_DESCRIPTOR sUnion; // Union functional descriptor
+ uint8_t bSlaveInterfaces[1]; // Slave interface 0
+} CDC_UNION_1SLAVE_DESCRIPTOR;
+
+// Line coding structure
+// Format of the data returned when a GetLineCoding request is received
+// (usbcdc11.pdf, 6.2.13)
+#if defined ( __CC_ARM )
+typedef __packed struct _CDC_LINE_CODING{
+#elif defined ( __GNUC__ )
+typedef struct __packed _CDC_LINE_CODING{
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _CDC_LINE_CODING {
+#endif
+ uint32_t dwDTERate; // Data terminal rate in bits per second
+ uint8_t bCharFormat; // Number of stop bits
+ uint8_t bParityType; // Parity bit type
+ uint8_t bDataBits; // Number of data bits
+} CDC_LINE_CODING;
+
+// Notification header
+// Data sent on the notification endpoint must follow this header.
+// see USB_SETUP_PACKET in file usb.h
+typedef USB_SETUP_PACKET CDC_NOTIFICATION_HEADER;
+
+#endif /* __CDC_H */
+
-/*----------------------------------------------------------------------------\r
- * U S B - K e r n e l\r
- *----------------------------------------------------------------------------\r
- * Name: cdcuser.c\r
- * Purpose: USB Communication Device Class User module\r
- * Version: V1.10\r
- *----------------------------------------------------------------------------\r
-* This software is supplied "AS IS" without any warranties, express,\r
- * implied or statutory, including but not limited to the implied\r
- * warranties of fitness for purpose, satisfactory quality and\r
- * noninfringement. Keil extends you a royalty-free right to reproduce\r
- * and distribute executable files created using this software for use\r
- * on NXP Semiconductors LPC microcontroller devices only. Nothing else\r
- * gives you the right to use this software.\r
- *\r
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
- *---------------------------------------------------------------------------*/\r
-\r
-#include "lpc_types.h"\r
-\r
-#include "usb.h"\r
-#include "usbhw.h"\r
-#include "usbcfg.h"\r
-#include "usbcore.h"\r
-#include "cdc.h"\r
-#include "cdcuser.h"\r
-#include "serial.h"\r
-\r
-\r
-unsigned char BulkBufIn [USB_CDC_BUFSIZE]; // Buffer to store USB IN packet\r
-unsigned char BulkBufOut [USB_CDC_BUFSIZE]; // Buffer to store USB OUT packet\r
-unsigned char NotificationBuf [10];\r
-\r
-CDC_LINE_CODING CDC_LineCoding = {9600, 0, 0, 8};\r
-unsigned short CDC_SerialState = 0x0000;\r
-unsigned short CDC_DepInEmpty = 1; // Data IN EP is empty\r
-\r
-/*----------------------------------------------------------------------------\r
- We need a buffer for incomming data on USB port because USB receives\r
- much faster than UART transmits\r
- *---------------------------------------------------------------------------*/\r
-/* Buffer masks */\r
-#define CDC_BUF_SIZE (64) // Output buffer in bytes (power 2)\r
- // large enough for file transfer\r
-#define CDC_BUF_MASK (CDC_BUF_SIZE-1ul)\r
-\r
-/* Buffer read / write macros */\r
-#define CDC_BUF_RESET(cdcBuf) (cdcBuf.rdIdx = cdcBuf.wrIdx = 0)\r
-#define CDC_BUF_WR(cdcBuf, dataIn) (cdcBuf.data[CDC_BUF_MASK & cdcBuf.wrIdx++] = (dataIn))\r
-#define CDC_BUF_RD(cdcBuf) (cdcBuf.data[CDC_BUF_MASK & cdcBuf.rdIdx++])\r
-#define CDC_BUF_EMPTY(cdcBuf) (cdcBuf.rdIdx == cdcBuf.wrIdx)\r
-#define CDC_BUF_FULL(cdcBuf) (cdcBuf.rdIdx == cdcBuf.wrIdx+1)\r
-#define CDC_BUF_COUNT(cdcBuf) (CDC_BUF_MASK & (cdcBuf.wrIdx - cdcBuf.rdIdx))\r
-\r
-\r
-// CDC output buffer\r
-typedef struct __CDC_BUF_T {\r
- unsigned char data[CDC_BUF_SIZE];\r
- unsigned int wrIdx;\r
- unsigned int rdIdx;\r
-} CDC_BUF_T;\r
-\r
-CDC_BUF_T CDC_OutBuf; // buffer for all CDC Out data\r
-\r
-/*----------------------------------------------------------------------------\r
- read data from CDC_OutBuf\r
- *---------------------------------------------------------------------------*/\r
-int CDC_RdOutBuf (char *buffer, const int *length) {\r
- int bytesToRead, bytesRead;\r
-\r
- /* Read *length bytes, block if *bytes are not avaialable */\r
- bytesToRead = *length;\r
- bytesToRead = (bytesToRead < (*length)) ? bytesToRead : (*length);\r
- bytesRead = bytesToRead;\r
-\r
-\r
- // ... add code to check for underrun\r
-\r
- while (bytesToRead--) {\r
- *buffer++ = CDC_BUF_RD(CDC_OutBuf);\r
- }\r
- return (bytesRead);\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
- write data to CDC_OutBuf\r
- *---------------------------------------------------------------------------*/\r
-int CDC_WrOutBuf (const char *buffer, int *length) {\r
- int bytesToWrite, bytesWritten;\r
-\r
- // Write *length bytes\r
- bytesToWrite = *length;\r
- bytesWritten = bytesToWrite;\r
-\r
-\r
- // ... add code to check for overwrite\r
-\r
- while (bytesToWrite) {\r
- CDC_BUF_WR(CDC_OutBuf, *buffer++); // Copy Data to buffer\r
- bytesToWrite--;\r
- }\r
-\r
- return (bytesWritten);\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
- check if character(s) are available at CDC_OutBuf\r
- *---------------------------------------------------------------------------*/\r
-int CDC_OutBufAvailChar (int *availChar) {\r
-\r
- *availChar = CDC_BUF_COUNT(CDC_OutBuf);\r
-\r
- return (0);\r
-}\r
-/* end Buffer handling */\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC Initialisation\r
- Initializes the data structures and serial port\r
- Parameters: None\r
- Return Value: None\r
- *---------------------------------------------------------------------------*/\r
-void CDC_Init (char portNum ) {\r
-\r
- if ( portNum == 0 )\r
- {\r
- ser_OpenPort (0);\r
- ser_InitPort0 (CDC_LineCoding.dwDTERate,\r
- CDC_LineCoding.bDataBits,\r
- CDC_LineCoding.bParityType,\r
- CDC_LineCoding.bCharFormat);\r
- }\r
- else\r
- {\r
- ser_OpenPort (1);\r
- ser_InitPort1 (CDC_LineCoding.dwDTERate,\r
- CDC_LineCoding.bDataBits,\r
- CDC_LineCoding.bParityType,\r
- CDC_LineCoding.bCharFormat);\r
- }\r
- CDC_DepInEmpty = 1;\r
- CDC_SerialState = CDC_GetSerialState();\r
-\r
- CDC_BUF_RESET(CDC_OutBuf);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC SendEncapsulatedCommand Request Callback\r
- Called automatically on CDC SEND_ENCAPSULATED_COMMAND Request\r
- Parameters: None (global SetupPacket and EP0Buf)\r
- Return Value: TRUE - Success, FALSE - Error\r
- *---------------------------------------------------------------------------*/\r
-uint32_t CDC_SendEncapsulatedCommand (void) {\r
-\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC GetEncapsulatedResponse Request Callback\r
- Called automatically on CDC Get_ENCAPSULATED_RESPONSE Request\r
- Parameters: None (global SetupPacket and EP0Buf)\r
- Return Value: TRUE - Success, FALSE - Error\r
- *---------------------------------------------------------------------------*/\r
-uint32_t CDC_GetEncapsulatedResponse (void) {\r
-\r
- /* ... add code to handle request */\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC SetCommFeature Request Callback\r
- Called automatically on CDC Set_COMM_FATURE Request\r
- Parameters: FeatureSelector\r
- Return Value: TRUE - Success, FALSE - Error\r
- *---------------------------------------------------------------------------*/\r
-uint32_t CDC_SetCommFeature (unsigned short wFeatureSelector) {\r
-\r
- /* ... add code to handle request */\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC GetCommFeature Request Callback\r
- Called automatically on CDC Get_COMM_FATURE Request\r
- Parameters: FeatureSelector\r
- Return Value: TRUE - Success, FALSE - Error\r
- *---------------------------------------------------------------------------*/\r
-uint32_t CDC_GetCommFeature (unsigned short wFeatureSelector) {\r
-\r
- /* ... add code to handle request */\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC ClearCommFeature Request Callback\r
- Called automatically on CDC CLEAR_COMM_FATURE Request\r
- Parameters: FeatureSelector\r
- Return Value: TRUE - Success, FALSE - Error\r
- *---------------------------------------------------------------------------*/\r
-uint32_t CDC_ClearCommFeature (unsigned short wFeatureSelector) {\r
-\r
- /* ... add code to handle request */\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC SetLineCoding Request Callback\r
- Called automatically on CDC SET_LINE_CODING Request\r
- Parameters: none (global SetupPacket and EP0Buf)\r
- Return Value: TRUE - Success, FALSE - Error\r
- *---------------------------------------------------------------------------*/\r
-uint32_t CDC_SetLineCoding (void) {\r
-\r
- CDC_LineCoding.dwDTERate = (EP0Buf[0] << 0)\r
- | (EP0Buf[1] << 8)\r
- | (EP0Buf[2] << 16)\r
- | (EP0Buf[3] << 24);\r
- CDC_LineCoding.bCharFormat = EP0Buf[4];\r
- CDC_LineCoding.bParityType = EP0Buf[5];\r
- CDC_LineCoding.bDataBits = EP0Buf[6];\r
-\r
-#if PORT_NUM\r
- ser_ClosePort(1);\r
- ser_OpenPort (1);\r
- ser_InitPort1 (CDC_LineCoding.dwDTERate,\r
- CDC_LineCoding.bDataBits,\r
- CDC_LineCoding.bParityType,\r
- CDC_LineCoding.bCharFormat);\r
-#else\r
- ser_ClosePort(0);\r
- ser_OpenPort (0);\r
- ser_InitPort0 (CDC_LineCoding.dwDTERate,\r
- CDC_LineCoding.bDataBits,\r
- CDC_LineCoding.bParityType,\r
- CDC_LineCoding.bCharFormat);\r
-#endif\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC GetLineCoding Request Callback\r
- Called automatically on CDC GET_LINE_CODING Request\r
- Parameters: None (global SetupPacket and EP0Buf)\r
- Return Value: TRUE - Success, FALSE - Error\r
- *---------------------------------------------------------------------------*/\r
-uint32_t CDC_GetLineCoding (void) {\r
-\r
- EP0Buf[0] = (CDC_LineCoding.dwDTERate >> 0) & 0xFF;\r
- EP0Buf[1] = (CDC_LineCoding.dwDTERate >> 8) & 0xFF;\r
- EP0Buf[2] = (CDC_LineCoding.dwDTERate >> 16) & 0xFF;\r
- EP0Buf[3] = (CDC_LineCoding.dwDTERate >> 24) & 0xFF;\r
- EP0Buf[4] = CDC_LineCoding.bCharFormat;\r
- EP0Buf[5] = CDC_LineCoding.bParityType;\r
- EP0Buf[6] = CDC_LineCoding.bDataBits;\r
-\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC SetControlLineState Request Callback\r
- Called automatically on CDC SET_CONTROL_LINE_STATE Request\r
- Parameters: ControlSignalBitmap\r
- Return Value: TRUE - Success, FALSE - Error\r
- *---------------------------------------------------------------------------*/\r
-uint32_t CDC_SetControlLineState (unsigned short wControlSignalBitmap) {\r
-\r
- /* ... add code to handle request */\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC SendBreak Request Callback\r
- Called automatically on CDC Set_COMM_FATURE Request\r
- Parameters: 0xFFFF start of Break\r
- 0x0000 stop of Break\r
- 0x#### Duration of Break\r
- Return Value: TRUE - Success, FALSE - Error\r
- *---------------------------------------------------------------------------*/\r
-uint32_t CDC_SendBreak (unsigned short wDurationOfBreak) {\r
-\r
- /* ... add code to handle request */\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC_BulkIn call on DataIn Request\r
- Parameters: none\r
- Return Value: none\r
- *---------------------------------------------------------------------------*/\r
-void CDC_BulkIn(void) {\r
- int numBytesRead, numBytesAvail;\r
-\r
- ser_AvailChar (&numBytesAvail);\r
-\r
- // ... add code to check for overwrite\r
-\r
- numBytesRead = ser_Read ((char *)&BulkBufIn[0], &numBytesAvail);\r
-\r
- // send over USB\r
- if (numBytesRead > 0) {\r
- USB_WriteEP (CDC_DEP_IN, &BulkBufIn[0], numBytesRead);\r
- }\r
- else {\r
- CDC_DepInEmpty = 1;\r
- }\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC_BulkOut call on DataOut Request\r
- Parameters: none\r
- Return Value: none\r
- *---------------------------------------------------------------------------*/\r
-void CDC_BulkOut(void) {\r
- int numBytesRead;\r
-\r
- // get data from USB into intermediate buffer\r
- numBytesRead = USB_ReadEP(CDC_DEP_OUT, &BulkBufOut[0]);\r
-\r
- // ... add code to check for overwrite\r
-\r
- // store data in a buffer to transmit it over serial interface\r
- CDC_WrOutBuf ((char *)&BulkBufOut[0], &numBytesRead);\r
-\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- Get the SERIAL_STATE as defined in usbcdc11.pdf, 6.3.5, Table 69.\r
- Parameters: none\r
- Return Value: SerialState as defined in usbcdc11.pdf\r
- *---------------------------------------------------------------------------*/\r
-unsigned short CDC_GetSerialState (void) {\r
- unsigned short temp;\r
-\r
- CDC_SerialState = 0;\r
- ser_LineState (&temp);\r
-\r
- if (temp & 0x8000) CDC_SerialState |= CDC_SERIAL_STATE_RX_CARRIER;\r
- if (temp & 0x2000) CDC_SerialState |= CDC_SERIAL_STATE_TX_CARRIER;\r
- if (temp & 0x0010) CDC_SerialState |= CDC_SERIAL_STATE_BREAK;\r
- if (temp & 0x4000) CDC_SerialState |= CDC_SERIAL_STATE_RING;\r
- if (temp & 0x0008) CDC_SerialState |= CDC_SERIAL_STATE_FRAMING;\r
- if (temp & 0x0004) CDC_SerialState |= CDC_SERIAL_STATE_PARITY;\r
- if (temp & 0x0002) CDC_SerialState |= CDC_SERIAL_STATE_OVERRUN;\r
-\r
- return (CDC_SerialState);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- Send the SERIAL_STATE notification as defined in usbcdc11.pdf, 6.3.5.\r
- *---------------------------------------------------------------------------*/\r
-void CDC_NotificationIn (void) {\r
-\r
- NotificationBuf[0] = 0xA1; // bmRequestType\r
- NotificationBuf[1] = CDC_NOTIFICATION_SERIAL_STATE; // bNotification (SERIAL_STATE)\r
- NotificationBuf[2] = 0x00; // wValue\r
- NotificationBuf[3] = 0x00;\r
- NotificationBuf[4] = 0x00; // wIndex (Interface #, LSB first)\r
- NotificationBuf[5] = 0x00;\r
- NotificationBuf[6] = 0x02; // wLength (Data length = 2 bytes, LSB first)\r
- NotificationBuf[7] = 0x00;\r
- NotificationBuf[8] = (CDC_SerialState >> 0) & 0xFF; // UART State Bitmap (16bits, LSB first)\r
- NotificationBuf[9] = (CDC_SerialState >> 8) & 0xFF;\r
-\r
- USB_WriteEP (CDC_CEP_IN, &NotificationBuf[0], 10); // send notification\r
-}\r
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: cdcuser.c
+ * Purpose: USB Communication Device Class User module
+ * Version: V1.10
+ *----------------------------------------------------------------------------
+* This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC microcontroller devices only. Nothing else
+ * gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#include "lpc_types.h"
+
+#include "usb.h"
+#include "hw.h"
+#include "cfg.h"
+#include "core.h"
+#include "cdc.h"
+#include "cdcuser.h"
+#include "serial.h"
+
+
+unsigned char BulkBufIn [USB_CDC_BUFSIZE]; // Buffer to store USB IN packet
+unsigned char BulkBufOut [USB_CDC_BUFSIZE]; // Buffer to store USB OUT packet
+unsigned char NotificationBuf [10];
+
+CDC_LINE_CODING CDC_LineCoding = {9600, 0, 0, 8};
+unsigned short CDC_SerialState = 0x0000;
+unsigned short CDC_DepInEmpty = 1; // Data IN EP is empty
+
+/*----------------------------------------------------------------------------
+ We need a buffer for incomming data on USB port because USB receives
+ much faster than UART transmits
+ *---------------------------------------------------------------------------*/
+/* Buffer masks */
+#define CDC_BUF_SIZE (64) // Output buffer in bytes (power 2)
+ // large enough for file transfer
+#define CDC_BUF_MASK (CDC_BUF_SIZE-1ul)
+
+/* Buffer read / write macros */
+#define CDC_BUF_RESET(cdcBuf) (cdcBuf.rdIdx = cdcBuf.wrIdx = 0)
+#define CDC_BUF_WR(cdcBuf, dataIn) (cdcBuf.data[CDC_BUF_MASK & cdcBuf.wrIdx++] = (dataIn))
+#define CDC_BUF_RD(cdcBuf) (cdcBuf.data[CDC_BUF_MASK & cdcBuf.rdIdx++])
+#define CDC_BUF_EMPTY(cdcBuf) (cdcBuf.rdIdx == cdcBuf.wrIdx)
+#define CDC_BUF_FULL(cdcBuf) (cdcBuf.rdIdx == cdcBuf.wrIdx+1)
+#define CDC_BUF_COUNT(cdcBuf) (CDC_BUF_MASK & (cdcBuf.wrIdx - cdcBuf.rdIdx))
+
+
+// CDC output buffer
+typedef struct __CDC_BUF_T {
+ unsigned char data[CDC_BUF_SIZE];
+ unsigned int wrIdx;
+ unsigned int rdIdx;
+} CDC_BUF_T;
+
+CDC_BUF_T CDC_OutBuf; // buffer for all CDC Out data
+
+/*----------------------------------------------------------------------------
+ read data from CDC_OutBuf
+ *---------------------------------------------------------------------------*/
+int CDC_RdOutBuf (char *buffer, const int *length) {
+ int bytesToRead, bytesRead;
+
+ /* Read *length bytes, block if *bytes are not avaialable */
+ bytesToRead = *length;
+ bytesToRead = (bytesToRead < (*length)) ? bytesToRead : (*length);
+ bytesRead = bytesToRead;
+
+
+ // ... add code to check for underrun
+
+ while (bytesToRead--) {
+ *buffer++ = CDC_BUF_RD(CDC_OutBuf);
+ }
+ return (bytesRead);
+}
+
+/*----------------------------------------------------------------------------
+ write data to CDC_OutBuf
+ *---------------------------------------------------------------------------*/
+int CDC_WrOutBuf (const char *buffer, int *length) {
+ int bytesToWrite, bytesWritten;
+
+ // Write *length bytes
+ bytesToWrite = *length;
+ bytesWritten = bytesToWrite;
+
+
+ // ... add code to check for overwrite
+
+ while (bytesToWrite) {
+ CDC_BUF_WR(CDC_OutBuf, *buffer++); // Copy Data to buffer
+ bytesToWrite--;
+ }
+
+ return (bytesWritten);
+}
+
+/*----------------------------------------------------------------------------
+ check if character(s) are available at CDC_OutBuf
+ *---------------------------------------------------------------------------*/
+int CDC_OutBufAvailChar (int *availChar) {
+
+ *availChar = CDC_BUF_COUNT(CDC_OutBuf);
+
+ return (0);
+}
+/* end Buffer handling */
+
+
+/*----------------------------------------------------------------------------
+ CDC Initialisation
+ Initializes the data structures and serial port
+ Parameters: None
+ Return Value: None
+ *---------------------------------------------------------------------------*/
+void CDC_Init (char portNum ) {
+
+ if ( portNum == 0 )
+ {
+ ser_OpenPort (0);
+ ser_InitPort0 (CDC_LineCoding.dwDTERate,
+ CDC_LineCoding.bDataBits,
+ CDC_LineCoding.bParityType,
+ CDC_LineCoding.bCharFormat);
+ }
+ else
+ {
+ ser_OpenPort (1);
+ ser_InitPort1 (CDC_LineCoding.dwDTERate,
+ CDC_LineCoding.bDataBits,
+ CDC_LineCoding.bParityType,
+ CDC_LineCoding.bCharFormat);
+ }
+ CDC_DepInEmpty = 1;
+ CDC_SerialState = CDC_GetSerialState();
+
+ CDC_BUF_RESET(CDC_OutBuf);
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC SendEncapsulatedCommand Request Callback
+ Called automatically on CDC SEND_ENCAPSULATED_COMMAND Request
+ Parameters: None (global SetupPacket and EP0Buf)
+ Return Value: TRUE - Success, FALSE - Error
+ *---------------------------------------------------------------------------*/
+uint32_t CDC_SendEncapsulatedCommand (void) {
+
+ return (TRUE);
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC GetEncapsulatedResponse Request Callback
+ Called automatically on CDC Get_ENCAPSULATED_RESPONSE Request
+ Parameters: None (global SetupPacket and EP0Buf)
+ Return Value: TRUE - Success, FALSE - Error
+ *---------------------------------------------------------------------------*/
+uint32_t CDC_GetEncapsulatedResponse (void) {
+
+ /* ... add code to handle request */
+ return (TRUE);
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC SetCommFeature Request Callback
+ Called automatically on CDC Set_COMM_FATURE Request
+ Parameters: FeatureSelector
+ Return Value: TRUE - Success, FALSE - Error
+ *---------------------------------------------------------------------------*/
+uint32_t CDC_SetCommFeature (unsigned short wFeatureSelector) {
+
+ /* ... add code to handle request */
+ return (TRUE);
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC GetCommFeature Request Callback
+ Called automatically on CDC Get_COMM_FATURE Request
+ Parameters: FeatureSelector
+ Return Value: TRUE - Success, FALSE - Error
+ *---------------------------------------------------------------------------*/
+uint32_t CDC_GetCommFeature (unsigned short wFeatureSelector) {
+
+ /* ... add code to handle request */
+ return (TRUE);
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC ClearCommFeature Request Callback
+ Called automatically on CDC CLEAR_COMM_FATURE Request
+ Parameters: FeatureSelector
+ Return Value: TRUE - Success, FALSE - Error
+ *---------------------------------------------------------------------------*/
+uint32_t CDC_ClearCommFeature (unsigned short wFeatureSelector) {
+
+ /* ... add code to handle request */
+ return (TRUE);
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC SetLineCoding Request Callback
+ Called automatically on CDC SET_LINE_CODING Request
+ Parameters: none (global SetupPacket and EP0Buf)
+ Return Value: TRUE - Success, FALSE - Error
+ *---------------------------------------------------------------------------*/
+uint32_t CDC_SetLineCoding (void) {
+
+ CDC_LineCoding.dwDTERate = (EP0Buf[0] << 0)
+ | (EP0Buf[1] << 8)
+ | (EP0Buf[2] << 16)
+ | (EP0Buf[3] << 24);
+ CDC_LineCoding.bCharFormat = EP0Buf[4];
+ CDC_LineCoding.bParityType = EP0Buf[5];
+ CDC_LineCoding.bDataBits = EP0Buf[6];
+
+#if PORT_NUM
+ ser_ClosePort(1);
+ ser_OpenPort (1);
+ ser_InitPort1 (CDC_LineCoding.dwDTERate,
+ CDC_LineCoding.bDataBits,
+ CDC_LineCoding.bParityType,
+ CDC_LineCoding.bCharFormat);
+#else
+ ser_ClosePort(0);
+ ser_OpenPort (0);
+ ser_InitPort0 (CDC_LineCoding.dwDTERate,
+ CDC_LineCoding.bDataBits,
+ CDC_LineCoding.bParityType,
+ CDC_LineCoding.bCharFormat);
+#endif
+ return (TRUE);
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC GetLineCoding Request Callback
+ Called automatically on CDC GET_LINE_CODING Request
+ Parameters: None (global SetupPacket and EP0Buf)
+ Return Value: TRUE - Success, FALSE - Error
+ *---------------------------------------------------------------------------*/
+uint32_t CDC_GetLineCoding (void) {
+
+ EP0Buf[0] = (CDC_LineCoding.dwDTERate >> 0) & 0xFF;
+ EP0Buf[1] = (CDC_LineCoding.dwDTERate >> 8) & 0xFF;
+ EP0Buf[2] = (CDC_LineCoding.dwDTERate >> 16) & 0xFF;
+ EP0Buf[3] = (CDC_LineCoding.dwDTERate >> 24) & 0xFF;
+ EP0Buf[4] = CDC_LineCoding.bCharFormat;
+ EP0Buf[5] = CDC_LineCoding.bParityType;
+ EP0Buf[6] = CDC_LineCoding.bDataBits;
+
+ return (TRUE);
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC SetControlLineState Request Callback
+ Called automatically on CDC SET_CONTROL_LINE_STATE Request
+ Parameters: ControlSignalBitmap
+ Return Value: TRUE - Success, FALSE - Error
+ *---------------------------------------------------------------------------*/
+uint32_t CDC_SetControlLineState (unsigned short wControlSignalBitmap) {
+
+ /* ... add code to handle request */
+ return (TRUE);
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC SendBreak Request Callback
+ Called automatically on CDC Set_COMM_FATURE Request
+ Parameters: 0xFFFF start of Break
+ 0x0000 stop of Break
+ 0x#### Duration of Break
+ Return Value: TRUE - Success, FALSE - Error
+ *---------------------------------------------------------------------------*/
+uint32_t CDC_SendBreak (unsigned short wDurationOfBreak) {
+
+ /* ... add code to handle request */
+ return (TRUE);
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC_BulkIn call on DataIn Request
+ Parameters: none
+ Return Value: none
+ *---------------------------------------------------------------------------*/
+void CDC_BulkIn(void) {
+ int numBytesRead, numBytesAvail;
+
+ ser_AvailChar (&numBytesAvail);
+
+ // ... add code to check for overwrite
+
+ numBytesRead = ser_Read ((char *)&BulkBufIn[0], &numBytesAvail);
+
+ // send over USB
+ if (numBytesRead > 0) {
+ USB_WriteEP (CDC_DEP_IN, &BulkBufIn[0], numBytesRead);
+ }
+ else {
+ CDC_DepInEmpty = 1;
+ }
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC_BulkOut call on DataOut Request
+ Parameters: none
+ Return Value: none
+ *---------------------------------------------------------------------------*/
+void CDC_BulkOut(void) {
+ int numBytesRead;
+
+ // get data from USB into intermediate buffer
+ numBytesRead = USB_ReadEP(CDC_DEP_OUT, &BulkBufOut[0]);
+
+ // ... add code to check for overwrite
+
+ // store data in a buffer to transmit it over serial interface
+ CDC_WrOutBuf ((char *)&BulkBufOut[0], &numBytesRead);
+
+}
+
+
+/*----------------------------------------------------------------------------
+ Get the SERIAL_STATE as defined in usbcdc11.pdf, 6.3.5, Table 69.
+ Parameters: none
+ Return Value: SerialState as defined in usbcdc11.pdf
+ *---------------------------------------------------------------------------*/
+unsigned short CDC_GetSerialState (void) {
+ unsigned short temp;
+
+ CDC_SerialState = 0;
+ ser_LineState (&temp);
+
+ if (temp & 0x8000) CDC_SerialState |= CDC_SERIAL_STATE_RX_CARRIER;
+ if (temp & 0x2000) CDC_SerialState |= CDC_SERIAL_STATE_TX_CARRIER;
+ if (temp & 0x0010) CDC_SerialState |= CDC_SERIAL_STATE_BREAK;
+ if (temp & 0x4000) CDC_SerialState |= CDC_SERIAL_STATE_RING;
+ if (temp & 0x0008) CDC_SerialState |= CDC_SERIAL_STATE_FRAMING;
+ if (temp & 0x0004) CDC_SerialState |= CDC_SERIAL_STATE_PARITY;
+ if (temp & 0x0002) CDC_SerialState |= CDC_SERIAL_STATE_OVERRUN;
+
+ return (CDC_SerialState);
+}
+
+
+/*----------------------------------------------------------------------------
+ Send the SERIAL_STATE notification as defined in usbcdc11.pdf, 6.3.5.
+ *---------------------------------------------------------------------------*/
+void CDC_NotificationIn (void) {
+
+ NotificationBuf[0] = 0xA1; // bmRequestType
+ NotificationBuf[1] = CDC_NOTIFICATION_SERIAL_STATE; // bNotification (SERIAL_STATE)
+ NotificationBuf[2] = 0x00; // wValue
+ NotificationBuf[3] = 0x00;
+ NotificationBuf[4] = 0x00; // wIndex (Interface #, LSB first)
+ NotificationBuf[5] = 0x00;
+ NotificationBuf[6] = 0x02; // wLength (Data length = 2 bytes, LSB first)
+ NotificationBuf[7] = 0x00;
+ NotificationBuf[8] = (CDC_SerialState >> 0) & 0xFF; // UART State Bitmap (16bits, LSB first)
+ NotificationBuf[9] = (CDC_SerialState >> 8) & 0xFF;
+
+ USB_WriteEP (CDC_CEP_IN, &NotificationBuf[0], 10); // send notification
+}
-/*----------------------------------------------------------------------------\r
- * U S B - K e r n e l\r
- *----------------------------------------------------------------------------\r
- * Name: cdcuser.h\r
- * Purpose: USB Communication Device Class User module Definitions\r
- * Version: V1.10\r
- *----------------------------------------------------------------------------\r
- * This software is supplied "AS IS" without any warranties, express,\r
- * implied or statutory, including but not limited to the implied\r
- * warranties of fitness for purpose, satisfactory quality and\r
- * noninfringement. Keil extends you a royalty-free right to reproduce\r
- * and distribute executable files created using this software for use\r
- * on NXP Semiconductors LPC microcontroller devices only. Nothing else \r
- * gives you the right to use this software.\r
- *\r
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
- *---------------------------------------------------------------------------*/\r
-\r
-#ifndef __CDCUSER_H__\r
-#define __CDCUSER_H__\r
-\r
-/* CDC buffer handling */\r
-extern int CDC_RdOutBuf (char *buffer, const int *length);\r
-extern CDC_WrOutBuf (const char *buffer, int *length);\r
-extern CDC_OutBufAvailChar (int *availChar);\r
-\r
-\r
-/* CDC Data In/Out Endpoint Address */\r
-#define CDC_DEP_IN 0x82\r
-#define CDC_DEP_OUT 0x02\r
-\r
-/* CDC Communication In Endpoint Address */\r
-#define CDC_CEP_IN 0x81\r
-\r
-/* CDC Requests Callback Functions */\r
-extern uint32_t CDC_SendEncapsulatedCommand (void);\r
-extern uint32_t CDC_GetEncapsulatedResponse (void);\r
-extern uint32_t CDC_SetCommFeature (unsigned short wFeatureSelector);\r
-extern uint32_t CDC_GetCommFeature (unsigned short wFeatureSelector);\r
-extern uint32_t CDC_ClearCommFeature (unsigned short wFeatureSelector);\r
-extern uint32_t CDC_GetLineCoding (void);\r
-extern uint32_t CDC_SetLineCoding (void);\r
-extern uint32_t CDC_SetControlLineState (unsigned short wControlSignalBitmap);\r
-extern uint32_t CDC_SendBreak (unsigned short wDurationOfBreak);\r
-\r
-/* CDC Bulk Callback Functions */\r
-extern void CDC_BulkIn (void);\r
-extern void CDC_BulkOut (void);\r
-\r
-/* CDC Notification Callback Function */\r
-extern void CDC_NotificationIn (void);\r
-\r
-/* CDC Initializtion Function */\r
-extern void CDC_Init (char portNum);\r
-\r
-/* CDC prepare the SERAIAL_STATE */\r
-extern unsigned short CDC_GetSerialState (void);\r
-\r
-/* flow control */\r
-extern unsigned short CDC_DepInEmpty; // DataEndPoint IN empty\r
-\r
-#endif /* __CDCUSER_H__ */\r
-\r
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: cdcuser.h
+ * Purpose: USB Communication Device Class User module Definitions
+ * Version: V1.10
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC microcontroller devices only. Nothing else
+ * gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#ifndef __CDCUSER_H__
+#define __CDCUSER_H__
+
+/* CDC buffer handling */
+extern int CDC_RdOutBuf (char *buffer, const int *length);
+extern CDC_WrOutBuf (const char *buffer, int *length);
+extern CDC_OutBufAvailChar (int *availChar);
+
+
+/* CDC Data In/Out Endpoint Address */
+#define CDC_DEP_IN 0x82
+#define CDC_DEP_OUT 0x02
+
+/* CDC Communication In Endpoint Address */
+#define CDC_CEP_IN 0x81
+
+/* CDC Requests Callback Functions */
+extern uint32_t CDC_SendEncapsulatedCommand (void);
+extern uint32_t CDC_GetEncapsulatedResponse (void);
+extern uint32_t CDC_SetCommFeature (unsigned short wFeatureSelector);
+extern uint32_t CDC_GetCommFeature (unsigned short wFeatureSelector);
+extern uint32_t CDC_ClearCommFeature (unsigned short wFeatureSelector);
+extern uint32_t CDC_GetLineCoding (void);
+extern uint32_t CDC_SetLineCoding (void);
+extern uint32_t CDC_SetControlLineState (unsigned short wControlSignalBitmap);
+extern uint32_t CDC_SendBreak (unsigned short wDurationOfBreak);
+
+/* CDC Bulk Callback Functions */
+extern void CDC_BulkIn (void);
+extern void CDC_BulkOut (void);
+
+/* CDC Notification Callback Function */
+extern void CDC_NotificationIn (void);
+
+/* CDC Initializtion Function */
+extern void CDC_Init (char portNum);
+
+/* CDC prepare the SERAIAL_STATE */
+extern unsigned short CDC_GetSerialState (void);
+
+/* flow control */
+extern unsigned short CDC_DepInEmpty; // DataEndPoint IN empty
+
+#endif /* __CDCUSER_H__ */
+
-/*----------------------------------------------------------------------------\r
- * U S B - K e r n e l\r
- *----------------------------------------------------------------------------\r
- * Name: usbcfg.h\r
- * Purpose: USB Custom Configuration\r
- * Version: V1.20\r
- *----------------------------------------------------------------------------\r
- * This software is supplied "AS IS" without any warranties, express,\r
- * implied or statutory, including but not limited to the implied\r
- * warranties of fitness for purpose, satisfactory quality and\r
- * noninfringement. Keil extends you a royalty-free right to reproduce\r
- * and distribute executable files created using this software for use\r
- * on NXP Semiconductors LPC family microcontroller devices only. Nothing \r
- * else gives you the right to use this software.\r
- *\r
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
- *----------------------------------------------------------------------------\r
- * History:\r
- * V1.20 Added vendor specific support\r
- * V1.00 Initial Version\r
- *---------------------------------------------------------------------------*/\r
-\r
-#ifndef __USBCFG_H__\r
-#define __USBCFG_H__\r
-\r
-\r
-//*** <<< Use Configuration Wizard in Context Menu >>> ***\r
-\r
-\r
-/*\r
-// <h> USB Configuration\r
-// <o0> USB Power\r
-// <i> Default Power Setting\r
-// <0=> Bus-powered\r
-// <1=> Self-powered\r
-// <o1> Max Number of Interfaces <1-256>\r
-// <o2> Max Number of Endpoints <1-32>\r
-// <o3> Max Endpoint 0 Packet Size\r
-// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes\r
-// <e4> DMA Transfer\r
-// <i> Use DMA for selected Endpoints\r
-// <o5.0> Endpoint 0 Out\r
-// <o5.1> Endpoint 0 In\r
-// <o5.2> Endpoint 1 Out\r
-// <o5.3> Endpoint 1 In\r
-// <o5.4> Endpoint 2 Out\r
-// <o5.5> Endpoint 2 In\r
-// <o5.6> Endpoint 3 Out\r
-// <o5.7> Endpoint 3 In\r
-// <o5.8> Endpoint 4 Out\r
-// <o5.9> Endpoint 4 In\r
-// <o5.10> Endpoint 5 Out\r
-// <o5.11> Endpoint 5 In\r
-// <o5.12> Endpoint 6 Out\r
-// <o5.13> Endpoint 6 In\r
-// <o5.14> Endpoint 7 Out\r
-// <o5.15> Endpoint 7 In\r
-// <o5.16> Endpoint 8 Out\r
-// <o5.17> Endpoint 8 In\r
-// <o5.18> Endpoint 9 Out\r
-// <o5.19> Endpoint 9 In\r
-// <o5.20> Endpoint 10 Out\r
-// <o5.21> Endpoint 10 In\r
-// <o5.22> Endpoint 11 Out\r
-// <o5.23> Endpoint 11 In\r
-// <o5.24> Endpoint 12 Out\r
-// <o5.25> Endpoint 12 In\r
-// <o5.26> Endpoint 13 Out\r
-// <o5.27> Endpoint 13 In\r
-// <o5.28> Endpoint 14 Out\r
-// <o5.29> Endpoint 14 In\r
-// <o5.30> Endpoint 15 Out\r
-// <o5.31> Endpoint 15 In\r
-// </e>\r
-// </h>\r
-*/\r
-\r
-#define USB_POWER 0\r
-#define USB_IF_NUM 4\r
-#define USB_EP_NUM 32\r
-#define USB_MAX_PACKET0 8\r
-#define USB_DMA 0\r
-#define USB_DMA_EP 0x00000000\r
-\r
-\r
-/*\r
-// <h> USB Event Handlers\r
-// <h> Device Events\r
-// <o0.0> Power Event\r
-// <o1.0> Reset Event\r
-// <o2.0> Suspend Event\r
-// <o3.0> Resume Event\r
-// <o4.0> Remote Wakeup Event\r
-// <o5.0> Start of Frame Event\r
-// <o6.0> Error Event\r
-// </h>\r
-// <h> Endpoint Events\r
-// <o7.0> Endpoint 0 Event\r
-// <o7.1> Endpoint 1 Event\r
-// <o7.2> Endpoint 2 Event\r
-// <o7.3> Endpoint 3 Event\r
-// <o7.4> Endpoint 4 Event\r
-// <o7.5> Endpoint 5 Event\r
-// <o7.6> Endpoint 6 Event\r
-// <o7.7> Endpoint 7 Event\r
-// <o7.8> Endpoint 8 Event\r
-// <o7.9> Endpoint 9 Event\r
-// <o7.10> Endpoint 10 Event\r
-// <o7.11> Endpoint 11 Event\r
-// <o7.12> Endpoint 12 Event\r
-// <o7.13> Endpoint 13 Event\r
-// <o7.14> Endpoint 14 Event\r
-// <o7.15> Endpoint 15 Event\r
-// </h>\r
-// <h> USB Core Events\r
-// <o8.0> Set Configuration Event\r
-// <o9.0> Set Interface Event\r
-// <o10.0> Set/Clear Feature Event\r
-// </h>\r
-// </h>\r
-*/\r
-\r
-#define USB_POWER_EVENT 0\r
-#define USB_RESET_EVENT 1\r
-#define USB_SUSPEND_EVENT 0\r
-#define USB_RESUME_EVENT 0\r
-#define USB_WAKEUP_EVENT 0\r
-#define USB_SOF_EVENT 0\r
-#define USB_ERROR_EVENT 0\r
-#define USB_EP_EVENT 0x0007\r
-#define USB_CONFIGURE_EVENT 1\r
-#define USB_INTERFACE_EVENT 0\r
-#define USB_FEATURE_EVENT 0\r
-\r
-\r
-/*\r
-// <e0> USB Class Support\r
-// <i> enables USB Class specific Requests\r
-// <e1> Human Interface Device (HID)\r
-// <o2> Interface Number <0-255>\r
-// </e>\r
-// <e3> Mass Storage\r
-// <o4> Interface Number <0-255>\r
-// </e>\r
-// <e5> Audio Device\r
-// <o6> Control Interface Number <0-255>\r
-// <o7> Streaming Interface 1 Number <0-255>\r
-// <o8> Streaming Interface 2 Number <0-255>\r
-// </e>\r
-// <e9> Communication Device\r
-// <o10> Control Interface Number <0-255>\r
-// <o11> Bulk Interface Number <0-255>\r
-// <o12> Max Communication Device Buffer Size\r
-// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes \r
-// </e>\r
-// </e>\r
-*/\r
-\r
-#define USB_CLASS 1\r
-#define USB_HID 0\r
-#define USB_HID_IF_NUM 0\r
-#define USB_MSC 0\r
-#define USB_MSC_IF_NUM 0\r
-#define USB_AUDIO 0\r
-#define USB_ADC_CIF_NUM 0\r
-#define USB_ADC_SIF1_NUM 1\r
-#define USB_ADC_SIF2_NUM 2\r
-#define USB_CDC 1\r
-#define USB_CDC_CIF_NUM 0\r
-#define USB_CDC_DIF_NUM 1\r
-#define USB_CDC_BUFSIZE 64\r
-\r
-/*\r
-// <e0> USB Vendor Support\r
-// <i> enables USB Vendor specific Requests\r
-// </e>\r
-*/\r
-#define USB_VENDOR 0\r
-\r
-\r
-#endif /* __USBCFG_H__ */\r
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: usbcfg.h
+ * Purpose: USB Custom Configuration
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC family microcontroller devices only. Nothing
+ * else gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *----------------------------------------------------------------------------
+ * History:
+ * V1.20 Added vendor specific support
+ * V1.00 Initial Version
+ *---------------------------------------------------------------------------*/
+
+#ifndef __USBCFG_H__
+#define __USBCFG_H__
+
+
+//*** <<< Use Configuration Wizard in Context Menu >>> ***
+
+
+/*
+// <h> USB Configuration
+// <o0> USB Power
+// <i> Default Power Setting
+// <0=> Bus-powered
+// <1=> Self-powered
+// <o1> Max Number of Interfaces <1-256>
+// <o2> Max Number of Endpoints <1-32>
+// <o3> Max Endpoint 0 Packet Size
+// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes
+// <e4> DMA Transfer
+// <i> Use DMA for selected Endpoints
+// <o5.0> Endpoint 0 Out
+// <o5.1> Endpoint 0 In
+// <o5.2> Endpoint 1 Out
+// <o5.3> Endpoint 1 In
+// <o5.4> Endpoint 2 Out
+// <o5.5> Endpoint 2 In
+// <o5.6> Endpoint 3 Out
+// <o5.7> Endpoint 3 In
+// <o5.8> Endpoint 4 Out
+// <o5.9> Endpoint 4 In
+// <o5.10> Endpoint 5 Out
+// <o5.11> Endpoint 5 In
+// <o5.12> Endpoint 6 Out
+// <o5.13> Endpoint 6 In
+// <o5.14> Endpoint 7 Out
+// <o5.15> Endpoint 7 In
+// <o5.16> Endpoint 8 Out
+// <o5.17> Endpoint 8 In
+// <o5.18> Endpoint 9 Out
+// <o5.19> Endpoint 9 In
+// <o5.20> Endpoint 10 Out
+// <o5.21> Endpoint 10 In
+// <o5.22> Endpoint 11 Out
+// <o5.23> Endpoint 11 In
+// <o5.24> Endpoint 12 Out
+// <o5.25> Endpoint 12 In
+// <o5.26> Endpoint 13 Out
+// <o5.27> Endpoint 13 In
+// <o5.28> Endpoint 14 Out
+// <o5.29> Endpoint 14 In
+// <o5.30> Endpoint 15 Out
+// <o5.31> Endpoint 15 In
+// </e>
+// </h>
+*/
+
+#define USB_POWER 0
+#define USB_IF_NUM 4
+#define USB_EP_NUM 32
+#define USB_MAX_PACKET0 8
+#define USB_DMA 0
+#define USB_DMA_EP 0x00000000
+
+
+/*
+// <h> USB Event Handlers
+// <h> Device Events
+// <o0.0> Power Event
+// <o1.0> Reset Event
+// <o2.0> Suspend Event
+// <o3.0> Resume Event
+// <o4.0> Remote Wakeup Event
+// <o5.0> Start of Frame Event
+// <o6.0> Error Event
+// </h>
+// <h> Endpoint Events
+// <o7.0> Endpoint 0 Event
+// <o7.1> Endpoint 1 Event
+// <o7.2> Endpoint 2 Event
+// <o7.3> Endpoint 3 Event
+// <o7.4> Endpoint 4 Event
+// <o7.5> Endpoint 5 Event
+// <o7.6> Endpoint 6 Event
+// <o7.7> Endpoint 7 Event
+// <o7.8> Endpoint 8 Event
+// <o7.9> Endpoint 9 Event
+// <o7.10> Endpoint 10 Event
+// <o7.11> Endpoint 11 Event
+// <o7.12> Endpoint 12 Event
+// <o7.13> Endpoint 13 Event
+// <o7.14> Endpoint 14 Event
+// <o7.15> Endpoint 15 Event
+// </h>
+// <h> USB Core Events
+// <o8.0> Set Configuration Event
+// <o9.0> Set Interface Event
+// <o10.0> Set/Clear Feature Event
+// </h>
+// </h>
+*/
+
+#define USB_POWER_EVENT 0
+#define USB_RESET_EVENT 1
+#define USB_SUSPEND_EVENT 0
+#define USB_RESUME_EVENT 0
+#define USB_WAKEUP_EVENT 0
+#define USB_SOF_EVENT 0
+#define USB_ERROR_EVENT 0
+#define USB_EP_EVENT 0x0007
+#define USB_CONFIGURE_EVENT 1
+#define USB_INTERFACE_EVENT 0
+#define USB_FEATURE_EVENT 0
+
+
+/*
+// <e0> USB Class Support
+// <i> enables USB Class specific Requests
+// <e1> Human Interface Device (HID)
+// <o2> Interface Number <0-255>
+// </e>
+// <e3> Mass Storage
+// <o4> Interface Number <0-255>
+// </e>
+// <e5> Audio Device
+// <o6> Control Interface Number <0-255>
+// <o7> Streaming Interface 1 Number <0-255>
+// <o8> Streaming Interface 2 Number <0-255>
+// </e>
+// <e9> Communication Device
+// <o10> Control Interface Number <0-255>
+// <o11> Bulk Interface Number <0-255>
+// <o12> Max Communication Device Buffer Size
+// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes
+// </e>
+// </e>
+*/
+
+#define USB_CLASS 1
+#define USB_HID 0
+#define USB_HID_IF_NUM 0
+#define USB_MSC 0
+#define USB_MSC_IF_NUM 0
+#define USB_AUDIO 0
+#define USB_ADC_CIF_NUM 0
+#define USB_ADC_SIF1_NUM 1
+#define USB_ADC_SIF2_NUM 2
+#define USB_CDC 1
+#define USB_CDC_CIF_NUM 0
+#define USB_CDC_DIF_NUM 1
+#define USB_CDC_BUFSIZE 64
+
+/*
+// <e0> USB Vendor Support
+// <i> enables USB Vendor specific Requests
+// </e>
+*/
+#define USB_VENDOR 0
+
+
+#endif /* __USBCFG_H__ */
-/*----------------------------------------------------------------------------\r
- * U S B - K e r n e l\r
- *----------------------------------------------------------------------------\r
- * Name: usbcore.c\r
- * Purpose: USB Core Module\r
- * Version: V1.20\r
- *----------------------------------------------------------------------------\r
- * This software is supplied "AS IS" without any warranties, express,\r
- * implied or statutory, including but not limited to the implied\r
- * warranties of fitness for purpose, satisfactory quality and\r
- * noninfringement. Keil extends you a royalty-free right to reproduce\r
- * and distribute executable files created using this software for use\r
- * on NXP Semiconductors LPC family microcontroller devices only. Nothing\r
- * else gives you the right to use this software.\r
- *\r
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
- *----------------------------------------------------------------------------\r
- * History:\r
- * V1.20 Added vendor specific requests\r
- * Changed string descriptor handling\r
- * Reworked Endpoint0\r
- * V1.00 Initial Version\r
- *----------------------------------------------------------------------------*/\r
-#include "lpc_types.h"\r
-\r
-#include "usb.h"\r
-#include "usbcfg.h"\r
-#include "usbhw.h"\r
-#include "usbcore.h"\r
-#include "usbdesc.h"\r
-#include "usbuser.h"\r
-\r
-#if (USB_CLASS)\r
-\r
-#if (USB_AUDIO)\r
-#include "audio.h"\r
-#include "adcuser.h"\r
-#endif\r
-\r
-#if (USB_HID)\r
-#include "hid.h"\r
-#include "hiduser.h"\r
-#endif\r
-\r
-#if (USB_MSC)\r
-#include "msc.h"\r
-#include "mscuser.h"\r
-extern MSC_CSW CSW;\r
-#endif\r
-\r
-#if (USB_CDC)\r
-#include "cdc.h"\r
-#include "cdcuser.h"\r
-#endif\r
-\r
-#endif\r
-\r
-#if (USB_VENDOR)\r
-#include "vendor.h"\r
-#endif\r
-\r
-#if defined ( __CC_ARM )\r
-#pragma diag_suppress 111,1441\r
-#endif\r
-\r
-#if defined ( __GNUC__ )\r
-#define __packed __attribute__((__packed__))\r
-#endif\r
-\r
-uint16_t USB_DeviceStatus;\r
-uint8_t USB_DeviceAddress;\r
-uint8_t USB_Configuration;\r
-uint32_t USB_EndPointMask;\r
-uint32_t USB_EndPointHalt;\r
-uint32_t USB_EndPointStall; /* EP must stay stalled */\r
-uint8_t USB_NumInterfaces;\r
-uint8_t USB_AltSetting[USB_IF_NUM];\r
-\r
-uint8_t EP0Buf[USB_MAX_PACKET0];\r
-\r
-\r
-USB_EP_DATA EP0Data;\r
-\r
-USB_SETUP_PACKET SetupPacket;\r
-\r
-\r
-/*\r
- * Reset USB Core\r
- * Parameters: None\r
- * Return Value: None\r
- */\r
-\r
-void USB_ResetCore (void) {\r
-\r
- USB_DeviceStatus = USB_POWER;\r
- USB_DeviceAddress = 0;\r
- USB_Configuration = 0;\r
- USB_EndPointMask = 0x00010001;\r
- USB_EndPointHalt = 0x00000000;\r
- USB_EndPointStall = 0x00000000;\r
-}\r
-\r
-\r
-/*\r
- * USB Request - Setup Stage\r
- * Parameters: None (global SetupPacket)\r
- * Return Value: None\r
- */\r
-\r
-void USB_SetupStage (void) {\r
- USB_ReadEP(0x00, (uint8_t *)&SetupPacket);\r
-}\r
-\r
-\r
-/*\r
- * USB Request - Data In Stage\r
- * Parameters: None (global EP0Data)\r
- * Return Value: None\r
- */\r
-\r
-void USB_DataInStage (void) {\r
- uint32_t cnt;\r
-\r
- if (EP0Data.Count > USB_MAX_PACKET0) {\r
- cnt = USB_MAX_PACKET0;\r
- } else {\r
- cnt = EP0Data.Count;\r
- }\r
- cnt = USB_WriteEP(0x80, EP0Data.pData, cnt);\r
- EP0Data.pData += cnt;\r
- EP0Data.Count -= cnt;\r
-}\r
-\r
-\r
-/*\r
- * USB Request - Data Out Stage\r
- * Parameters: None (global EP0Data)\r
- * Return Value: None\r
- */\r
-\r
-void USB_DataOutStage (void) {\r
- uint32_t cnt;\r
-\r
- cnt = USB_ReadEP(0x00, EP0Data.pData);\r
- EP0Data.pData += cnt;\r
- EP0Data.Count -= cnt;\r
-}\r
-\r
-\r
-/*\r
- * USB Request - Status In Stage\r
- * Parameters: None\r
- * Return Value: None\r
- */\r
-\r
-void USB_StatusInStage (void) {\r
- USB_WriteEP(0x80, NULL, 0);\r
-}\r
-\r
-\r
-/*\r
- * USB Request - Status Out Stage\r
- * Parameters: None\r
- * Return Value: None\r
- */\r
-\r
-void USB_StatusOutStage (void) {\r
- USB_ReadEP(0x00, EP0Buf);\r
-}\r
-\r
-\r
-/*\r
- * Get Status USB Request\r
- * Parameters: None (global SetupPacket)\r
- * Return Value: TRUE - Success, FALSE - Error\r
- */\r
-\r
-#if defined ( __IAR_SYSTEMS_ICC__ )\r
-inline uint32_t USB_ReqGetStatus (void) {\r
-#else \r
-__inline uint32_t USB_ReqGetStatus (void) {\r
-#endif\r
- uint32_t n, m;\r
-\r
- switch (SetupPacket.bmRequestType.BM.Recipient) {\r
- case REQUEST_TO_DEVICE:\r
- EP0Data.pData = (uint8_t *)&USB_DeviceStatus;\r
- break;\r
- case REQUEST_TO_INTERFACE:\r
- if ((USB_Configuration != 0) && (SetupPacket.wIndex.WB.L < USB_NumInterfaces)) {\r
- *((__packed uint16_t *)EP0Buf) = 0;\r
- *((uint16_t *)EP0Buf) = 0;\r
- EP0Data.pData = EP0Buf;\r
- } else {\r
- return (FALSE);\r
- }\r
- break;\r
- case REQUEST_TO_ENDPOINT:\r
- n = SetupPacket.wIndex.WB.L & 0x8F;\r
- m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);\r
- if (((USB_Configuration != 0) || ((n & 0x0F) == 0)) && (USB_EndPointMask & m)) {\r
- *((__packed uint16_t *)EP0Buf) = (USB_EndPointHalt & m) ? 1 : 0;\r
- *((uint16_t *)EP0Buf) = (USB_EndPointHalt & m) ? 1 : 0;\r
- EP0Data.pData = EP0Buf;\r
- } else {\r
- return (FALSE);\r
- }\r
- break;\r
- default:\r
- return (FALSE);\r
- }\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*\r
- * Set/Clear Feature USB Request\r
- * Parameters: sc: 0 - Clear, 1 - Set\r
- * (global SetupPacket)\r
- * Return Value: TRUE - Success, FALSE - Error\r
- */\r
-\r
-#if defined ( __IAR_SYSTEMS_ICC__ )\r
-inline uint32_t USB_ReqSetClrFeature (uint32_t sc) {\r
-#else\r
-__inline uint32_t USB_ReqSetClrFeature (uint32_t sc) {\r
-#endif\r
- uint32_t n, m;\r
-\r
- switch (SetupPacket.bmRequestType.BM.Recipient) {\r
- case REQUEST_TO_DEVICE:\r
- if (SetupPacket.wValue.W == USB_FEATURE_REMOTE_WAKEUP) {\r
- if (sc) {\r
- USB_WakeUpCfg(TRUE);\r
- USB_DeviceStatus |= USB_GETSTATUS_REMOTE_WAKEUP;\r
- } else {\r
- USB_WakeUpCfg(FALSE);\r
- USB_DeviceStatus &= ~USB_GETSTATUS_REMOTE_WAKEUP;\r
- }\r
- } else {\r
- return (FALSE);\r
- }\r
- break;\r
- case REQUEST_TO_INTERFACE:\r
- return (FALSE);\r
- case REQUEST_TO_ENDPOINT:\r
- n = SetupPacket.wIndex.WB.L & 0x8F;\r
- m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);\r
- if ((USB_Configuration != 0) && ((n & 0x0F) != 0) && (USB_EndPointMask & m)) {\r
- if (SetupPacket.wValue.W == USB_FEATURE_ENDPOINT_STALL) {\r
- if (sc) {\r
- USB_SetStallEP(n);\r
- USB_EndPointHalt |= m;\r
- } else {\r
- if ((USB_EndPointStall & m) != 0) {\r
- return (TRUE);\r
- }\r
- USB_ClrStallEP(n);\r
-#if (USB_MSC)\r
- if ((n == MSC_EP_IN) && ((USB_EndPointHalt & m) != 0)) {\r
- /* Compliance Test: rewrite CSW after unstall */\r
- if (CSW.dSignature == MSC_CSW_Signature) {\r
- USB_WriteEP(MSC_EP_IN, (uint8_t *)&CSW, sizeof(CSW));\r
- }\r
- }\r
-#endif\r
- USB_EndPointHalt &= ~m;\r
- }\r
- } else {\r
- return (FALSE);\r
- }\r
- } else {\r
- return (FALSE);\r
- }\r
- break;\r
- default:\r
- return (FALSE);\r
- }\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*\r
- * Set Address USB Request\r
- * Parameters: None (global SetupPacket)\r
- * Return Value: TRUE - Success, FALSE - Error\r
- */\r
-\r
-#if defined ( __IAR_SYSTEMS_ICC__ )\r
-inline uint32_t USB_ReqSetAddress (void) {\r
-#else\r
-__inline uint32_t USB_ReqSetAddress (void) {\r
-#endif\r
- switch (SetupPacket.bmRequestType.BM.Recipient) {\r
- case REQUEST_TO_DEVICE:\r
- USB_DeviceAddress = 0x80 | SetupPacket.wValue.WB.L;\r
- break;\r
- default:\r
- return (FALSE);\r
- }\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*\r
- * Get Descriptor USB Request\r
- * Parameters: None (global SetupPacket)\r
- * Return Value: TRUE - Success, FALSE - Error\r
- */\r
-\r
-#if defined ( __IAR_SYSTEMS_ICC__ )\r
-inline uint32_t USB_ReqGetDescriptor (void) {\r
-#else\r
-__inline uint32_t USB_ReqGetDescriptor (void) {\r
-#endif\r
- uint8_t *pD;\r
- uint32_t len, n;\r
-\r
- switch (SetupPacket.bmRequestType.BM.Recipient) {\r
- case REQUEST_TO_DEVICE:\r
- switch (SetupPacket.wValue.WB.H) {\r
- case USB_DEVICE_DESCRIPTOR_TYPE:\r
- EP0Data.pData = (uint8_t *)USB_DeviceDescriptor;\r
- len = USB_DEVICE_DESC_SIZE;\r
- break;\r
- case USB_CONFIGURATION_DESCRIPTOR_TYPE:\r
- pD = (uint8_t *)USB_ConfigDescriptor;\r
- for (n = 0; n != SetupPacket.wValue.WB.L; n++) {\r
- if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bLength != 0) {\r
- pD += ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;\r
- }\r
- }\r
- if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bLength == 0) {\r
- return (FALSE);\r
- }\r
- EP0Data.pData = pD;\r
- len = ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;\r
- break;\r
- case USB_STRING_DESCRIPTOR_TYPE:\r
- pD = (uint8_t *)USB_StringDescriptor;\r
- for (n = 0; n != SetupPacket.wValue.WB.L; n++) {\r
- if (((USB_STRING_DESCRIPTOR *)pD)->bLength != 0) {\r
- pD += ((USB_STRING_DESCRIPTOR *)pD)->bLength;\r
- }\r
- }\r
- if (((USB_STRING_DESCRIPTOR *)pD)->bLength == 0) {\r
- return (FALSE);\r
- }\r
- EP0Data.pData = pD;\r
- len = ((USB_STRING_DESCRIPTOR *)EP0Data.pData)->bLength;\r
- break;\r
- default:\r
- return (FALSE);\r
- }\r
- break;\r
- case REQUEST_TO_INTERFACE:\r
- switch (SetupPacket.wValue.WB.H) {\r
-#if USB_HID\r
- case HID_HID_DESCRIPTOR_TYPE:\r
- if (SetupPacket.wIndex.WB.L != USB_HID_IF_NUM) {\r
- return (FALSE); /* Only Single HID Interface is supported */\r
- }\r
- EP0Data.pData = (uint8_t *)USB_ConfigDescriptor + HID_DESC_OFFSET;\r
- len = HID_DESC_SIZE;\r
- break;\r
- case HID_REPORT_DESCRIPTOR_TYPE:\r
- if (SetupPacket.wIndex.WB.L != USB_HID_IF_NUM) {\r
- return (FALSE); /* Only Single HID Interface is supported */\r
- }\r
- EP0Data.pData = (uint8_t *)HID_ReportDescriptor;\r
- len = HID_ReportDescSize;\r
- break;\r
- case HID_PHYSICAL_DESCRIPTOR_TYPE:\r
- return (FALSE); /* HID Physical Descriptor is not supported */\r
-#endif\r
- default:\r
- return (FALSE);\r
- }\r
-// break;\r
- default:\r
- return (FALSE);\r
- }\r
-\r
- if (EP0Data.Count > len) {\r
- EP0Data.Count = len;\r
- }\r
-\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*\r
- * Get Configuration USB Request\r
- * Parameters: None (global SetupPacket)\r
- * Return Value: TRUE - Success, FALSE - Error\r
- */\r
-\r
-#if defined ( __IAR_SYSTEMS_ICC__ )\r
-inline uint32_t USB_ReqGetConfiguration (void) {\r
-#else\r
-__inline uint32_t USB_ReqGetConfiguration (void) {\r
-#endif\r
- switch (SetupPacket.bmRequestType.BM.Recipient) {\r
- case REQUEST_TO_DEVICE:\r
- EP0Data.pData = &USB_Configuration;\r
- break;\r
- default:\r
- return (FALSE);\r
- }\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*\r
- * Set Configuration USB Request\r
- * Parameters: None (global SetupPacket)\r
- * Return Value: TRUE - Success, FALSE - Error\r
- */\r
-\r
-#if defined ( __IAR_SYSTEMS_ICC__ )\r
-inline uint32_t USB_ReqSetConfiguration (void) {\r
-#else\r
-__inline uint32_t USB_ReqSetConfiguration (void) {\r
-#endif\r
- USB_COMMON_DESCRIPTOR *pD;\r
- uint32_t alt = 0;\r
- uint32_t n, m;\r
- uint32_t tmp;\r
-\r
- switch (SetupPacket.bmRequestType.BM.Recipient) {\r
- case REQUEST_TO_DEVICE:\r
-\r
- if (SetupPacket.wValue.WB.L) {\r
- pD = (USB_COMMON_DESCRIPTOR *)USB_ConfigDescriptor;\r
- while (pD->bLength) {\r
- switch (pD->bDescriptorType) {\r
- case USB_CONFIGURATION_DESCRIPTOR_TYPE:\r
- if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bConfigurationValue == SetupPacket.wValue.WB.L) {\r
- USB_Configuration = SetupPacket.wValue.WB.L;\r
- USB_NumInterfaces = ((USB_CONFIGURATION_DESCRIPTOR *)pD)->bNumInterfaces;\r
- for (n = 0; n < USB_IF_NUM; n++) {\r
- USB_AltSetting[n] = 0;\r
- }\r
- for (n = 1; n < 16; n++) {\r
- if (USB_EndPointMask & (1 << n)) {\r
- USB_DisableEP(n);\r
- }\r
- if (USB_EndPointMask & ((1 << 16) << n)) {\r
- USB_DisableEP(n | 0x80);\r
- }\r
- }\r
- USB_EndPointMask = 0x00010001;\r
- USB_EndPointHalt = 0x00000000;\r
- USB_EndPointStall= 0x00000000;\r
- USB_Configure(TRUE);\r
- if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bmAttributes & USB_CONFIG_POWERED_MASK) {\r
- USB_DeviceStatus |= USB_GETSTATUS_SELF_POWERED;\r
- } else {\r
- USB_DeviceStatus &= ~USB_GETSTATUS_SELF_POWERED;\r
- }\r
- } else {\r
-// (uint8_t *)pD += ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;\r
- tmp = (uint32_t)pD;\r
- tmp += ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;\r
- pD = (USB_COMMON_DESCRIPTOR *)tmp;\r
- continue;\r
- }\r
- break;\r
- case USB_INTERFACE_DESCRIPTOR_TYPE:\r
- alt = ((USB_INTERFACE_DESCRIPTOR *)pD)->bAlternateSetting;\r
- break;\r
- case USB_ENDPOINT_DESCRIPTOR_TYPE:\r
- if (alt == 0) {\r
- n = ((USB_ENDPOINT_DESCRIPTOR *)pD)->bEndpointAddress & 0x8F;\r
- m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);\r
- USB_EndPointMask |= m;\r
- USB_ConfigEP((USB_ENDPOINT_DESCRIPTOR *)pD);\r
- USB_EnableEP(n);\r
- USB_ResetEP(n);\r
- }\r
- break;\r
- }\r
-// (uint8_t *)pD += pD->bLength;\r
- tmp = (uint32_t)pD;\r
- tmp += pD->bLength;\r
- pD = (USB_COMMON_DESCRIPTOR *)tmp;\r
- }\r
- }\r
- else {\r
- USB_Configuration = 0;\r
- for (n = 1; n < 16; n++) {\r
- if (USB_EndPointMask & (1 << n)) {\r
- USB_DisableEP(n);\r
- }\r
- if (USB_EndPointMask & ((1 << 16) << n)) {\r
- USB_DisableEP(n | 0x80);\r
- }\r
- }\r
- USB_EndPointMask = 0x00010001;\r
- USB_EndPointHalt = 0x00000000;\r
- USB_EndPointStall = 0x00000000;\r
- USB_Configure(FALSE);\r
- }\r
-\r
- if (USB_Configuration != SetupPacket.wValue.WB.L) {\r
- return (FALSE);\r
- }\r
- break;\r
- default:\r
- return (FALSE);\r
- }\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*\r
- * Get Interface USB Request\r
- * Parameters: None (global SetupPacket)\r
- * Return Value: TRUE - Success, FALSE - Error\r
- */\r
-\r
-#if defined ( __IAR_SYSTEMS_ICC__ )\r
-inline uint32_t USB_ReqGetInterface (void) {\r
-#else\r
-__inline uint32_t USB_ReqGetInterface (void) {\r
-#endif\r
- switch (SetupPacket.bmRequestType.BM.Recipient) {\r
- case REQUEST_TO_INTERFACE:\r
- if ((USB_Configuration != 0) && (SetupPacket.wIndex.WB.L < USB_NumInterfaces)) {\r
- EP0Data.pData = USB_AltSetting + SetupPacket.wIndex.WB.L;\r
- } else {\r
- return (FALSE);\r
- }\r
- break;\r
- default:\r
- return (FALSE);\r
- }\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*\r
- * Set Interface USB Request\r
- * Parameters: None (global SetupPacket)\r
- * Return Value: TRUE - Success, FALSE - Error\r
- */\r
-#if defined ( __IAR_SYSTEMS_ICC__ )\r
-inline uint32_t USB_ReqSetInterface (void) {\r
-#else\r
-__inline uint32_t USB_ReqSetInterface (void) {\r
-#endif\r
- USB_COMMON_DESCRIPTOR *pD;\r
- uint32_t ifn = 0, alt = 0, old = 0, msk = 0;\r
- uint32_t n, m;\r
- uint32_t set;\r
- uint32_t tmp;\r
-\r
- switch (SetupPacket.bmRequestType.BM.Recipient) {\r
- case REQUEST_TO_INTERFACE:\r
- if (USB_Configuration == 0) return (FALSE);\r
- set = FALSE;\r
- pD = (USB_COMMON_DESCRIPTOR *)USB_ConfigDescriptor;\r
- while (pD->bLength) {\r
- switch (pD->bDescriptorType) {\r
- case USB_CONFIGURATION_DESCRIPTOR_TYPE:\r
- if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bConfigurationValue != USB_Configuration) {\r
-// (uint8_t *)pD += ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;\r
- tmp = (uint32_t)pD;\r
- tmp += ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;\r
- pD = (USB_COMMON_DESCRIPTOR *)tmp;\r
-\r
- continue;\r
- }\r
- break;\r
- case USB_INTERFACE_DESCRIPTOR_TYPE:\r
- ifn = ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber;\r
- alt = ((USB_INTERFACE_DESCRIPTOR *)pD)->bAlternateSetting;\r
- msk = 0;\r
- if ((ifn == SetupPacket.wIndex.WB.L) && (alt == SetupPacket.wValue.WB.L)) {\r
- set = TRUE;\r
- old = USB_AltSetting[ifn];\r
- USB_AltSetting[ifn] = (uint8_t)alt;\r
- }\r
- break;\r
- case USB_ENDPOINT_DESCRIPTOR_TYPE:\r
- if (ifn == SetupPacket.wIndex.WB.L) {\r
- n = ((USB_ENDPOINT_DESCRIPTOR *)pD)->bEndpointAddress & 0x8F;\r
- m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);\r
- if (alt == SetupPacket.wValue.WB.L) {\r
- USB_EndPointMask |= m;\r
- USB_EndPointHalt &= ~m;\r
- USB_ConfigEP((USB_ENDPOINT_DESCRIPTOR *)pD);\r
- USB_EnableEP(n);\r
- USB_ResetEP(n);\r
- msk |= m;\r
- }\r
- else if ((alt == old) && ((msk & m) == 0)) {\r
- USB_EndPointMask &= ~m;\r
- USB_EndPointHalt &= ~m;\r
- USB_DisableEP(n);\r
- }\r
- }\r
- break;\r
- }\r
-// (uint8_t *)pD += pD->bLength;\r
- tmp = (uint32_t)pD;\r
- tmp += pD->bLength;\r
- pD = (USB_COMMON_DESCRIPTOR *)tmp;\r
- }\r
- break;\r
- default:\r
- return (FALSE);\r
- }\r
-\r
- return (set);\r
-}\r
-\r
-\r
-/*\r
- * USB Endpoint 0 Event Callback\r
- * Parameters: event\r
- * Return Value: none\r
- */\r
-\r
-void USB_EndPoint0 (uint32_t event) {\r
-\r
- switch (event) {\r
- case USB_EVT_SETUP:\r
- USB_SetupStage();\r
- USB_DirCtrlEP(SetupPacket.bmRequestType.BM.Dir);\r
- EP0Data.Count = SetupPacket.wLength; /* Number of bytes to transfer */\r
- switch (SetupPacket.bmRequestType.BM.Type) {\r
-\r
- case REQUEST_STANDARD:\r
- switch (SetupPacket.bRequest) {\r
- case USB_REQUEST_GET_STATUS:\r
- if (!USB_ReqGetStatus()) {\r
- goto stall_i;\r
- }\r
- USB_DataInStage();\r
- break;\r
-\r
- case USB_REQUEST_CLEAR_FEATURE:\r
- if (!USB_ReqSetClrFeature(0)) {\r
- goto stall_i;\r
- }\r
- USB_StatusInStage();\r
-#if USB_FEATURE_EVENT\r
- USB_Feature_Event();\r
-#endif\r
- break;\r
-\r
- case USB_REQUEST_SET_FEATURE:\r
- if (!USB_ReqSetClrFeature(1)) {\r
- goto stall_i;\r
- }\r
- USB_StatusInStage();\r
-#if USB_FEATURE_EVENT\r
- USB_Feature_Event();\r
-#endif\r
- break;\r
-\r
- case USB_REQUEST_SET_ADDRESS:\r
- if (!USB_ReqSetAddress()) {\r
- goto stall_i;\r
- }\r
- USB_StatusInStage();\r
- break;\r
-\r
- case USB_REQUEST_GET_DESCRIPTOR:\r
- if (!USB_ReqGetDescriptor()) {\r
- goto stall_i;\r
- }\r
- USB_DataInStage();\r
- break;\r
-\r
- case USB_REQUEST_SET_DESCRIPTOR:\r
-/*stall_o:*/ USB_SetStallEP(0x00); /* not supported */\r
- EP0Data.Count = 0;\r
- break;\r
-\r
- case USB_REQUEST_GET_CONFIGURATION:\r
- if (!USB_ReqGetConfiguration()) {\r
- goto stall_i;\r
- }\r
- USB_DataInStage();\r
- break;\r
-\r
- case USB_REQUEST_SET_CONFIGURATION:\r
- if (!USB_ReqSetConfiguration()) {\r
- goto stall_i;\r
- }\r
- USB_StatusInStage();\r
-#if USB_CONFIGURE_EVENT\r
- USB_Configure_Event();\r
-#endif\r
- break;\r
-\r
- case USB_REQUEST_GET_INTERFACE:\r
- if (!USB_ReqGetInterface()) {\r
- goto stall_i;\r
- }\r
- USB_DataInStage();\r
- break;\r
-\r
- case USB_REQUEST_SET_INTERFACE:\r
- if (!USB_ReqSetInterface()) {\r
- goto stall_i;\r
- }\r
- USB_StatusInStage();\r
-#if USB_INTERFACE_EVENT\r
- USB_Interface_Event();\r
-#endif\r
- break;\r
-\r
- default:\r
- goto stall_i;\r
- }\r
- break; /* end case REQUEST_STANDARD */\r
-\r
-#if USB_CLASS\r
- case REQUEST_CLASS:\r
- switch (SetupPacket.bmRequestType.BM.Recipient) {\r
-\r
- case REQUEST_TO_DEVICE:\r
- goto stall_i; /* not supported */\r
-\r
- case REQUEST_TO_INTERFACE:\r
-#if USB_HID\r
- if (SetupPacket.wIndex.WB.L == USB_HID_IF_NUM) { /* IF number correct? */\r
- switch (SetupPacket.bRequest) {\r
- case HID_REQUEST_GET_REPORT:\r
- if (HID_GetReport()) {\r
- EP0Data.pData = EP0Buf; /* point to data to be sent */\r
- USB_DataInStage(); /* send requested data */\r
- goto setup_class_ok;\r
- }\r
- break;\r
- case HID_REQUEST_SET_REPORT:\r
- EP0Data.pData = EP0Buf; /* data to be received */\r
- goto setup_class_ok;\r
- case HID_REQUEST_GET_IDLE:\r
- if (HID_GetIdle()) {\r
- EP0Data.pData = EP0Buf; /* point to data to be sent */\r
- USB_DataInStage(); /* send requested data */\r
- goto setup_class_ok;\r
- }\r
- break;\r
- case HID_REQUEST_SET_IDLE:\r
- if (HID_SetIdle()) {\r
- USB_StatusInStage(); /* send Acknowledge */\r
- goto setup_class_ok;\r
- }\r
- break;\r
- case HID_REQUEST_GET_PROTOCOL:\r
- if (HID_GetProtocol()) {\r
- EP0Data.pData = EP0Buf; /* point to data to be sent */\r
- USB_DataInStage(); /* send requested data */\r
- goto setup_class_ok;\r
- }\r
- break;\r
- case HID_REQUEST_SET_PROTOCOL:\r
- if (HID_SetProtocol()) {\r
- USB_StatusInStage(); /* send Acknowledge */\r
- goto setup_class_ok;\r
- }\r
- break;\r
- }\r
- }\r
-#endif /* USB_HID */\r
-#if USB_MSC\r
- if (SetupPacket.wIndex.WB.L == USB_MSC_IF_NUM) { /* IF number correct? */\r
- switch (SetupPacket.bRequest) {\r
- case MSC_REQUEST_RESET:\r
- if ((SetupPacket.wValue.W == 0) && /* RESET with invalid parameters -> STALL */\r
- (SetupPacket.wLength == 0)) {\r
- if (MSC_Reset()) {\r
- USB_StatusInStage();\r
- goto setup_class_ok;\r
- }\r
- }\r
- break;\r
- case MSC_REQUEST_GET_MAX_LUN:\r
- if ((SetupPacket.wValue.W == 0) && /* GET_MAX_LUN with invalid parameters -> STALL */\r
- (SetupPacket.wLength == 1)) {\r
- if (MSC_GetMaxLUN()) {\r
- EP0Data.pData = EP0Buf;\r
- USB_DataInStage();\r
- goto setup_class_ok;\r
- }\r
- }\r
- break;\r
- }\r
- }\r
-#endif /* USB_MSC */\r
-#if USB_AUDIO\r
- if ((SetupPacket.wIndex.WB.L == USB_ADC_CIF_NUM) || /* IF number correct? */\r
- (SetupPacket.wIndex.WB.L == USB_ADC_SIF1_NUM) ||\r
- (SetupPacket.wIndex.WB.L == USB_ADC_SIF2_NUM)) {\r
- switch (SetupPacket.bRequest) {\r
- case AUDIO_REQUEST_GET_CUR:\r
- case AUDIO_REQUEST_GET_MIN:\r
- case AUDIO_REQUEST_GET_MAX:\r
- case AUDIO_REQUEST_GET_RES:\r
- if (ADC_IF_GetRequest()) {\r
- EP0Data.pData = EP0Buf; /* point to data to be sent */\r
- USB_DataInStage(); /* send requested data */\r
- goto setup_class_ok;\r
- }\r
- break;\r
- case AUDIO_REQUEST_SET_CUR:\r
-// case AUDIO_REQUEST_SET_MIN:\r
-// case AUDIO_REQUEST_SET_MAX:\r
-// case AUDIO_REQUEST_SET_RES:\r
- EP0Data.pData = EP0Buf; /* data to be received */\r
- goto setup_class_ok;\r
- }\r
- }\r
-#endif /* USB_AUDIO */\r
-#if USB_CDC\r
- if ((SetupPacket.wIndex.WB.L == USB_CDC_CIF_NUM) || /* IF number correct? */\r
- (SetupPacket.wIndex.WB.L == USB_CDC_DIF_NUM)) {\r
- switch (SetupPacket.bRequest) {\r
- case CDC_SEND_ENCAPSULATED_COMMAND:\r
- EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */\r
- goto setup_class_ok;\r
- case CDC_GET_ENCAPSULATED_RESPONSE:\r
- if (CDC_GetEncapsulatedResponse()) {\r
- EP0Data.pData = EP0Buf; /* point to data to be sent */\r
- USB_DataInStage(); /* send requested data */\r
- goto setup_class_ok;\r
- }\r
- break;\r
- case CDC_SET_COMM_FEATURE:\r
- EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */\r
- goto setup_class_ok;\r
- case CDC_GET_COMM_FEATURE:\r
- if (CDC_GetCommFeature(SetupPacket.wValue.W)) {\r
- EP0Data.pData = EP0Buf; /* point to data to be sent */\r
- USB_DataInStage(); /* send requested data */\r
- goto setup_class_ok;\r
- }\r
- break;\r
- case CDC_CLEAR_COMM_FEATURE:\r
- if (CDC_ClearCommFeature(SetupPacket.wValue.W)) {\r
- USB_StatusInStage(); /* send Acknowledge */\r
- goto setup_class_ok;\r
- }\r
- break;\r
- case CDC_SET_LINE_CODING:\r
- EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */\r
- goto setup_class_ok;\r
- case CDC_GET_LINE_CODING:\r
- if (CDC_GetLineCoding()) {\r
- EP0Data.pData = EP0Buf; /* point to data to be sent */\r
- USB_DataInStage(); /* send requested data */\r
- goto setup_class_ok;\r
- }\r
- break;\r
- case CDC_SET_CONTROL_LINE_STATE:\r
- if (CDC_SetControlLineState(SetupPacket.wValue.W)) {\r
- USB_StatusInStage(); /* send Acknowledge */\r
- goto setup_class_ok;\r
- }\r
- break;\r
- case CDC_SEND_BREAK:\r
- if (CDC_SendBreak(SetupPacket.wValue.W)) {\r
- USB_StatusInStage(); /* send Acknowledge */\r
- goto setup_class_ok;\r
- }\r
- break;\r
- }\r
- }\r
-#endif /* USB_CDC */\r
- goto stall_i; /* not supported */\r
- /* end case REQUEST_TO_INTERFACE */\r
-\r
- case REQUEST_TO_ENDPOINT:\r
-#if USB_AUDIO\r
- switch (SetupPacket.bRequest) {\r
- case AUDIO_REQUEST_GET_CUR:\r
- case AUDIO_REQUEST_GET_MIN:\r
- case AUDIO_REQUEST_GET_MAX:\r
- case AUDIO_REQUEST_GET_RES:\r
- if (ADC_EP_GetRequest()) {\r
- EP0Data.pData = EP0Buf; /* point to data to be sent */\r
- USB_DataInStage(); /* send requested data */\r
- goto setup_class_ok;\r
- }\r
- break;\r
- case AUDIO_REQUEST_SET_CUR:\r
-// case AUDIO_REQUEST_SET_MIN:\r
-// case AUDIO_REQUEST_SET_MAX:\r
-// case AUDIO_REQUEST_SET_RES:\r
- EP0Data.pData = EP0Buf; /* data to be received */\r
- goto setup_class_ok;\r
- }\r
-#endif /* USB_AUDIO */\r
- goto stall_i;\r
- /* end case REQUEST_TO_ENDPOINT */\r
-\r
- default:\r
- goto stall_i;\r
- }\r
-setup_class_ok: /* request finished successfully */\r
- break; /* end case REQUEST_CLASS */\r
-#endif /* USB_CLASS */\r
-\r
-#if USB_VENDOR\r
- case REQUEST_VENDOR:\r
- switch (SetupPacket.bmRequestType.BM.Recipient) {\r
-\r
- case REQUEST_TO_DEVICE:\r
- if (!USB_ReqVendorDev(TRUE)) {\r
- goto stall_i; /* not supported */\r
- }\r
- break;\r
-\r
- case REQUEST_TO_INTERFACE:\r
- if (!USB_ReqVendorIF(TRUE)) {\r
- goto stall_i; /* not supported */\r
- }\r
- break;\r
-\r
- case REQUEST_TO_ENDPOINT:\r
- if (!USB_ReqVendorEP(TRUE)) {\r
- goto stall_i; /* not supported */\r
- }\r
- break;\r
-\r
- default:\r
- goto stall_i;\r
- }\r
-\r
- if (SetupPacket.wLength) {\r
- if (SetupPacket.bmRequestType.BM.Dir == REQUEST_DEVICE_TO_HOST) {\r
- USB_DataInStage();\r
- }\r
- } else {\r
- USB_StatusInStage();\r
- }\r
-\r
- break; /* end case REQUEST_VENDOR */\r
-#endif /* USB_VENDOR */\r
-\r
- default:\r
-stall_i: USB_SetStallEP(0x80);\r
- EP0Data.Count = 0;\r
- break;\r
- }\r
- break; /* end case USB_EVT_SETUP */\r
-\r
- case USB_EVT_OUT:\r
- if (SetupPacket.bmRequestType.BM.Dir == REQUEST_HOST_TO_DEVICE) {\r
- if (EP0Data.Count) { /* still data to receive ? */\r
- USB_DataOutStage(); /* receive data */\r
- if (EP0Data.Count == 0) { /* data complete ? */\r
- switch (SetupPacket.bmRequestType.BM.Type) {\r
-\r
- case REQUEST_STANDARD:\r
- goto stall_i; /* not supported */\r
-\r
-#if (USB_CLASS)\r
- case REQUEST_CLASS:\r
- switch (SetupPacket.bmRequestType.BM.Recipient) {\r
- case REQUEST_TO_DEVICE:\r
- goto stall_i; /* not supported */\r
-\r
- case REQUEST_TO_INTERFACE:\r
-#if USB_HID\r
- if (SetupPacket.wIndex.WB.L == USB_HID_IF_NUM) { /* IF number correct? */\r
- switch (SetupPacket.bRequest) {\r
- case HID_REQUEST_SET_REPORT:\r
- if (HID_SetReport()) {\r
- USB_StatusInStage(); /* send Acknowledge */\r
- goto out_class_ok;\r
- }\r
- break;\r
- }\r
- }\r
-#endif /* USB_HID */\r
-#if USB_AUDIO\r
- if ((SetupPacket.wIndex.WB.L == USB_ADC_CIF_NUM) || /* IF number correct? */\r
- (SetupPacket.wIndex.WB.L == USB_ADC_SIF1_NUM) ||\r
- (SetupPacket.wIndex.WB.L == USB_ADC_SIF2_NUM)) {\r
- switch (SetupPacket.bRequest) {\r
- case AUDIO_REQUEST_SET_CUR:\r
-// case AUDIO_REQUEST_SET_MIN:\r
-// case AUDIO_REQUEST_SET_MAX:\r
-// case AUDIO_REQUEST_SET_RES:\r
- if (ADC_IF_SetRequest()) {\r
- USB_StatusInStage(); /* send Acknowledge */\r
- goto out_class_ok;\r
- }\r
- break;\r
- }\r
- }\r
-#endif /* USB_AUDIO */\r
-#if USB_CDC\r
- if ((SetupPacket.wIndex.WB.L == USB_CDC_CIF_NUM) || /* IF number correct? */\r
- (SetupPacket.wIndex.WB.L == USB_CDC_DIF_NUM)) {\r
- switch (SetupPacket.bRequest) {\r
- case CDC_SEND_ENCAPSULATED_COMMAND:\r
- if (CDC_SendEncapsulatedCommand()) {\r
- USB_StatusInStage(); /* send Acknowledge */\r
- goto out_class_ok;\r
- }\r
- break;\r
- case CDC_SET_COMM_FEATURE:\r
- if (CDC_SetCommFeature(SetupPacket.wValue.W)) {\r
- USB_StatusInStage(); /* send Acknowledge */\r
- goto out_class_ok;\r
- }\r
- break;\r
- case CDC_SET_LINE_CODING:\r
- if (CDC_SetLineCoding()) {\r
- USB_StatusInStage(); /* send Acknowledge */\r
- goto out_class_ok;\r
- }\r
- break;\r
- }\r
- }\r
-#endif /* USB_CDC */\r
- goto stall_i;\r
- /* end case REQUEST_TO_INTERFACE */\r
-\r
- case REQUEST_TO_ENDPOINT:\r
-#if USB_AUDIO\r
- switch (SetupPacket.bRequest) {\r
- case AUDIO_REQUEST_SET_CUR:\r
-// case AUDIO_REQUEST_SET_MIN:\r
-// case AUDIO_REQUEST_SET_MAX:\r
-// case AUDIO_REQUEST_SET_RES:\r
- if (ADC_EP_SetRequest()) {\r
- USB_StatusInStage(); /* send Acknowledge */\r
- goto out_class_ok;\r
- }\r
- break;\r
- }\r
-#endif /* USB_AUDIO */\r
- goto stall_i;\r
- /* end case REQUEST_TO_ENDPOINT */\r
-\r
- default:\r
- goto stall_i;\r
- }\r
-out_class_ok: /* request finished successfully */\r
- break; /* end case REQUEST_CLASS */\r
-#endif /* USB_CLASS */\r
-\r
-#if USB_VENDOR\r
- case REQUEST_VENDOR:\r
- switch (SetupPacket.bmRequestType.BM.Recipient) {\r
-\r
- case REQUEST_TO_DEVICE:\r
- if (!USB_ReqVendorDev(FALSE)) {\r
- goto stall_i; /* not supported */\r
- }\r
- break;\r
-\r
- case REQUEST_TO_INTERFACE:\r
- if (!USB_ReqVendorIF(FALSE)) {\r
- goto stall_i; /* not supported */\r
- }\r
- break;\r
-\r
- case REQUEST_TO_ENDPOINT:\r
- if (!USB_ReqVendorEP(FALSE)) {\r
- goto stall_i; /* not supported */\r
- }\r
- break;\r
-\r
- default:\r
- goto stall_i;\r
- }\r
-\r
- USB_StatusInStage();\r
-\r
- break; /* end case REQUEST_VENDOR */\r
-#endif /* USB_VENDOR */\r
-\r
- default:\r
- goto stall_i;\r
- }\r
- }\r
- }\r
- } else {\r
- USB_StatusOutStage(); /* receive Acknowledge */\r
- }\r
- break; /* end case USB_EVT_OUT */\r
-\r
- case USB_EVT_IN :\r
- if (SetupPacket.bmRequestType.BM.Dir == REQUEST_DEVICE_TO_HOST) {\r
- USB_DataInStage(); /* send data */\r
- } else {\r
- if (USB_DeviceAddress & 0x80) {\r
- USB_DeviceAddress &= 0x7F;\r
- USB_SetAddress(USB_DeviceAddress);\r
- }\r
- }\r
- break; /* end case USB_EVT_IN */\r
-\r
- case USB_EVT_OUT_STALL:\r
- USB_ClrStallEP(0x00);\r
- break;\r
-\r
- case USB_EVT_IN_STALL:\r
- USB_ClrStallEP(0x80);\r
- break;\r
-\r
- }\r
-}\r
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: usbcore.c
+ * Purpose: USB Core Module
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC family microcontroller devices only. Nothing
+ * else gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *----------------------------------------------------------------------------
+ * History:
+ * V1.20 Added vendor specific requests
+ * Changed string descriptor handling
+ * Reworked Endpoint0
+ * V1.00 Initial Version
+ *----------------------------------------------------------------------------*/
+#include "lpc_types.h"
+
+#include "usb.h"
+#include "cfg.h"
+#include "hw.h"
+#include "core.h"
+#include "desc.h"
+#include "user.h"
+
+#if (USB_CLASS)
+
+#if (USB_AUDIO)
+#include "audio.h"
+#include "adcuser.h"
+#endif
+
+#if (USB_HID)
+#include "hid.h"
+#include "hiduser.h"
+#endif
+
+#if (USB_MSC)
+#include "msc.h"
+#include "mscuser.h"
+extern MSC_CSW CSW;
+#endif
+
+#if (USB_CDC)
+#include "cdc.h"
+#include "cdcuser.h"
+#endif
+
+#endif
+
+#if (USB_VENDOR)
+#include "vendor.h"
+#endif
+
+#if defined ( __CC_ARM )
+#pragma diag_suppress 111,1441
+#endif
+
+#if defined ( __GNUC__ )
+#define __packed __attribute__((__packed__))
+#endif
+
+uint16_t USB_DeviceStatus;
+uint8_t USB_DeviceAddress;
+uint8_t USB_Configuration;
+uint32_t USB_EndPointMask;
+uint32_t USB_EndPointHalt;
+uint32_t USB_EndPointStall; /* EP must stay stalled */
+uint8_t USB_NumInterfaces;
+uint8_t USB_AltSetting[USB_IF_NUM];
+
+uint8_t EP0Buf[USB_MAX_PACKET0];
+
+
+USB_EP_DATA EP0Data;
+
+USB_SETUP_PACKET SetupPacket;
+
+
+/*
+ * Reset USB Core
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USB_ResetCore (void) {
+
+ USB_DeviceStatus = USB_POWER;
+ USB_DeviceAddress = 0;
+ USB_Configuration = 0;
+ USB_EndPointMask = 0x00010001;
+ USB_EndPointHalt = 0x00000000;
+ USB_EndPointStall = 0x00000000;
+}
+
+
+/*
+ * USB Request - Setup Stage
+ * Parameters: None (global SetupPacket)
+ * Return Value: None
+ */
+
+void USB_SetupStage (void) {
+ USB_ReadEP(0x00, (uint8_t *)&SetupPacket);
+}
+
+
+/*
+ * USB Request - Data In Stage
+ * Parameters: None (global EP0Data)
+ * Return Value: None
+ */
+
+void USB_DataInStage (void) {
+ uint32_t cnt;
+
+ if (EP0Data.Count > USB_MAX_PACKET0) {
+ cnt = USB_MAX_PACKET0;
+ } else {
+ cnt = EP0Data.Count;
+ }
+ cnt = USB_WriteEP(0x80, EP0Data.pData, cnt);
+ EP0Data.pData += cnt;
+ EP0Data.Count -= cnt;
+}
+
+
+/*
+ * USB Request - Data Out Stage
+ * Parameters: None (global EP0Data)
+ * Return Value: None
+ */
+
+void USB_DataOutStage (void) {
+ uint32_t cnt;
+
+ cnt = USB_ReadEP(0x00, EP0Data.pData);
+ EP0Data.pData += cnt;
+ EP0Data.Count -= cnt;
+}
+
+
+/*
+ * USB Request - Status In Stage
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USB_StatusInStage (void) {
+ USB_WriteEP(0x80, NULL, 0);
+}
+
+
+/*
+ * USB Request - Status Out Stage
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USB_StatusOutStage (void) {
+ USB_ReadEP(0x00, EP0Buf);
+}
+
+
+/*
+ * Get Status USB Request
+ * Parameters: None (global SetupPacket)
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+#if defined ( __IAR_SYSTEMS_ICC__ )
+inline uint32_t USB_ReqGetStatus (void) {
+#else
+__inline uint32_t USB_ReqGetStatus (void) {
+#endif
+ uint32_t n, m;
+
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+ case REQUEST_TO_DEVICE:
+ EP0Data.pData = (uint8_t *)&USB_DeviceStatus;
+ break;
+ case REQUEST_TO_INTERFACE:
+ if ((USB_Configuration != 0) && (SetupPacket.wIndex.WB.L < USB_NumInterfaces)) {
+ *((__packed uint16_t *)EP0Buf) = 0;
+ *((uint16_t *)EP0Buf) = 0;
+ EP0Data.pData = EP0Buf;
+ } else {
+ return (FALSE);
+ }
+ break;
+ case REQUEST_TO_ENDPOINT:
+ n = SetupPacket.wIndex.WB.L & 0x8F;
+ m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);
+ if (((USB_Configuration != 0) || ((n & 0x0F) == 0)) && (USB_EndPointMask & m)) {
+ *((__packed uint16_t *)EP0Buf) = (USB_EndPointHalt & m) ? 1 : 0;
+ *((uint16_t *)EP0Buf) = (USB_EndPointHalt & m) ? 1 : 0;
+ EP0Data.pData = EP0Buf;
+ } else {
+ return (FALSE);
+ }
+ break;
+ default:
+ return (FALSE);
+ }
+ return (TRUE);
+}
+
+
+/*
+ * Set/Clear Feature USB Request
+ * Parameters: sc: 0 - Clear, 1 - Set
+ * (global SetupPacket)
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+#if defined ( __IAR_SYSTEMS_ICC__ )
+inline uint32_t USB_ReqSetClrFeature (uint32_t sc) {
+#else
+__inline uint32_t USB_ReqSetClrFeature (uint32_t sc) {
+#endif
+ uint32_t n, m;
+
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+ case REQUEST_TO_DEVICE:
+ if (SetupPacket.wValue.W == USB_FEATURE_REMOTE_WAKEUP) {
+ if (sc) {
+ USB_WakeUpCfg(TRUE);
+ USB_DeviceStatus |= USB_GETSTATUS_REMOTE_WAKEUP;
+ } else {
+ USB_WakeUpCfg(FALSE);
+ USB_DeviceStatus &= ~USB_GETSTATUS_REMOTE_WAKEUP;
+ }
+ } else {
+ return (FALSE);
+ }
+ break;
+ case REQUEST_TO_INTERFACE:
+ return (FALSE);
+ case REQUEST_TO_ENDPOINT:
+ n = SetupPacket.wIndex.WB.L & 0x8F;
+ m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);
+ if ((USB_Configuration != 0) && ((n & 0x0F) != 0) && (USB_EndPointMask & m)) {
+ if (SetupPacket.wValue.W == USB_FEATURE_ENDPOINT_STALL) {
+ if (sc) {
+ USB_SetStallEP(n);
+ USB_EndPointHalt |= m;
+ } else {
+ if ((USB_EndPointStall & m) != 0) {
+ return (TRUE);
+ }
+ USB_ClrStallEP(n);
+#if (USB_MSC)
+ if ((n == MSC_EP_IN) && ((USB_EndPointHalt & m) != 0)) {
+ /* Compliance Test: rewrite CSW after unstall */
+ if (CSW.dSignature == MSC_CSW_Signature) {
+ USB_WriteEP(MSC_EP_IN, (uint8_t *)&CSW, sizeof(CSW));
+ }
+ }
+#endif
+ USB_EndPointHalt &= ~m;
+ }
+ } else {
+ return (FALSE);
+ }
+ } else {
+ return (FALSE);
+ }
+ break;
+ default:
+ return (FALSE);
+ }
+ return (TRUE);
+}
+
+
+/*
+ * Set Address USB Request
+ * Parameters: None (global SetupPacket)
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+#if defined ( __IAR_SYSTEMS_ICC__ )
+inline uint32_t USB_ReqSetAddress (void) {
+#else
+__inline uint32_t USB_ReqSetAddress (void) {
+#endif
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+ case REQUEST_TO_DEVICE:
+ USB_DeviceAddress = 0x80 | SetupPacket.wValue.WB.L;
+ break;
+ default:
+ return (FALSE);
+ }
+ return (TRUE);
+}
+
+
+/*
+ * Get Descriptor USB Request
+ * Parameters: None (global SetupPacket)
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+#if defined ( __IAR_SYSTEMS_ICC__ )
+inline uint32_t USB_ReqGetDescriptor (void) {
+#else
+__inline uint32_t USB_ReqGetDescriptor (void) {
+#endif
+ uint8_t *pD;
+ uint32_t len, n;
+
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+ case REQUEST_TO_DEVICE:
+ switch (SetupPacket.wValue.WB.H) {
+ case USB_DEVICE_DESCRIPTOR_TYPE:
+ EP0Data.pData = (uint8_t *)USB_DeviceDescriptor;
+ len = USB_DEVICE_DESC_SIZE;
+ break;
+ case USB_CONFIGURATION_DESCRIPTOR_TYPE:
+ pD = (uint8_t *)USB_ConfigDescriptor;
+ for (n = 0; n != SetupPacket.wValue.WB.L; n++) {
+ if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bLength != 0) {
+ pD += ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;
+ }
+ }
+ if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bLength == 0) {
+ return (FALSE);
+ }
+ EP0Data.pData = pD;
+ len = ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;
+ break;
+ case USB_STRING_DESCRIPTOR_TYPE:
+ pD = (uint8_t *)USB_StringDescriptor;
+ for (n = 0; n != SetupPacket.wValue.WB.L; n++) {
+ if (((USB_STRING_DESCRIPTOR *)pD)->bLength != 0) {
+ pD += ((USB_STRING_DESCRIPTOR *)pD)->bLength;
+ }
+ }
+ if (((USB_STRING_DESCRIPTOR *)pD)->bLength == 0) {
+ return (FALSE);
+ }
+ EP0Data.pData = pD;
+ len = ((USB_STRING_DESCRIPTOR *)EP0Data.pData)->bLength;
+ break;
+ default:
+ return (FALSE);
+ }
+ break;
+ case REQUEST_TO_INTERFACE:
+ switch (SetupPacket.wValue.WB.H) {
+#if USB_HID
+ case HID_HID_DESCRIPTOR_TYPE:
+ if (SetupPacket.wIndex.WB.L != USB_HID_IF_NUM) {
+ return (FALSE); /* Only Single HID Interface is supported */
+ }
+ EP0Data.pData = (uint8_t *)USB_ConfigDescriptor + HID_DESC_OFFSET;
+ len = HID_DESC_SIZE;
+ break;
+ case HID_REPORT_DESCRIPTOR_TYPE:
+ if (SetupPacket.wIndex.WB.L != USB_HID_IF_NUM) {
+ return (FALSE); /* Only Single HID Interface is supported */
+ }
+ EP0Data.pData = (uint8_t *)HID_ReportDescriptor;
+ len = HID_ReportDescSize;
+ break;
+ case HID_PHYSICAL_DESCRIPTOR_TYPE:
+ return (FALSE); /* HID Physical Descriptor is not supported */
+#endif
+ default:
+ return (FALSE);
+ }
+// break;
+ default:
+ return (FALSE);
+ }
+
+ if (EP0Data.Count > len) {
+ EP0Data.Count = len;
+ }
+
+ return (TRUE);
+}
+
+
+/*
+ * Get Configuration USB Request
+ * Parameters: None (global SetupPacket)
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+#if defined ( __IAR_SYSTEMS_ICC__ )
+inline uint32_t USB_ReqGetConfiguration (void) {
+#else
+__inline uint32_t USB_ReqGetConfiguration (void) {
+#endif
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+ case REQUEST_TO_DEVICE:
+ EP0Data.pData = &USB_Configuration;
+ break;
+ default:
+ return (FALSE);
+ }
+ return (TRUE);
+}
+
+
+/*
+ * Set Configuration USB Request
+ * Parameters: None (global SetupPacket)
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+#if defined ( __IAR_SYSTEMS_ICC__ )
+inline uint32_t USB_ReqSetConfiguration (void) {
+#else
+__inline uint32_t USB_ReqSetConfiguration (void) {
+#endif
+ USB_COMMON_DESCRIPTOR *pD;
+ uint32_t alt = 0;
+ uint32_t n, m;
+ uint32_t tmp;
+
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+ case REQUEST_TO_DEVICE:
+
+ if (SetupPacket.wValue.WB.L) {
+ pD = (USB_COMMON_DESCRIPTOR *)USB_ConfigDescriptor;
+ while (pD->bLength) {
+ switch (pD->bDescriptorType) {
+ case USB_CONFIGURATION_DESCRIPTOR_TYPE:
+ if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bConfigurationValue == SetupPacket.wValue.WB.L) {
+ USB_Configuration = SetupPacket.wValue.WB.L;
+ USB_NumInterfaces = ((USB_CONFIGURATION_DESCRIPTOR *)pD)->bNumInterfaces;
+ for (n = 0; n < USB_IF_NUM; n++) {
+ USB_AltSetting[n] = 0;
+ }
+ for (n = 1; n < 16; n++) {
+ if (USB_EndPointMask & (1 << n)) {
+ USB_DisableEP(n);
+ }
+ if (USB_EndPointMask & ((1 << 16) << n)) {
+ USB_DisableEP(n | 0x80);
+ }
+ }
+ USB_EndPointMask = 0x00010001;
+ USB_EndPointHalt = 0x00000000;
+ USB_EndPointStall= 0x00000000;
+ USB_Configure(TRUE);
+ if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bmAttributes & USB_CONFIG_POWERED_MASK) {
+ USB_DeviceStatus |= USB_GETSTATUS_SELF_POWERED;
+ } else {
+ USB_DeviceStatus &= ~USB_GETSTATUS_SELF_POWERED;
+ }
+ } else {
+// (uint8_t *)pD += ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;
+ tmp = (uint32_t)pD;
+ tmp += ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;
+ pD = (USB_COMMON_DESCRIPTOR *)tmp;
+ continue;
+ }
+ break;
+ case USB_INTERFACE_DESCRIPTOR_TYPE:
+ alt = ((USB_INTERFACE_DESCRIPTOR *)pD)->bAlternateSetting;
+ break;
+ case USB_ENDPOINT_DESCRIPTOR_TYPE:
+ if (alt == 0) {
+ n = ((USB_ENDPOINT_DESCRIPTOR *)pD)->bEndpointAddress & 0x8F;
+ m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);
+ USB_EndPointMask |= m;
+ USB_ConfigEP((USB_ENDPOINT_DESCRIPTOR *)pD);
+ USB_EnableEP(n);
+ USB_ResetEP(n);
+ }
+ break;
+ }
+// (uint8_t *)pD += pD->bLength;
+ tmp = (uint32_t)pD;
+ tmp += pD->bLength;
+ pD = (USB_COMMON_DESCRIPTOR *)tmp;
+ }
+ }
+ else {
+ USB_Configuration = 0;
+ for (n = 1; n < 16; n++) {
+ if (USB_EndPointMask & (1 << n)) {
+ USB_DisableEP(n);
+ }
+ if (USB_EndPointMask & ((1 << 16) << n)) {
+ USB_DisableEP(n | 0x80);
+ }
+ }
+ USB_EndPointMask = 0x00010001;
+ USB_EndPointHalt = 0x00000000;
+ USB_EndPointStall = 0x00000000;
+ USB_Configure(FALSE);
+ }
+
+ if (USB_Configuration != SetupPacket.wValue.WB.L) {
+ return (FALSE);
+ }
+ break;
+ default:
+ return (FALSE);
+ }
+ return (TRUE);
+}
+
+
+/*
+ * Get Interface USB Request
+ * Parameters: None (global SetupPacket)
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+#if defined ( __IAR_SYSTEMS_ICC__ )
+inline uint32_t USB_ReqGetInterface (void) {
+#else
+__inline uint32_t USB_ReqGetInterface (void) {
+#endif
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+ case REQUEST_TO_INTERFACE:
+ if ((USB_Configuration != 0) && (SetupPacket.wIndex.WB.L < USB_NumInterfaces)) {
+ EP0Data.pData = USB_AltSetting + SetupPacket.wIndex.WB.L;
+ } else {
+ return (FALSE);
+ }
+ break;
+ default:
+ return (FALSE);
+ }
+ return (TRUE);
+}
+
+
+/*
+ * Set Interface USB Request
+ * Parameters: None (global SetupPacket)
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+#if defined ( __IAR_SYSTEMS_ICC__ )
+inline uint32_t USB_ReqSetInterface (void) {
+#else
+__inline uint32_t USB_ReqSetInterface (void) {
+#endif
+ USB_COMMON_DESCRIPTOR *pD;
+ uint32_t ifn = 0, alt = 0, old = 0, msk = 0;
+ uint32_t n, m;
+ uint32_t set;
+ uint32_t tmp;
+
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+ case REQUEST_TO_INTERFACE:
+ if (USB_Configuration == 0) return (FALSE);
+ set = FALSE;
+ pD = (USB_COMMON_DESCRIPTOR *)USB_ConfigDescriptor;
+ while (pD->bLength) {
+ switch (pD->bDescriptorType) {
+ case USB_CONFIGURATION_DESCRIPTOR_TYPE:
+ if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bConfigurationValue != USB_Configuration) {
+// (uint8_t *)pD += ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;
+ tmp = (uint32_t)pD;
+ tmp += ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;
+ pD = (USB_COMMON_DESCRIPTOR *)tmp;
+
+ continue;
+ }
+ break;
+ case USB_INTERFACE_DESCRIPTOR_TYPE:
+ ifn = ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber;
+ alt = ((USB_INTERFACE_DESCRIPTOR *)pD)->bAlternateSetting;
+ msk = 0;
+ if ((ifn == SetupPacket.wIndex.WB.L) && (alt == SetupPacket.wValue.WB.L)) {
+ set = TRUE;
+ old = USB_AltSetting[ifn];
+ USB_AltSetting[ifn] = (uint8_t)alt;
+ }
+ break;
+ case USB_ENDPOINT_DESCRIPTOR_TYPE:
+ if (ifn == SetupPacket.wIndex.WB.L) {
+ n = ((USB_ENDPOINT_DESCRIPTOR *)pD)->bEndpointAddress & 0x8F;
+ m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);
+ if (alt == SetupPacket.wValue.WB.L) {
+ USB_EndPointMask |= m;
+ USB_EndPointHalt &= ~m;
+ USB_ConfigEP((USB_ENDPOINT_DESCRIPTOR *)pD);
+ USB_EnableEP(n);
+ USB_ResetEP(n);
+ msk |= m;
+ }
+ else if ((alt == old) && ((msk & m) == 0)) {
+ USB_EndPointMask &= ~m;
+ USB_EndPointHalt &= ~m;
+ USB_DisableEP(n);
+ }
+ }
+ break;
+ }
+// (uint8_t *)pD += pD->bLength;
+ tmp = (uint32_t)pD;
+ tmp += pD->bLength;
+ pD = (USB_COMMON_DESCRIPTOR *)tmp;
+ }
+ break;
+ default:
+ return (FALSE);
+ }
+
+ return (set);
+}
+
+
+/*
+ * USB Endpoint 0 Event Callback
+ * Parameters: event
+ * Return Value: none
+ */
+
+void USB_EndPoint0 (uint32_t event) {
+
+ switch (event) {
+ case USB_EVT_SETUP:
+ USB_SetupStage();
+ USB_DirCtrlEP(SetupPacket.bmRequestType.BM.Dir);
+ EP0Data.Count = SetupPacket.wLength; /* Number of bytes to transfer */
+ switch (SetupPacket.bmRequestType.BM.Type) {
+
+ case REQUEST_STANDARD:
+ switch (SetupPacket.bRequest) {
+ case USB_REQUEST_GET_STATUS:
+ if (!USB_ReqGetStatus()) {
+ goto stall_i;
+ }
+ USB_DataInStage();
+ break;
+
+ case USB_REQUEST_CLEAR_FEATURE:
+ if (!USB_ReqSetClrFeature(0)) {
+ goto stall_i;
+ }
+ USB_StatusInStage();
+#if USB_FEATURE_EVENT
+ USB_Feature_Event();
+#endif
+ break;
+
+ case USB_REQUEST_SET_FEATURE:
+ if (!USB_ReqSetClrFeature(1)) {
+ goto stall_i;
+ }
+ USB_StatusInStage();
+#if USB_FEATURE_EVENT
+ USB_Feature_Event();
+#endif
+ break;
+
+ case USB_REQUEST_SET_ADDRESS:
+ if (!USB_ReqSetAddress()) {
+ goto stall_i;
+ }
+ USB_StatusInStage();
+ break;
+
+ case USB_REQUEST_GET_DESCRIPTOR:
+ if (!USB_ReqGetDescriptor()) {
+ goto stall_i;
+ }
+ USB_DataInStage();
+ break;
+
+ case USB_REQUEST_SET_DESCRIPTOR:
+/*stall_o:*/ USB_SetStallEP(0x00); /* not supported */
+ EP0Data.Count = 0;
+ break;
+
+ case USB_REQUEST_GET_CONFIGURATION:
+ if (!USB_ReqGetConfiguration()) {
+ goto stall_i;
+ }
+ USB_DataInStage();
+ break;
+
+ case USB_REQUEST_SET_CONFIGURATION:
+ if (!USB_ReqSetConfiguration()) {
+ goto stall_i;
+ }
+ USB_StatusInStage();
+#if USB_CONFIGURE_EVENT
+ USB_Configure_Event();
+#endif
+ break;
+
+ case USB_REQUEST_GET_INTERFACE:
+ if (!USB_ReqGetInterface()) {
+ goto stall_i;
+ }
+ USB_DataInStage();
+ break;
+
+ case USB_REQUEST_SET_INTERFACE:
+ if (!USB_ReqSetInterface()) {
+ goto stall_i;
+ }
+ USB_StatusInStage();
+#if USB_INTERFACE_EVENT
+ USB_Interface_Event();
+#endif
+ break;
+
+ default:
+ goto stall_i;
+ }
+ break; /* end case REQUEST_STANDARD */
+
+#if USB_CLASS
+ case REQUEST_CLASS:
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+
+ case REQUEST_TO_DEVICE:
+ goto stall_i; /* not supported */
+
+ case REQUEST_TO_INTERFACE:
+#if USB_HID
+ if (SetupPacket.wIndex.WB.L == USB_HID_IF_NUM) { /* IF number correct? */
+ switch (SetupPacket.bRequest) {
+ case HID_REQUEST_GET_REPORT:
+ if (HID_GetReport()) {
+ EP0Data.pData = EP0Buf; /* point to data to be sent */
+ USB_DataInStage(); /* send requested data */
+ goto setup_class_ok;
+ }
+ break;
+ case HID_REQUEST_SET_REPORT:
+ EP0Data.pData = EP0Buf; /* data to be received */
+ goto setup_class_ok;
+ case HID_REQUEST_GET_IDLE:
+ if (HID_GetIdle()) {
+ EP0Data.pData = EP0Buf; /* point to data to be sent */
+ USB_DataInStage(); /* send requested data */
+ goto setup_class_ok;
+ }
+ break;
+ case HID_REQUEST_SET_IDLE:
+ if (HID_SetIdle()) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto setup_class_ok;
+ }
+ break;
+ case HID_REQUEST_GET_PROTOCOL:
+ if (HID_GetProtocol()) {
+ EP0Data.pData = EP0Buf; /* point to data to be sent */
+ USB_DataInStage(); /* send requested data */
+ goto setup_class_ok;
+ }
+ break;
+ case HID_REQUEST_SET_PROTOCOL:
+ if (HID_SetProtocol()) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto setup_class_ok;
+ }
+ break;
+ }
+ }
+#endif /* USB_HID */
+#if USB_MSC
+ if (SetupPacket.wIndex.WB.L == USB_MSC_IF_NUM) { /* IF number correct? */
+ switch (SetupPacket.bRequest) {
+ case MSC_REQUEST_RESET:
+ if ((SetupPacket.wValue.W == 0) && /* RESET with invalid parameters -> STALL */
+ (SetupPacket.wLength == 0)) {
+ if (MSC_Reset()) {
+ USB_StatusInStage();
+ goto setup_class_ok;
+ }
+ }
+ break;
+ case MSC_REQUEST_GET_MAX_LUN:
+ if ((SetupPacket.wValue.W == 0) && /* GET_MAX_LUN with invalid parameters -> STALL */
+ (SetupPacket.wLength == 1)) {
+ if (MSC_GetMaxLUN()) {
+ EP0Data.pData = EP0Buf;
+ USB_DataInStage();
+ goto setup_class_ok;
+ }
+ }
+ break;
+ }
+ }
+#endif /* USB_MSC */
+#if USB_AUDIO
+ if ((SetupPacket.wIndex.WB.L == USB_ADC_CIF_NUM) || /* IF number correct? */
+ (SetupPacket.wIndex.WB.L == USB_ADC_SIF1_NUM) ||
+ (SetupPacket.wIndex.WB.L == USB_ADC_SIF2_NUM)) {
+ switch (SetupPacket.bRequest) {
+ case AUDIO_REQUEST_GET_CUR:
+ case AUDIO_REQUEST_GET_MIN:
+ case AUDIO_REQUEST_GET_MAX:
+ case AUDIO_REQUEST_GET_RES:
+ if (ADC_IF_GetRequest()) {
+ EP0Data.pData = EP0Buf; /* point to data to be sent */
+ USB_DataInStage(); /* send requested data */
+ goto setup_class_ok;
+ }
+ break;
+ case AUDIO_REQUEST_SET_CUR:
+// case AUDIO_REQUEST_SET_MIN:
+// case AUDIO_REQUEST_SET_MAX:
+// case AUDIO_REQUEST_SET_RES:
+ EP0Data.pData = EP0Buf; /* data to be received */
+ goto setup_class_ok;
+ }
+ }
+#endif /* USB_AUDIO */
+#if USB_CDC
+ if ((SetupPacket.wIndex.WB.L == USB_CDC_CIF_NUM) || /* IF number correct? */
+ (SetupPacket.wIndex.WB.L == USB_CDC_DIF_NUM)) {
+ switch (SetupPacket.bRequest) {
+ case CDC_SEND_ENCAPSULATED_COMMAND:
+ EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */
+ goto setup_class_ok;
+ case CDC_GET_ENCAPSULATED_RESPONSE:
+ if (CDC_GetEncapsulatedResponse()) {
+ EP0Data.pData = EP0Buf; /* point to data to be sent */
+ USB_DataInStage(); /* send requested data */
+ goto setup_class_ok;
+ }
+ break;
+ case CDC_SET_COMM_FEATURE:
+ EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */
+ goto setup_class_ok;
+ case CDC_GET_COMM_FEATURE:
+ if (CDC_GetCommFeature(SetupPacket.wValue.W)) {
+ EP0Data.pData = EP0Buf; /* point to data to be sent */
+ USB_DataInStage(); /* send requested data */
+ goto setup_class_ok;
+ }
+ break;
+ case CDC_CLEAR_COMM_FEATURE:
+ if (CDC_ClearCommFeature(SetupPacket.wValue.W)) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto setup_class_ok;
+ }
+ break;
+ case CDC_SET_LINE_CODING:
+ EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */
+ goto setup_class_ok;
+ case CDC_GET_LINE_CODING:
+ if (CDC_GetLineCoding()) {
+ EP0Data.pData = EP0Buf; /* point to data to be sent */
+ USB_DataInStage(); /* send requested data */
+ goto setup_class_ok;
+ }
+ break;
+ case CDC_SET_CONTROL_LINE_STATE:
+ if (CDC_SetControlLineState(SetupPacket.wValue.W)) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto setup_class_ok;
+ }
+ break;
+ case CDC_SEND_BREAK:
+ if (CDC_SendBreak(SetupPacket.wValue.W)) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto setup_class_ok;
+ }
+ break;
+ }
+ }
+#endif /* USB_CDC */
+ goto stall_i; /* not supported */
+ /* end case REQUEST_TO_INTERFACE */
+
+ case REQUEST_TO_ENDPOINT:
+#if USB_AUDIO
+ switch (SetupPacket.bRequest) {
+ case AUDIO_REQUEST_GET_CUR:
+ case AUDIO_REQUEST_GET_MIN:
+ case AUDIO_REQUEST_GET_MAX:
+ case AUDIO_REQUEST_GET_RES:
+ if (ADC_EP_GetRequest()) {
+ EP0Data.pData = EP0Buf; /* point to data to be sent */
+ USB_DataInStage(); /* send requested data */
+ goto setup_class_ok;
+ }
+ break;
+ case AUDIO_REQUEST_SET_CUR:
+// case AUDIO_REQUEST_SET_MIN:
+// case AUDIO_REQUEST_SET_MAX:
+// case AUDIO_REQUEST_SET_RES:
+ EP0Data.pData = EP0Buf; /* data to be received */
+ goto setup_class_ok;
+ }
+#endif /* USB_AUDIO */
+ goto stall_i;
+ /* end case REQUEST_TO_ENDPOINT */
+
+ default:
+ goto stall_i;
+ }
+setup_class_ok: /* request finished successfully */
+ break; /* end case REQUEST_CLASS */
+#endif /* USB_CLASS */
+
+#if USB_VENDOR
+ case REQUEST_VENDOR:
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+
+ case REQUEST_TO_DEVICE:
+ if (!USB_ReqVendorDev(TRUE)) {
+ goto stall_i; /* not supported */
+ }
+ break;
+
+ case REQUEST_TO_INTERFACE:
+ if (!USB_ReqVendorIF(TRUE)) {
+ goto stall_i; /* not supported */
+ }
+ break;
+
+ case REQUEST_TO_ENDPOINT:
+ if (!USB_ReqVendorEP(TRUE)) {
+ goto stall_i; /* not supported */
+ }
+ break;
+
+ default:
+ goto stall_i;
+ }
+
+ if (SetupPacket.wLength) {
+ if (SetupPacket.bmRequestType.BM.Dir == REQUEST_DEVICE_TO_HOST) {
+ USB_DataInStage();
+ }
+ } else {
+ USB_StatusInStage();
+ }
+
+ break; /* end case REQUEST_VENDOR */
+#endif /* USB_VENDOR */
+
+ default:
+stall_i: USB_SetStallEP(0x80);
+ EP0Data.Count = 0;
+ break;
+ }
+ break; /* end case USB_EVT_SETUP */
+
+ case USB_EVT_OUT:
+ if (SetupPacket.bmRequestType.BM.Dir == REQUEST_HOST_TO_DEVICE) {
+ if (EP0Data.Count) { /* still data to receive ? */
+ USB_DataOutStage(); /* receive data */
+ if (EP0Data.Count == 0) { /* data complete ? */
+ switch (SetupPacket.bmRequestType.BM.Type) {
+
+ case REQUEST_STANDARD:
+ goto stall_i; /* not supported */
+
+#if (USB_CLASS)
+ case REQUEST_CLASS:
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+ case REQUEST_TO_DEVICE:
+ goto stall_i; /* not supported */
+
+ case REQUEST_TO_INTERFACE:
+#if USB_HID
+ if (SetupPacket.wIndex.WB.L == USB_HID_IF_NUM) { /* IF number correct? */
+ switch (SetupPacket.bRequest) {
+ case HID_REQUEST_SET_REPORT:
+ if (HID_SetReport()) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto out_class_ok;
+ }
+ break;
+ }
+ }
+#endif /* USB_HID */
+#if USB_AUDIO
+ if ((SetupPacket.wIndex.WB.L == USB_ADC_CIF_NUM) || /* IF number correct? */
+ (SetupPacket.wIndex.WB.L == USB_ADC_SIF1_NUM) ||
+ (SetupPacket.wIndex.WB.L == USB_ADC_SIF2_NUM)) {
+ switch (SetupPacket.bRequest) {
+ case AUDIO_REQUEST_SET_CUR:
+// case AUDIO_REQUEST_SET_MIN:
+// case AUDIO_REQUEST_SET_MAX:
+// case AUDIO_REQUEST_SET_RES:
+ if (ADC_IF_SetRequest()) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto out_class_ok;
+ }
+ break;
+ }
+ }
+#endif /* USB_AUDIO */
+#if USB_CDC
+ if ((SetupPacket.wIndex.WB.L == USB_CDC_CIF_NUM) || /* IF number correct? */
+ (SetupPacket.wIndex.WB.L == USB_CDC_DIF_NUM)) {
+ switch (SetupPacket.bRequest) {
+ case CDC_SEND_ENCAPSULATED_COMMAND:
+ if (CDC_SendEncapsulatedCommand()) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto out_class_ok;
+ }
+ break;
+ case CDC_SET_COMM_FEATURE:
+ if (CDC_SetCommFeature(SetupPacket.wValue.W)) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto out_class_ok;
+ }
+ break;
+ case CDC_SET_LINE_CODING:
+ if (CDC_SetLineCoding()) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto out_class_ok;
+ }
+ break;
+ }
+ }
+#endif /* USB_CDC */
+ goto stall_i;
+ /* end case REQUEST_TO_INTERFACE */
+
+ case REQUEST_TO_ENDPOINT:
+#if USB_AUDIO
+ switch (SetupPacket.bRequest) {
+ case AUDIO_REQUEST_SET_CUR:
+// case AUDIO_REQUEST_SET_MIN:
+// case AUDIO_REQUEST_SET_MAX:
+// case AUDIO_REQUEST_SET_RES:
+ if (ADC_EP_SetRequest()) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto out_class_ok;
+ }
+ break;
+ }
+#endif /* USB_AUDIO */
+ goto stall_i;
+ /* end case REQUEST_TO_ENDPOINT */
+
+ default:
+ goto stall_i;
+ }
+out_class_ok: /* request finished successfully */
+ break; /* end case REQUEST_CLASS */
+#endif /* USB_CLASS */
+
+#if USB_VENDOR
+ case REQUEST_VENDOR:
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+
+ case REQUEST_TO_DEVICE:
+ if (!USB_ReqVendorDev(FALSE)) {
+ goto stall_i; /* not supported */
+ }
+ break;
+
+ case REQUEST_TO_INTERFACE:
+ if (!USB_ReqVendorIF(FALSE)) {
+ goto stall_i; /* not supported */
+ }
+ break;
+
+ case REQUEST_TO_ENDPOINT:
+ if (!USB_ReqVendorEP(FALSE)) {
+ goto stall_i; /* not supported */
+ }
+ break;
+
+ default:
+ goto stall_i;
+ }
+
+ USB_StatusInStage();
+
+ break; /* end case REQUEST_VENDOR */
+#endif /* USB_VENDOR */
+
+ default:
+ goto stall_i;
+ }
+ }
+ }
+ } else {
+ USB_StatusOutStage(); /* receive Acknowledge */
+ }
+ break; /* end case USB_EVT_OUT */
+
+ case USB_EVT_IN :
+ if (SetupPacket.bmRequestType.BM.Dir == REQUEST_DEVICE_TO_HOST) {
+ USB_DataInStage(); /* send data */
+ } else {
+ if (USB_DeviceAddress & 0x80) {
+ USB_DeviceAddress &= 0x7F;
+ USB_SetAddress(USB_DeviceAddress);
+ }
+ }
+ break; /* end case USB_EVT_IN */
+
+ case USB_EVT_OUT_STALL:
+ USB_ClrStallEP(0x00);
+ break;
+
+ case USB_EVT_IN_STALL:
+ USB_ClrStallEP(0x80);
+ break;
+
+ }
+}
-/*----------------------------------------------------------------------------\r
- * U S B - K e r n e l\r
- *----------------------------------------------------------------------------\r
- * Name: usbcore.h\r
- * Purpose: USB Core Definitions\r
- * Version: V1.20\r
- *----------------------------------------------------------------------------\r
- * This software is supplied "AS IS" without any warranties, express,\r
- * implied or statutory, including but not limited to the implied\r
- * warranties of fitness for purpose, satisfactory quality and\r
- * noninfringement. Keil extends you a royalty-free right to reproduce\r
- * and distribute executable files created using this software for use\r
- * on NXP Semiconductors LPC microcontroller devices only. Nothing else \r
- * gives you the right to use this software.\r
- *\r
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
- *---------------------------------------------------------------------------*/\r
-\r
-#ifndef __USBCORE_H__\r
-#define __USBCORE_H__\r
-\r
-\r
-/* USB Endpoint Data Structure */\r
-typedef struct _USB_EP_DATA {\r
- uint8_t *pData;\r
- uint16_t Count;\r
-} USB_EP_DATA;\r
-\r
-/* USB Core Global Variables */\r
-extern uint16_t USB_DeviceStatus;\r
-extern uint8_t USB_DeviceAddress;\r
-extern uint8_t USB_Configuration;\r
-extern uint32_t USB_EndPointMask;\r
-extern uint32_t USB_EndPointHalt;\r
-extern uint32_t USB_EndPointStall;\r
-extern uint8_t USB_AltSetting[USB_IF_NUM];\r
-\r
-/* USB Endpoint 0 Buffer */\r
-extern uint8_t EP0Buf[USB_MAX_PACKET0];\r
-\r
-/* USB Endpoint 0 Data Info */\r
-extern USB_EP_DATA EP0Data;\r
-\r
-/* USB Setup Packet */\r
-extern USB_SETUP_PACKET SetupPacket;\r
-\r
-/* USB Core Functions */\r
-extern void USB_ResetCore (void);\r
-\r
-\r
-\r
-#endif /* __USBCORE_H__ */\r
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: usbcore.h
+ * Purpose: USB Core Definitions
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC microcontroller devices only. Nothing else
+ * gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#ifndef __USBCORE_H__
+#define __USBCORE_H__
+
+
+/* USB Endpoint Data Structure */
+typedef struct _USB_EP_DATA {
+ uint8_t *pData;
+ uint16_t Count;
+} USB_EP_DATA;
+
+/* USB Core Global Variables */
+extern uint16_t USB_DeviceStatus;
+extern uint8_t USB_DeviceAddress;
+extern uint8_t USB_Configuration;
+extern uint32_t USB_EndPointMask;
+extern uint32_t USB_EndPointHalt;
+extern uint32_t USB_EndPointStall;
+extern uint8_t USB_AltSetting[USB_IF_NUM];
+
+/* USB Endpoint 0 Buffer */
+extern uint8_t EP0Buf[USB_MAX_PACKET0];
+
+/* USB Endpoint 0 Data Info */
+extern USB_EP_DATA EP0Data;
+
+/* USB Setup Packet */
+extern USB_SETUP_PACKET SetupPacket;
+
+/* USB Core Functions */
+extern void USB_ResetCore (void);
+
+
+
+#endif /* __USBCORE_H__ */
-/*----------------------------------------------------------------------------\r
- * U S B - K e r n e l\r
- *----------------------------------------------------------------------------\r
- * Name: usbdesc.c\r
- * Purpose: USB Descriptors\r
- * Version: V1.20\r
- *----------------------------------------------------------------------------\r
- * This software is supplied "AS IS" without any warranties, express,\r
- * implied or statutory, including but not limited to the implied\r
- * warranties of fitness for purpose, satisfactory quality and\r
- * noninfringement. Keil extends you a royalty-free right to reproduce\r
- * and distribute executable files created using this software for use\r
- * on NXP Semiconductors LPC microcontroller devices only. Nothing else\r
- * gives you the right to use this software.\r
- *\r
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
- *----------------------------------------------------------------------------\r
- * History:\r
- * V1.20 Changed string descriptor handling\r
- * V1.00 Initial Version\r
- *---------------------------------------------------------------------------*/\r
-#include "lpc_types.h"\r
-#include "usb.h"\r
-#include "cdc.h"\r
-#include "usbcfg.h"\r
-#include "usbdesc.h"\r
-\r
-\r
-/* USB Standard Device Descriptor */\r
-const uint8_t USB_DeviceDescriptor[] = {\r
- USB_DEVICE_DESC_SIZE, /* bLength */\r
- USB_DEVICE_DESCRIPTOR_TYPE, /* bDescriptorType */\r
- WBVAL(0x0200), /* 2.0 */ /* bcdUSB */\r
- USB_DEVICE_CLASS_COMMUNICATIONS, /* bDeviceClass CDC*/\r
- 0x00, /* bDeviceSubClass */\r
- 0x00, /* bDeviceProtocol */\r
- USB_MAX_PACKET0, /* bMaxPacketSize0 */\r
- WBVAL(0x1FC9), /* idVendor */\r
- WBVAL(0x2002), /* idProduct */\r
- WBVAL(0x0100), /* 1.00 */ /* bcdDevice */\r
- 0x01, /* iManufacturer */\r
- 0x02, /* iProduct */\r
- 0x03, /* iSerialNumber */\r
- 0x01 /* bNumConfigurations: one possible configuration*/\r
-};\r
-\r
-/* USB Configuration Descriptor */\r
-/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */\r
-const uint8_t USB_ConfigDescriptor[] = {\r
-/* Configuration 1 */\r
- USB_CONFIGUARTION_DESC_SIZE, /* bLength */\r
- USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */\r
- WBVAL( /* wTotalLength */\r
- 1*USB_CONFIGUARTION_DESC_SIZE +\r
- 1*USB_INTERFACE_DESC_SIZE + /* communication interface */\r
- 0x0013 + /* CDC functions */\r
- 1*USB_ENDPOINT_DESC_SIZE + /* interrupt endpoint */\r
- 1*USB_INTERFACE_DESC_SIZE + /* data interface */\r
- 2*USB_ENDPOINT_DESC_SIZE /* bulk endpoints */\r
- ),\r
- 0x02, /* bNumInterfaces */\r
- 0x01, /* bConfigurationValue: 0x01 is used to select this configuration */\r
- 0x00, /* iConfiguration: no string to describe this configuration */\r
- USB_CONFIG_BUS_POWERED /*|*/ /* bmAttributes */\r
-/*USB_CONFIG_REMOTE_WAKEUP*/,\r
- USB_CONFIG_POWER_MA(100), /* bMaxPower, device power consumption is 100 mA */\r
-/* Interface 0, Alternate Setting 0, Communication class interface descriptor */\r
- USB_INTERFACE_DESC_SIZE, /* bLength */\r
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */\r
- USB_CDC_CIF_NUM, /* bInterfaceNumber: Number of Interface */\r
- 0x00, /* bAlternateSetting: Alternate setting */\r
- 0x01, /* bNumEndpoints: One endpoint used */\r
- CDC_COMMUNICATION_INTERFACE_CLASS, /* bInterfaceClass: Communication Interface Class */\r
- CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass: Abstract Control Model */\r
- 0x00, /* bInterfaceProtocol: no protocol used */\r
- 0x5E, /* iInterface: */\r
-/*Header Functional Descriptor*/\r
- 0x05, /* bLength: Endpoint Descriptor size */\r
- CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */\r
- CDC_HEADER, /* bDescriptorSubtype: Header Func Desc */\r
- WBVAL(CDC_V1_10), /* 1.10 */ /* bcdCDC */\r
-/*Call Management Functional Descriptor*/\r
- 0x05, /* bFunctionLength */\r
- CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */\r
- CDC_CALL_MANAGEMENT, /* bDescriptorSubtype: Call Management Func Desc */\r
- 0x01, /* bmCapabilities: device handles call management */\r
- 0x01, /* bDataInterface: CDC data IF ID */\r
-/*Abstract Control Management Functional Descriptor*/\r
- 0x04, /* bFunctionLength */\r
- CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */\r
- CDC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype: Abstract Control Management desc */\r
- 0x02, /* bmCapabilities: SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported */\r
-/*Union Functional Descriptor*/\r
- 0x05, /* bFunctionLength */\r
- CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */\r
- CDC_UNION, /* bDescriptorSubtype: Union func desc */\r
- USB_CDC_CIF_NUM, /* bMasterInterface: Communication class interface is master */\r
- USB_CDC_DIF_NUM, /* bSlaveInterface0: Data class interface is slave 0 */\r
-/*Endpoint 1 Descriptor*/ /* event notification (optional) */\r
- USB_ENDPOINT_DESC_SIZE, /* bLength */\r
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */\r
- USB_ENDPOINT_IN(1), /* bEndpointAddress */\r
- USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */\r
- WBVAL(0x0010), /* wMaxPacketSize */\r
- 0x02, /* 2ms */ /* bInterval */\r
-/* Interface 1, Alternate Setting 0, Data class interface descriptor*/\r
- USB_INTERFACE_DESC_SIZE, /* bLength */\r
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */\r
- USB_CDC_DIF_NUM, /* bInterfaceNumber: Number of Interface */\r
- 0x00, /* bAlternateSetting: no alternate setting */\r
- 0x02, /* bNumEndpoints: two endpoints used */\r
- CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass: Data Interface Class */\r
- 0x00, /* bInterfaceSubClass: no subclass available */\r
- 0x00, /* bInterfaceProtocol: no protocol used */\r
- 0x5E, /* iInterface: */\r
-/* Endpoint, EP2 Bulk Out */\r
- USB_ENDPOINT_DESC_SIZE, /* bLength */\r
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */\r
- USB_ENDPOINT_OUT(2), /* bEndpointAddress */\r
- USB_ENDPOINT_TYPE_BULK, /* bmAttributes */\r
- WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */\r
- 0x00, /* bInterval: ignore for Bulk transfer */\r
-/* Endpoint, EP2 Bulk In */\r
- USB_ENDPOINT_DESC_SIZE, /* bLength */\r
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */\r
- USB_ENDPOINT_IN(2), /* bEndpointAddress */\r
- USB_ENDPOINT_TYPE_BULK, /* bmAttributes */\r
- WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */\r
- 0x00, /* bInterval: ignore for Bulk transfer */\r
-/* Terminator */\r
- 0 /* bLength */\r
-};\r
-\r
-\r
-\r
-\r
-/* USB String Descriptor (optional) */\r
-const uint8_t USB_StringDescriptor[] = {\r
-/* Index 0x00: LANGID Codes */\r
- 0x04, /* bLength */\r
- USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */\r
- WBVAL(0x0409), /* US English */ /* wLANGID */\r
-/* Index 0x01: Manufacturer */\r
- (13*2 + 2), /* bLength (13 Char + Type + lenght) */\r
- USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */\r
- 'N',0,\r
- 'X',0,\r
- 'P',0,\r
- ' ',0,\r
- 'S',0,\r
- 'E',0,\r
- 'M',0,\r
- 'I',0,\r
- 'C',0,\r
- 'O',0,\r
- 'N',0,\r
- 'D',0,\r
- ' ',0,\r
-/* Index 0x02: Product */\r
- (17*2 + 2), /* bLength ( 17 Char + Type + lenght) */\r
- USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */\r
- 'N',0,\r
- 'X',0,\r
- 'P',0,\r
- ' ',0,\r
- 'L',0,\r
- 'P',0,\r
- 'C',0,\r
- '1',0,\r
- '7',0,\r
- 'x',0,\r
- 'x',0,\r
- ' ',0,\r
- 'V',0,\r
- 'C',0,\r
- 'O',0,\r
- 'M',0,\r
- ' ',0,\r
-/* Index 0x03: Serial Number */\r
- (12*2 + 2), /* bLength (12 Char + Type + lenght) */\r
- USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */\r
- 'D',0,\r
- 'E',0,\r
- 'M',0,\r
- 'O',0,\r
- '0',0,\r
- '0',0,\r
- '0',0,\r
- '0',0,\r
- '0',0,\r
- '0',0,\r
- '0',0,\r
- '0',0,\r
-/* Index 0x04: Interface 0, Alternate Setting 0 */\r
- ( 4*2 + 2), /* bLength (4 Char + Type + lenght) */\r
- USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */\r
- 'V',0,\r
- 'C',0,\r
- 'O',0,\r
- 'M',0,\r
-};\r
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: usbdesc.c
+ * Purpose: USB Descriptors
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC microcontroller devices only. Nothing else
+ * gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *----------------------------------------------------------------------------
+ * History:
+ * V1.20 Changed string descriptor handling
+ * V1.00 Initial Version
+ *---------------------------------------------------------------------------*/
+#include "lpc_types.h"
+#include "usb.h"
+#include "cdc.h"
+#include "cfg.h"
+#include "desc.h"
+
+
+/* USB Standard Device Descriptor */
+const uint8_t USB_DeviceDescriptor[] = {
+ USB_DEVICE_DESC_SIZE, /* bLength */
+ USB_DEVICE_DESCRIPTOR_TYPE, /* bDescriptorType */
+ WBVAL(0x0200), /* 2.0 */ /* bcdUSB */
+ USB_DEVICE_CLASS_COMMUNICATIONS, /* bDeviceClass CDC*/
+ 0x00, /* bDeviceSubClass */
+ 0x00, /* bDeviceProtocol */
+ USB_MAX_PACKET0, /* bMaxPacketSize0 */
+ WBVAL(0x1FC9), /* idVendor */
+ WBVAL(0x2002), /* idProduct */
+ WBVAL(0x0100), /* 1.00 */ /* bcdDevice */
+ 0x01, /* iManufacturer */
+ 0x02, /* iProduct */
+ 0x03, /* iSerialNumber */
+ 0x01 /* bNumConfigurations: one possible configuration*/
+};
+
+/* USB Configuration Descriptor */
+/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
+const uint8_t USB_ConfigDescriptor[] = {
+/* Configuration 1 */
+ USB_CONFIGUARTION_DESC_SIZE, + /* bLength */
+ USB_CONFIGURATION_DESCRIPTOR_TYPE, + /* bDescriptorType */
+ WBVAL( /* wTotalLength */
+ (USB_CONFIGUARTION_DESC_SIZE) +
+ (USB_INTERFACE_DESC_SIZE) + /* communication interface */
+ 0x0013 + /* CDC functions */
+ (USB_ENDPOINT_DESC_SIZE) + /* interrupt endpoint */
+ (USB_INTERFACE_DESC_SIZE) + /* data interface */
+ (2*USB_ENDPOINT_DESC_SIZE) /* bulk endpoints */
+ ),
+ 0x02, /* bNumInterfaces */
+ 0x01, /* bConfigurationValue: 0x01 is used to select this configuration */
+ 0x00, /* iConfiguration: no string to describe this configuration */
+ USB_CONFIG_BUS_POWERED /*|*/ /* bmAttributes */
+/*USB_CONFIG_REMOTE_WAKEUP*/,
+ USB_CONFIG_POWER_MA(100), /* bMaxPower, device power consumption is 100 mA */
+/* Interface 0, Alternate Setting 0, Communication class interface descriptor */
+ USB_INTERFACE_DESC_SIZE, /* bLength */
+ USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_CDC_CIF_NUM, /* bInterfaceNumber: Number of Interface */
+ 0x00, /* bAlternateSetting: Alternate setting */
+ 0x01, /* bNumEndpoints: One endpoint used */
+ CDC_COMMUNICATION_INTERFACE_CLASS, /* bInterfaceClass: Communication Interface Class */
+ CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass: Abstract Control Model */
+ 0x00, /* bInterfaceProtocol: no protocol used */
+ 0x5E, /* iInterface: */
+/*Header Functional Descriptor*/
+ 0x05, /* bLength: Endpoint Descriptor size */
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
+ CDC_HEADER, /* bDescriptorSubtype: Header Func Desc */
+ WBVAL(CDC_V1_10), /* 1.10 */ /* bcdCDC */
+/*Call Management Functional Descriptor*/
+ 0x05, /* bFunctionLength */
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
+ CDC_CALL_MANAGEMENT, /* bDescriptorSubtype: Call Management Func Desc */
+ 0x01, /* bmCapabilities: device handles call management */
+ 0x01, /* bDataInterface: CDC data IF ID */
+/*Abstract Control Management Functional Descriptor*/
+ 0x04, /* bFunctionLength */
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
+ CDC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype: Abstract Control Management desc */
+ 0x02, /* bmCapabilities: SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported */
+/*Union Functional Descriptor*/
+ 0x05, /* bFunctionLength */
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
+ CDC_UNION, /* bDescriptorSubtype: Union func desc */
+ USB_CDC_CIF_NUM, /* bMasterInterface: Communication class interface is master */
+ USB_CDC_DIF_NUM, /* bSlaveInterface0: Data class interface is slave 0 */
+/*Endpoint 1 Descriptor*/ /* event notification (optional) */
+ USB_ENDPOINT_DESC_SIZE, /* bLength */
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_ENDPOINT_IN(1), /* bEndpointAddress */
+ USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */
+ WBVAL(0x0010), /* wMaxPacketSize */
+ 0x02, /* 2ms */ /* bInterval */
+/* Interface 1, Alternate Setting 0, Data class interface descriptor*/
+ USB_INTERFACE_DESC_SIZE, /* bLength */
+ USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_CDC_DIF_NUM, /* bInterfaceNumber: Number of Interface */
+ 0x00, /* bAlternateSetting: no alternate setting */
+ 0x02, /* bNumEndpoints: two endpoints used */
+ CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass: Data Interface Class */
+ 0x00, /* bInterfaceSubClass: no subclass available */
+ 0x00, /* bInterfaceProtocol: no protocol used */
+ 0x5E, /* iInterface: */
+/* Endpoint, EP2 Bulk Out */
+ USB_ENDPOINT_DESC_SIZE, /* bLength */
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_ENDPOINT_OUT(2), /* bEndpointAddress */
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */
+ WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */
+ 0x00, /* bInterval: ignore for Bulk transfer */
+/* Endpoint, EP2 Bulk In */
+ USB_ENDPOINT_DESC_SIZE, /* bLength */
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_ENDPOINT_IN(2), /* bEndpointAddress */
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */
+ WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */
+ 0x00, /* bInterval: ignore for Bulk transfer */
+/* Terminator */
+ 0 /* bLength */
+};
+
+
+
+
+/* USB String Descriptor (optional) */
+const uint8_t USB_StringDescriptor[] = {
+/* Index 0x00: LANGID Codes */
+ 0x04, /* bLength */
+ USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
+ WBVAL(0x0409), /* US English */ /* wLANGID */
+/* Index 0x01: Manufacturer */
+ (7*2 + 2), /* bLength (13 Char + Type + lenght) */
+ USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
+ 'L',0,
+ 'a',0,
+ 'b',0,
+ 'i',0,
+ 't',0,
+ 'a',0,
+ 't',0,
+/* Index 0x02: Product */
+ (17*2 + 2), /* bLength ( 17 Char + Type + lenght) */
+ USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
+ 'R',0,
+ 'a',0,
+ 'p',0,
+ 'p',0,
+ 'e',0,
+ 'r',0,
+ ' ',0,
+ 'U',0,
+ 'S',0,
+ 'B',0,
+ ' ',0,
+ 'S',0,
+ 'e',0,
+ 'r',0,
+ 'i',0,
+ 'a',0,
+ 'l',0,
+/* Index 0x03: Serial Number */
+ (12*2 + 2), /* bLength (12 Char + Type + lenght) */
+ USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
+ 'P',0,
+ 'R',0,
+ 'O',0,
+ 'T',0,
+ 'O',0,
+ 'T',0,
+ 'Y',0,
+ 'P',0,
+ 'E',0,
+ ' ',0,
+ '4',0,
+ '2',0,
+/* Index 0x04: Interface 0, Alternate Setting 0 */
+ ( 4*2 + 2), /* bLength (4 Char + Type + lenght) */
+ USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
+ 'V',0,
+ 'C',0,
+ 'O',0,
+ 'M',0,
+};
-/*----------------------------------------------------------------------------\r
- * U S B - K e r n e l\r
- *----------------------------------------------------------------------------\r
- * Name: usbdesc.h\r
- * Purpose: USB Descriptors Definitions\r
- * Version: V1.20\r
- *----------------------------------------------------------------------------\r
- * This software is supplied "AS IS" without any warranties, express,\r
- * implied or statutory, including but not limited to the implied\r
- * warranties of fitness for purpose, satisfactory quality and\r
- * noninfringement. Keil extends you a royalty-free right to reproduce\r
- * and distribute executable files created using this software for use\r
- * on NXP Semiconductors LPC microcontroller devices only. Nothing else \r
- * gives you the right to use this software.\r
- *\r
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
- *---------------------------------------------------------------------------*/\r
-\r
-#ifndef __USBDESC_H__\r
-#define __USBDESC_H__\r
-\r
-\r
-#define WBVAL(x) (x & 0xFF),((x >> 8) & 0xFF)\r
-\r
-#define USB_DEVICE_DESC_SIZE (sizeof(USB_DEVICE_DESCRIPTOR))\r
-#define USB_CONFIGUARTION_DESC_SIZE (sizeof(USB_CONFIGURATION_DESCRIPTOR))\r
-#define USB_INTERFACE_DESC_SIZE (sizeof(USB_INTERFACE_DESCRIPTOR))\r
-#define USB_ENDPOINT_DESC_SIZE (sizeof(USB_ENDPOINT_DESCRIPTOR))\r
-\r
-extern const uint8_t USB_DeviceDescriptor[];\r
-extern const uint8_t USB_ConfigDescriptor[];\r
-extern const uint8_t USB_StringDescriptor[];\r
-\r
-\r
-#endif /* __USBDESC_H__ */\r
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: usbdesc.h
+ * Purpose: USB Descriptors Definitions
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC microcontroller devices only. Nothing else
+ * gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#ifndef __USBDESC_H__
+#define __USBDESC_H__
+
+
+#define WBVAL(x) ((x) & 0xFF),(((x) >> 8) & 0xFF)
+
+#define USB_DEVICE_DESC_SIZE (sizeof(USB_DEVICE_DESCRIPTOR))
+#define USB_CONFIGUARTION_DESC_SIZE (sizeof(USB_CONFIGURATION_DESCRIPTOR))
+#define USB_INTERFACE_DESC_SIZE (sizeof(USB_INTERFACE_DESCRIPTOR))
+#define USB_ENDPOINT_DESC_SIZE (sizeof(USB_ENDPOINT_DESCRIPTOR))
+
+extern const uint8_t USB_DeviceDescriptor[];
+extern const uint8_t USB_ConfigDescriptor[];
+extern const uint8_t USB_StringDescriptor[];
+
+
+#endif /* __USBDESC_H__ */
-/*----------------------------------------------------------------------------\r
- * U S B - K e r n e l\r
- *----------------------------------------------------------------------------\r
- * Name: usbhw.c\r
- * Purpose: USB Hardware Layer Module for NXP's LPC17xx MCU\r
- * Version: V1.20\r
- *----------------------------------------------------------------------------\r
- * This software is supplied "AS IS" without any warranties, express,\r
- * implied or statutory, including but not limited to the implied\r
- * warranties of fitness for purpose, satisfactory quality and\r
- * noninfringement. Keil extends you a royalty-free right to reproduce\r
- * and distribute executable files created using this software for use\r
- * on NXP Semiconductors LPC family microcontroller devices only. Nothing \r
- * else gives you the right to use this software.\r
- *\r
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
- *----------------------------------------------------------------------------\r
- * History:\r
- * V1.20 Added USB_ClearEPBuf\r
- * V1.00 Initial Version\r
- *----------------------------------------------------------------------------*/\r
-#include "../LPC17xx.h" /* LPC17xx definitions */\r
-#include "usb.h"\r
-#include "usbcfg.h"\r
-#include "usbreg.h"\r
-#include "usbhw.h"\r
-#include "usbcore.h"\r
-#include "usbuser.h"\r
-\r
-#if defined ( __CC_ARM__ )\r
-#pragma diag_suppress 1441\r
-#endif\r
-\r
-\r
-#define EP_MSK_CTRL 0x0001 /* Control Endpoint Logical Address Mask */\r
-#define EP_MSK_BULK 0xC924 /* Bulk Endpoint Logical Address Mask */\r
-#define EP_MSK_INT 0x4492 /* Interrupt Endpoint Logical Address Mask */\r
-#define EP_MSK_ISO 0x1248 /* Isochronous Endpoint Logical Address Mask */\r
-\r
-\r
-#if USB_DMA\r
-\r
-#pragma arm section zidata = "USB_RAM"\r
-uint32_t UDCA[USB_EP_NUM]; /* UDCA in USB RAM */\r
-uint32_t DD_NISO_Mem[4*DD_NISO_CNT]; /* Non-Iso DMA Descriptor Memory */\r
-uint32_t DD_ISO_Mem [5*DD_ISO_CNT]; /* Iso DMA Descriptor Memory */\r
-#pragma arm section zidata\r
-uint32_t udca[USB_EP_NUM]; /* UDCA saved values */\r
-\r
-uint32_t DDMemMap[2]; /* DMA Descriptor Memory Usage */\r
-\r
-#endif\r
-\r
-\r
-/*\r
- * Get Endpoint Physical Address\r
- * Parameters: EPNum: Endpoint Number\r
- * EPNum.0..3: Address\r
- * EPNum.7: Dir\r
- * Return Value: Endpoint Physical Address\r
- */\r
-\r
-uint32_t EPAdr (uint32_t EPNum) {\r
- uint32_t val;\r
-\r
- val = (EPNum & 0x0F) << 1;\r
- if (EPNum & 0x80) {\r
- val += 1;\r
- }\r
- return (val);\r
-}\r
-\r
-\r
-/*\r
- * Write Command\r
- * Parameters: cmd: Command\r
- * Return Value: None\r
- */\r
-\r
-void WrCmd (uint32_t cmd) {\r
-\r
- USB->USBDevIntClr = CCEMTY_INT;\r
- USB->USBCmdCode = cmd;\r
- while ((USB->USBDevIntSt & CCEMTY_INT) == 0);\r
-}\r
-\r
-\r
-/*\r
- * Write Command Data\r
- * Parameters: cmd: Command\r
- * val: Data\r
- * Return Value: None\r
- */\r
-\r
-void WrCmdDat (uint32_t cmd, uint32_t val) {\r
-\r
- USB->USBDevIntClr = CCEMTY_INT;\r
- USB->USBCmdCode = cmd;\r
- while ((USB->USBDevIntSt & CCEMTY_INT) == 0);\r
- USB->USBDevIntClr = CCEMTY_INT;\r
- USB->USBCmdCode = val;\r
- while ((USB->USBDevIntSt & CCEMTY_INT) == 0);\r
-}\r
-\r
-\r
-/*\r
- * Write Command to Endpoint\r
- * Parameters: cmd: Command\r
- * val: Data\r
- * Return Value: None\r
- */\r
-\r
-void WrCmdEP (uint32_t EPNum, uint32_t cmd){\r
-\r
- USB->USBDevIntClr = CCEMTY_INT;\r
- USB->USBCmdCode = CMD_SEL_EP(EPAdr(EPNum));\r
- while ((USB->USBDevIntSt & CCEMTY_INT) == 0);\r
- USB->USBDevIntClr = CCEMTY_INT;\r
- USB->USBCmdCode = cmd;\r
- while ((USB->USBDevIntSt & CCEMTY_INT) == 0);\r
-}\r
-\r
-\r
-/*\r
- * Read Command Data\r
- * Parameters: cmd: Command\r
- * Return Value: Data Value\r
- */\r
-\r
-uint32_t RdCmdDat (uint32_t cmd) {\r
-\r
- USB->USBDevIntClr = CCEMTY_INT | CDFULL_INT;\r
- USB->USBCmdCode = cmd;\r
- while ((USB->USBDevIntSt & CDFULL_INT) == 0);\r
- return (USB->USBCmdData);\r
-}\r
-\r
-\r
-/*\r
- * USB Initialize Function\r
- * Called by the User to initialize USB\r
- * Return Value: None\r
- */\r
-\r
-void USB_Init (void) {\r
-\r
- PINCON->PINSEL1 &= ~((3<<26)|(3<<28)); /* P0.29 D+, P0.30 D- */\r
- PINCON->PINSEL1 |= ((1<<26)|(1<<28)); /* PINSEL1 26.27, 28.29 = 01 */\r
-\r
- PINCON->PINSEL3 &= ~((3<< 4)|(3<<28)); /* P1.18 GoodLink, P1.30 VBUS */\r
- PINCON->PINSEL3 |= ((1<< 4)|(2<<28)); /* PINSEL3 4.5 = 01, 28.29 = 10 */\r
-\r
- PINCON->PINSEL4 &= ~((3<<18) ); /* P2.9 SoftConnect */\r
- PINCON->PINSEL4 |= ((1<<18) ); /* PINSEL4 18.19 = 01 */\r
-\r
- SC->PCONP |= (1UL<<31); /* USB PCLK -> enable USB Per. */\r
-\r
- USB->USBClkCtrl = 0x1A; /* Dev, PortSel, AHB clock enable */\r
- while ((USB->USBClkSt & 0x1A) != 0x1A); \r
-\r
- NVIC_EnableIRQ(USB_IRQn); /* enable USB interrupt */\r
-\r
- USB_Reset();\r
- USB_SetAddress(0);\r
-}\r
-\r
-\r
-/*\r
- * USB Connect Function\r
- * Called by the User to Connect/Disconnect USB\r
- * Parameters: con: Connect/Disconnect\r
- * Return Value: None\r
- */\r
-\r
-void USB_Connect (uint32_t con) {\r
- WrCmdDat(CMD_SET_DEV_STAT, DAT_WR_BYTE(con ? DEV_CON : 0));\r
-}\r
-\r
-\r
-/*\r
- * USB Reset Function\r
- * Called automatically on USB Reset\r
- * Return Value: None\r
- */\r
-\r
-void USB_Reset (void) {\r
-#if USB_DMA\r
- uint32_t n;\r
-#endif\r
-\r
- USB->USBEpInd = 0;\r
- USB->USBMaxPSize = USB_MAX_PACKET0;\r
- USB->USBEpInd = 1;\r
- USB->USBMaxPSize = USB_MAX_PACKET0;\r
- while ((USB->USBDevIntSt & EP_RLZED_INT) == 0);\r
-\r
- USB->USBEpIntClr = 0xFFFFFFFF;\r
- USB->USBEpIntEn = 0xFFFFFFFF ^ USB_DMA_EP;\r
- USB->USBDevIntClr = 0xFFFFFFFF;\r
- USB->USBDevIntEn = DEV_STAT_INT | EP_SLOW_INT |\r
- (USB_SOF_EVENT ? FRAME_INT : 0) |\r
- (USB_ERROR_EVENT ? ERR_INT : 0);\r
-\r
-#if USB_DMA\r
- USB->USBUDCAH = USB_RAM_ADR;\r
- USB->USBDMARClr = 0xFFFFFFFF;\r
- USB->USBEpDMADis = 0xFFFFFFFF;\r
- USB->USBEpDMAEn = USB_DMA_EP;\r
- USB->USBEoTIntClr = 0xFFFFFFFF;\r
- USB->USBNDDRIntClr = 0xFFFFFFFF;\r
- USB->USBSysErrIntClr = 0xFFFFFFFF;\r
- USB->USBDMAIntEn = 0x00000007;\r
- DDMemMap[0] = 0x00000000;\r
- DDMemMap[1] = 0x00000000;\r
- for (n = 0; n < USB_EP_NUM; n++) {\r
- udca[n] = 0;\r
- UDCA[n] = 0;\r
- }\r
-#endif\r
-}\r
-\r
-\r
-/*\r
- * USB Suspend Function\r
- * Called automatically on USB Suspend\r
- * Return Value: None\r
- */\r
-\r
-void USB_Suspend (void) {\r
- /* Performed by Hardware */\r
-}\r
-\r
-\r
-/*\r
- * USB Resume Function\r
- * Called automatically on USB Resume\r
- * Return Value: None\r
- */\r
-\r
-void USB_Resume (void) {\r
- /* Performed by Hardware */\r
-}\r
-\r
-\r
-/*\r
- * USB Remote Wakeup Function\r
- * Called automatically on USB Remote Wakeup\r
- * Return Value: None\r
- */\r
-\r
-void USB_WakeUp (void) {\r
-\r
- if (USB_DeviceStatus & USB_GETSTATUS_REMOTE_WAKEUP) {\r
- WrCmdDat(CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));\r
- }\r
-}\r
-\r
-\r
-/*\r
- * USB Remote Wakeup Configuration Function\r
- * Parameters: cfg: Enable/Disable\r
- * Return Value: None\r
- */\r
-\r
-void USB_WakeUpCfg (uint32_t cfg) {\r
- /* Not needed */\r
-}\r
-\r
-\r
-/*\r
- * USB Set Address Function\r
- * Parameters: adr: USB Address\r
- * Return Value: None\r
- */\r
-\r
-void USB_SetAddress (uint32_t adr) {\r
- WrCmdDat(CMD_SET_ADDR, DAT_WR_BYTE(DEV_EN | adr)); /* Don't wait for next */\r
- WrCmdDat(CMD_SET_ADDR, DAT_WR_BYTE(DEV_EN | adr)); /* Setup Status Phase */\r
-}\r
-\r
-\r
-/*\r
- * USB Configure Function\r
- * Parameters: cfg: Configure/Deconfigure\r
- * Return Value: None\r
- */\r
-\r
-void USB_Configure (uint32_t cfg) {\r
-\r
- WrCmdDat(CMD_CFG_DEV, DAT_WR_BYTE(cfg ? CONF_DVICE : 0));\r
-\r
- USB->USBReEp = 0x00000003;\r
- while ((USB->USBDevIntSt & EP_RLZED_INT) == 0);\r
- USB->USBDevIntClr = EP_RLZED_INT;\r
-}\r
-\r
-\r
-/*\r
- * Configure USB Endpoint according to Descriptor\r
- * Parameters: pEPD: Pointer to Endpoint Descriptor\r
- * Return Value: None\r
- */\r
-\r
-void USB_ConfigEP (USB_ENDPOINT_DESCRIPTOR *pEPD) {\r
- uint32_t num;\r
-\r
- num = EPAdr(pEPD->bEndpointAddress);\r
- USB->USBReEp |= (1 << num);\r
- USB->USBEpInd = num;\r
- USB->USBMaxPSize = pEPD->wMaxPacketSize;\r
- while ((USB->USBDevIntSt & EP_RLZED_INT) == 0);\r
- USB->USBDevIntClr = EP_RLZED_INT;\r
-}\r
-\r
-\r
-/*\r
- * Set Direction for USB Control Endpoint\r
- * Parameters: dir: Out (dir == 0), In (dir <> 0)\r
- * Return Value: None\r
- */\r
-\r
-void USB_DirCtrlEP (uint32_t dir) {\r
- /* Not needed */\r
-}\r
-\r
-\r
-/*\r
- * Enable USB Endpoint\r
- * Parameters: EPNum: Endpoint Number\r
- * EPNum.0..3: Address\r
- * EPNum.7: Dir\r
- * Return Value: None\r
- */\r
-\r
-void USB_EnableEP (uint32_t EPNum) {\r
- WrCmdDat(CMD_SET_EP_STAT(EPAdr(EPNum)), DAT_WR_BYTE(0));\r
-}\r
-\r
-\r
-/*\r
- * Disable USB Endpoint\r
- * Parameters: EPNum: Endpoint Number\r
- * EPNum.0..3: Address\r
- * EPNum.7: Dir\r
- * Return Value: None\r
- */\r
-\r
-void USB_DisableEP (uint32_t EPNum) {\r
- WrCmdDat(CMD_SET_EP_STAT(EPAdr(EPNum)), DAT_WR_BYTE(EP_STAT_DA));\r
-}\r
-\r
-\r
-/*\r
- * Reset USB Endpoint\r
- * Parameters: EPNum: Endpoint Number\r
- * EPNum.0..3: Address\r
- * EPNum.7: Dir\r
- * Return Value: None\r
- */\r
-\r
-void USB_ResetEP (uint32_t EPNum) {\r
- WrCmdDat(CMD_SET_EP_STAT(EPAdr(EPNum)), DAT_WR_BYTE(0));\r
-}\r
-\r
-\r
-/*\r
- * Set Stall for USB Endpoint\r
- * Parameters: EPNum: Endpoint Number\r
- * EPNum.0..3: Address\r
- * EPNum.7: Dir\r
- * Return Value: None\r
- */\r
-\r
-void USB_SetStallEP (uint32_t EPNum) {\r
- WrCmdDat(CMD_SET_EP_STAT(EPAdr(EPNum)), DAT_WR_BYTE(EP_STAT_ST));\r
-}\r
-\r
-\r
-/*\r
- * Clear Stall for USB Endpoint\r
- * Parameters: EPNum: Endpoint Number\r
- * EPNum.0..3: Address\r
- * EPNum.7: Dir\r
- * Return Value: None\r
- */\r
-\r
-void USB_ClrStallEP (uint32_t EPNum) {\r
- WrCmdDat(CMD_SET_EP_STAT(EPAdr(EPNum)), DAT_WR_BYTE(0));\r
-}\r
-\r
-\r
-/*\r
- * Clear USB Endpoint Buffer\r
- * Parameters: EPNum: Endpoint Number\r
- * EPNum.0..3: Address\r
- * EPNum.7: Dir\r
- * Return Value: None\r
- */\r
-\r
-void USB_ClearEPBuf (uint32_t EPNum) {\r
- WrCmdEP(EPNum, CMD_CLR_BUF);\r
-}\r
-\r
-\r
-/*\r
- * Read USB Endpoint Data\r
- * Parameters: EPNum: Endpoint Number\r
- * EPNum.0..3: Address\r
- * EPNum.7: Dir\r
- * pData: Pointer to Data Buffer\r
- * Return Value: Number of bytes read\r
- */\r
-\r
-uint32_t USB_ReadEP (uint32_t EPNum, uint8_t *pData) {\r
- uint32_t cnt, n;\r
-\r
- USB->USBCtrl = ((EPNum & 0x0F) << 2) | CTRL_RD_EN;\r
-\r
- do {\r
- cnt = USB->USBRxPLen;\r
- } while ((cnt & PKT_RDY) == 0);\r
- cnt &= PKT_LNGTH_MASK;\r
-\r
- for (n = 0; n < (cnt + 3) / 4; n++) {\r
- *((__packed uint32_t *)pData) = USB->USBRxData;\r
- pData += 4;\r
- }\r
- USB->USBCtrl = 0;\r
-\r
- if (((EP_MSK_ISO >> EPNum) & 1) == 0) { /* Non-Isochronous Endpoint */\r
- WrCmdEP(EPNum, CMD_CLR_BUF);\r
- }\r
-\r
- return (cnt);\r
-}\r
-\r
-\r
-/*\r
- * Write USB Endpoint Data\r
- * Parameters: EPNum: Endpoint Number\r
- * EPNum.0..3: Address\r
- * EPNum.7: Dir\r
- * pData: Pointer to Data Buffer\r
- * cnt: Number of bytes to write\r
- * Return Value: Number of bytes written\r
- */\r
-\r
-uint32_t USB_WriteEP (uint32_t EPNum, uint8_t *pData, uint32_t cnt) {\r
- uint32_t n;\r
-\r
- USB->USBCtrl = ((EPNum & 0x0F) << 2) | CTRL_WR_EN;\r
-\r
- USB->USBTxPLen = cnt;\r
-\r
- for (n = 0; n < (cnt + 3) / 4; n++) {\r
- USB->USBTxData = *((__packed uint32_t *)pData);\r
- pData += 4;\r
- }\r
- USB->USBCtrl = 0;\r
- WrCmdEP(EPNum, CMD_VALID_BUF);\r
- return (cnt);\r
-}\r
-\r
-#if USB_DMA\r
-\r
-/* DMA Descriptor Memory Layout */\r
-const uint32_t DDAdr[2] = { DD_NISO_ADR, DD_ISO_ADR };\r
-const uint32_t DDSz [2] = { 16, 20 };\r
-\r
-\r
-/*\r
- * Setup USB DMA Transfer for selected Endpoint\r
- * Parameters: EPNum: Endpoint Number\r
- * pDD: Pointer to DMA Descriptor\r
- * Return Value: TRUE - Success, FALSE - Error\r
- */\r
-\r
-uint32_t USB_DMA_Setup(uint32_t EPNum, USB_DMA_DESCRIPTOR *pDD) {\r
- uint32_t num, ptr, nxt, iso, n;\r
-\r
- iso = pDD->Cfg.Type.IsoEP; /* Iso or Non-Iso Descriptor */\r
- num = EPAdr(EPNum); /* Endpoint's Physical Address */\r
-\r
- ptr = 0; /* Current Descriptor */\r
- nxt = udca[num]; /* Initial Descriptor */\r
- while (nxt) { /* Go through Descriptor List */\r
- ptr = nxt; /* Current Descriptor */\r
- if (!pDD->Cfg.Type.Link) { /* Check for Linked Descriptors */\r
- n = (ptr - DDAdr[iso]) / DDSz[iso]; /* Descriptor Index */\r
- DDMemMap[iso] &= ~(1 << n); /* Unmark Memory Usage */\r
- }\r
- nxt = *((uint32_t *)ptr); /* Next Descriptor */\r
- }\r
-\r
- for (n = 0; n < 32; n++) { /* Search for available Memory */\r
- if ((DDMemMap[iso] & (1 << n)) == 0) {\r
- break; /* Memory found */\r
- }\r
- }\r
- if (n == 32) return (FALSE); /* Memory not available */\r
-\r
- DDMemMap[iso] |= 1 << n; /* Mark Memory Usage */\r
- nxt = DDAdr[iso] + n * DDSz[iso]; /* Next Descriptor */\r
-\r
- if (ptr && pDD->Cfg.Type.Link) {\r
- *((uint32_t *)(ptr + 0)) = nxt; /* Link in new Descriptor */\r
- *((uint32_t *)(ptr + 4)) |= 0x00000004; /* Next DD is Valid */\r
- } else {\r
- udca[num] = nxt; /* Save new Descriptor */\r
- UDCA[num] = nxt; /* Update UDCA in USB */\r
- }\r
-\r
- /* Fill in DMA Descriptor */\r
- *(((uint32_t *)nxt)++) = 0; /* Next DD Pointer */\r
- *(((uint32_t *)nxt)++) = pDD->Cfg.Type.ATLE |\r
- (pDD->Cfg.Type.IsoEP << 4) |\r
- (pDD->MaxSize << 5) |\r
- (pDD->BufLen << 16);\r
- *(((uint32_t *)nxt)++) = pDD->BufAdr;\r
- *(((uint32_t *)nxt)++) = pDD->Cfg.Type.LenPos << 8;\r
- if (iso) {\r
- *((uint32_t *)nxt) = pDD->InfoAdr;\r
- }\r
-\r
- return (TRUE); /* Success */\r
-}\r
-\r
-\r
-/*\r
- * Enable USB DMA Endpoint\r
- * Parameters: EPNum: Endpoint Number\r
- * EPNum.0..3: Address\r
- * EPNum.7: Dir\r
- * Return Value: None\r
- */\r
-\r
-void USB_DMA_Enable (uint32_t EPNum) {\r
- USB->USBEpDMAEn = 1 << EPAdr(EPNum);\r
-}\r
-\r
-\r
-/*\r
- * Disable USB DMA Endpoint\r
- * Parameters: EPNum: Endpoint Number\r
- * EPNum.0..3: Address\r
- * EPNum.7: Dir\r
- * Return Value: None\r
- */\r
-\r
-void USB_DMA_Disable (uint32_t EPNum) {\r
- USB->USBEpDMADis = 1 << EPAdr(EPNum);\r
-}\r
-\r
-\r
-/*\r
- * Get USB DMA Endpoint Status\r
- * Parameters: EPNum: Endpoint Number\r
- * EPNum.0..3: Address\r
- * EPNum.7: Dir\r
- * Return Value: DMA Status\r
- */\r
-\r
-uint32_t USB_DMA_Status (uint32_t EPNum) {\r
- uint32_t ptr, val;\r
- \r
- ptr = UDCA[EPAdr(EPNum)]; /* Current Descriptor */\r
- if (ptr == 0) \r
- return (USB_DMA_INVALID);\r
-\r
- val = *((uint32_t *)(ptr + 3*4)); /* Status Information */\r
- switch ((val >> 1) & 0x0F) {\r
- case 0x00: /* Not serviced */\r
- return (USB_DMA_IDLE);\r
- case 0x01: /* Being serviced */\r
- return (USB_DMA_BUSY);\r
- case 0x02: /* Normal Completition */\r
- return (USB_DMA_DONE);\r
- case 0x03: /* Data Under Run */\r
- return (USB_DMA_UNDER_RUN);\r
- case 0x08: /* Data Over Run */\r
- return (USB_DMA_OVER_RUN);\r
- case 0x09: /* System Error */\r
- return (USB_DMA_ERROR);\r
- }\r
-\r
- return (USB_DMA_UNKNOWN);\r
-}\r
-\r
-\r
-/*\r
- * Get USB DMA Endpoint Current Buffer Address\r
- * Parameters: EPNum: Endpoint Number\r
- * EPNum.0..3: Address\r
- * EPNum.7: Dir\r
- * Return Value: DMA Address (or -1 when DMA is Invalid)\r
- */\r
-\r
-uint32_t USB_DMA_BufAdr (uint32_t EPNum) {\r
- uint32_t ptr, val;\r
-\r
- ptr = UDCA[EPAdr(EPNum)]; /* Current Descriptor */\r
- if (ptr == 0)\r
- {\r
- return ((uint32_t)(-1)); /* DMA Invalid */\r
- }\r
-\r
- val = *((uint32_t *)(ptr + 2*4)); /* Buffer Address */\r
- return (val); /* Current Address */\r
-}\r
-\r
-\r
-/*\r
- * Get USB DMA Endpoint Current Buffer Count\r
- * Number of transfered Bytes or Iso Packets\r
- * Parameters: EPNum: Endpoint Number\r
- * EPNum.0..3: Address\r
- * EPNum.7: Dir\r
- * Return Value: DMA Count (or -1 when DMA is Invalid)\r
- */\r
-\r
-uint32_t USB_DMA_BufCnt (uint32_t EPNum) {\r
- uint32_t ptr, val;\r
-\r
- ptr = UDCA[EPAdr(EPNum)]; /* Current Descriptor */\r
- if (ptr == 0)\r
- { \r
- return ((uint32_t)(-1)); /* DMA Invalid */\r
- }\r
- val = *((uint32_t *)(ptr + 3*4)); /* Status Information */\r
- return (val >> 16); /* Current Count */\r
-}\r
-\r
-\r
-#endif /* USB_DMA */\r
-\r
-\r
-/*\r
- * Get USB Last Frame Number\r
- * Parameters: None\r
- * Return Value: Frame Number\r
- */\r
-\r
-uint32_t USB_GetFrame (void) {\r
- uint32_t val;\r
-\r
- WrCmd(CMD_RD_FRAME);\r
- val = RdCmdDat(DAT_RD_FRAME);\r
- val = val | (RdCmdDat(DAT_RD_FRAME) << 8);\r
-\r
- return (val);\r
-}\r
-\r
-\r
-/*\r
- * USB Interrupt Service Routine\r
- */\r
-\r
-void USB_IRQHandler (void) {\r
- uint32_t disr, val, n, m;\r
- uint32_t episr, episrCur;\r
-\r
- disr = USB->USBDevIntSt; /* Device Interrupt Status */\r
-\r
- /* Device Status Interrupt (Reset, Connect change, Suspend/Resume) */\r
- if (disr & DEV_STAT_INT) {\r
- USB->USBDevIntClr = DEV_STAT_INT;\r
- WrCmd(CMD_GET_DEV_STAT);\r
- val = RdCmdDat(DAT_GET_DEV_STAT); /* Device Status */\r
- if (val & DEV_RST) { /* Reset */\r
- USB_Reset();\r
-#if USB_RESET_EVENT\r
- USB_Reset_Event();\r
-#endif\r
- }\r
- if (val & DEV_CON_CH) { /* Connect change */\r
-#if USB_POWER_EVENT\r
- USB_Power_Event(val & DEV_CON);\r
-#endif\r
- }\r
- if (val & DEV_SUS_CH) { /* Suspend/Resume */\r
- if (val & DEV_SUS) { /* Suspend */\r
- USB_Suspend();\r
-#if USB_SUSPEND_EVENT\r
- USB_Suspend_Event();\r
-#endif\r
- } else { /* Resume */\r
- USB_Resume();\r
-#if USB_RESUME_EVENT\r
- USB_Resume_Event();\r
-#endif\r
- }\r
- }\r
- goto isr_end;\r
- }\r
-\r
-#if USB_SOF_EVENT\r
- /* Start of Frame Interrupt */\r
- if (disr & FRAME_INT) {\r
- USB_SOF_Event();\r
- }\r
-#endif\r
-\r
-#if USB_ERROR_EVENT\r
- /* Error Interrupt */\r
- if (disr & ERR_INT) {\r
- WrCmd(CMD_RD_ERR_STAT);\r
- val = RdCmdDat(DAT_RD_ERR_STAT);\r
- USB_Error_Event(val);\r
- }\r
-#endif\r
-\r
- /* Endpoint's Slow Interrupt */\r
- if (disr & EP_SLOW_INT) {\r
- episrCur = 0;\r
- episr = USB->USBEpIntSt;\r
- for (n = 0; n < USB_EP_NUM; n++) { /* Check All Endpoints */\r
- if (episr == episrCur) break; /* break if all EP interrupts handled */\r
- if (episr & (1 << n)) {\r
- episrCur |= (1 << n);\r
- m = n >> 1;\r
- \r
- USB->USBEpIntClr = (1 << n);\r
- while ((USB->USBDevIntSt & CDFULL_INT) == 0);\r
- val = USB->USBCmdData;\r
- \r
- if ((n & 1) == 0) { /* OUT Endpoint */\r
- if (n == 0) { /* Control OUT Endpoint */\r
- if (val & EP_SEL_STP) { /* Setup Packet */\r
- if (USB_P_EP[0]) {\r
- USB_P_EP[0](USB_EVT_SETUP);\r
- continue;\r
- }\r
- }\r
- }\r
- if (USB_P_EP[m]) {\r
- USB_P_EP[m](USB_EVT_OUT);\r
- }\r
- } else { /* IN Endpoint */\r
- if (USB_P_EP[m]) {\r
- USB_P_EP[m](USB_EVT_IN);\r
- }\r
- }\r
- }\r
- }\r
- USB->USBDevIntClr = EP_SLOW_INT;\r
- }\r
-\r
-#if USB_DMA\r
-\r
- if (USB->USBDMAIntSt & 0x00000001) { /* End of Transfer Interrupt */\r
- val = USB->USBEoTIntSt;\r
- for (n = 2; n < USB_EP_NUM; n++) { /* Check All Endpoints */\r
- if (val & (1 << n)) {\r
- m = n >> 1;\r
- if ((n & 1) == 0) { /* OUT Endpoint */\r
- if (USB_P_EP[m]) {\r
- USB_P_EP[m](USB_EVT_OUT_DMA_EOT);\r
- }\r
- } else { /* IN Endpoint */\r
- if (USB_P_EP[m]) {\r
- USB_P_EP[m](USB_EVT_IN_DMA_EOT);\r
- }\r
- }\r
- }\r
- }\r
- USB->USBEoTIntClr = val;\r
- }\r
-\r
- if (USB->USBDMAIntSt & 0x00000002) { /* New DD Request Interrupt */\r
- val = USB->USBNDDRIntSt;\r
- for (n = 2; n < USB_EP_NUM; n++) { /* Check All Endpoints */\r
- if (val & (1 << n)) {\r
- m = n >> 1;\r
- if ((n & 1) == 0) { /* OUT Endpoint */\r
- if (USB_P_EP[m]) {\r
- USB_P_EP[m](USB_EVT_OUT_DMA_NDR);\r
- }\r
- } else { /* IN Endpoint */\r
- if (USB_P_EP[m]) {\r
- USB_P_EP[m](USB_EVT_IN_DMA_NDR);\r
- }\r
- }\r
- }\r
- }\r
- USB->USBNDDRIntClr = val;\r
- }\r
-\r
- if (USB->USBDMAIntSt & 0x00000004) { /* System Error Interrupt */\r
- val = USB->USBSysErrIntSt;\r
- for (n = 2; n < USB_EP_NUM; n++) { /* Check All Endpoints */\r
- if (val & (1 << n)) {\r
- m = n >> 1;\r
- if ((n & 1) == 0) { /* OUT Endpoint */\r
- if (USB_P_EP[m]) {\r
- USB_P_EP[m](USB_EVT_OUT_DMA_ERR);\r
- }\r
- } else { /* IN Endpoint */\r
- if (USB_P_EP[m]) {\r
- USB_P_EP[m](USB_EVT_IN_DMA_ERR);\r
- }\r
- }\r
- }\r
- }\r
- USB->USBSysErrIntClr = val;\r
- }\r
-\r
-#endif /* USB_DMA */\r
-\r
-isr_end:\r
- return;\r
-}\r
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: usbhw.c
+ * Purpose: USB Hardware Layer Module for NXP's LPC17xx MCU
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC family microcontroller devices only. Nothing
+ * else gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *----------------------------------------------------------------------------
+ * History:
+ * V1.20 Added USB_ClearEPBuf
+ * V1.00 Initial Version
+ *----------------------------------------------------------------------------*/
+#include <board.h> /* LPC17xx definitions */
+#include "usb.h"
+#include "cfg.h"
+#include "reg.h"
+#include "hw.h"
+#include "core.h"
+#include "user.h"
+
+#if defined ( __CC_ARM__ )
+#pragma diag_suppress 1441
+#endif
+
+
+#define EP_MSK_CTRL 0x0001 /* Control Endpoint Logical Address Mask */
+#define EP_MSK_BULK 0xC924 /* Bulk Endpoint Logical Address Mask */
+#define EP_MSK_INT 0x4492 /* Interrupt Endpoint Logical Address Mask */
+#define EP_MSK_ISO 0x1248 /* Isochronous Endpoint Logical Address Mask */
+
+
+#if USB_DMA
+
+#pragma arm section zidata = "USB_RAM"
+uint32_t UDCA[USB_EP_NUM]; /* UDCA in USB RAM */
+uint32_t DD_NISO_Mem[4*DD_NISO_CNT]; /* Non-Iso DMA Descriptor Memory */
+uint32_t DD_ISO_Mem [5*DD_ISO_CNT]; /* Iso DMA Descriptor Memory */
+#pragma arm section zidata
+uint32_t udca[USB_EP_NUM]; /* UDCA saved values */
+
+uint32_t DDMemMap[2]; /* DMA Descriptor Memory Usage */
+
+#endif
+
+
+/*
+ * Get Endpoint Physical Address
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: Endpoint Physical Address
+ */
+
+uint32_t EPAdr (uint32_t EPNum) {
+ uint32_t val;
+
+ val = (EPNum & 0x0F) << 1;
+ if (EPNum & 0x80) {
+ val += 1;
+ }
+ return (val);
+}
+
+
+/*
+ * Write Command
+ * Parameters: cmd: Command
+ * Return Value: None
+ */
+
+void WrCmd (uint32_t cmd) {
+
+ USB->USBDevIntClr = CCEMTY_INT;
+ USB->USBCmdCode = cmd;
+ while ((USB->USBDevIntSt & CCEMTY_INT) == 0);
+}
+
+
+/*
+ * Write Command Data
+ * Parameters: cmd: Command
+ * val: Data
+ * Return Value: None
+ */
+
+void WrCmdDat (uint32_t cmd, uint32_t val) {
+
+ USB->USBDevIntClr = CCEMTY_INT;
+ USB->USBCmdCode = cmd;
+ while ((USB->USBDevIntSt & CCEMTY_INT) == 0);
+ USB->USBDevIntClr = CCEMTY_INT;
+ USB->USBCmdCode = val;
+ while ((USB->USBDevIntSt & CCEMTY_INT) == 0);
+}
+
+
+/*
+ * Write Command to Endpoint
+ * Parameters: cmd: Command
+ * val: Data
+ * Return Value: None
+ */
+
+void WrCmdEP (uint32_t EPNum, uint32_t cmd){
+
+ USB->USBDevIntClr = CCEMTY_INT;
+ USB->USBCmdCode = CMD_SEL_EP(EPAdr(EPNum));
+ while ((USB->USBDevIntSt & CCEMTY_INT) == 0);
+ USB->USBDevIntClr = CCEMTY_INT;
+ USB->USBCmdCode = cmd;
+ while ((USB->USBDevIntSt & CCEMTY_INT) == 0);
+}
+
+
+/*
+ * Read Command Data
+ * Parameters: cmd: Command
+ * Return Value: Data Value
+ */
+
+uint32_t RdCmdDat (uint32_t cmd) {
+
+ USB->USBDevIntClr = CCEMTY_INT | CDFULL_INT;
+ USB->USBCmdCode = cmd;
+ while ((USB->USBDevIntSt & CDFULL_INT) == 0);
+ return (USB->USBCmdData);
+}
+
+
+/*
+ * USB Initialize Function
+ * Called by the User to initialize USB
+ * Return Value: None
+ */
+
+void USB_Init (void) {
+
+ PINCON->PINSEL1 &= ~((3<<26)|(3<<28)); /* P0.29 D+, P0.30 D- */
+ PINCON->PINSEL1 |= ((1<<26)|(1<<28)); /* PINSEL1 26.27, 28.29 = 01 */
+
+ PINCON->PINSEL3 &= ~((3<< 4)|(3<<28)); /* P1.18 GoodLink, P1.30 VBUS */
+ PINCON->PINSEL3 |= ((1<< 4)|(2<<28)); /* PINSEL3 4.5 = 01, 28.29 = 10 */
+
+ PINCON->PINSEL4 &= ~((3<<18) ); /* P2.9 SoftConnect */
+ PINCON->PINSEL4 |= ((1<<18) ); /* PINSEL4 18.19 = 01 */
+
+ SC->PCONP |= (1UL<<31); /* USB PCLK -> enable USB Per. */
+
+ USB->USBClkCtrl = 0x1A; /* Dev, PortSel, AHB clock enable */
+ while ((USB->USBClkSt & 0x1A) != 0x1A);
+
+ NVIC_EnableIRQ(USB_IRQn); /* enable USB interrupt */
+
+ USB_Reset();
+ USB_SetAddress(0);
+}
+
+
+/*
+ * USB Connect Function
+ * Called by the User to Connect/Disconnect USB
+ * Parameters: con: Connect/Disconnect
+ * Return Value: None
+ */
+
+void USB_Connect (uint32_t con) {
+ WrCmdDat(CMD_SET_DEV_STAT, DAT_WR_BYTE(con ? DEV_CON : 0));
+}
+
+
+/*
+ * USB Reset Function
+ * Called automatically on USB Reset
+ * Return Value: None
+ */
+
+void USB_Reset (void) {
+#if USB_DMA
+ uint32_t n;
+#endif
+
+ USB->USBEpInd = 0;
+ USB->USBMaxPSize = USB_MAX_PACKET0;
+ USB->USBEpInd = 1;
+ USB->USBMaxPSize = USB_MAX_PACKET0;
+ while ((USB->USBDevIntSt & EP_RLZED_INT) == 0);
+
+ USB->USBEpIntClr = 0xFFFFFFFF;
+ USB->USBEpIntEn = 0xFFFFFFFF ^ USB_DMA_EP;
+ USB->USBDevIntClr = 0xFFFFFFFF;
+ USB->USBDevIntEn = DEV_STAT_INT | EP_SLOW_INT |
+ (USB_SOF_EVENT ? FRAME_INT : 0) |
+ (USB_ERROR_EVENT ? ERR_INT : 0);
+
+#if USB_DMA
+ USB->USBUDCAH = USB_RAM_ADR;
+ USB->USBDMARClr = 0xFFFFFFFF;
+ USB->USBEpDMADis = 0xFFFFFFFF;
+ USB->USBEpDMAEn = USB_DMA_EP;
+ USB->USBEoTIntClr = 0xFFFFFFFF;
+ USB->USBNDDRIntClr = 0xFFFFFFFF;
+ USB->USBSysErrIntClr = 0xFFFFFFFF;
+ USB->USBDMAIntEn = 0x00000007;
+ DDMemMap[0] = 0x00000000;
+ DDMemMap[1] = 0x00000000;
+ for (n = 0; n < USB_EP_NUM; n++) {
+ udca[n] = 0;
+ UDCA[n] = 0;
+ }
+#endif
+}
+
+
+/*
+ * USB Suspend Function
+ * Called automatically on USB Suspend
+ * Return Value: None
+ */
+
+void USB_Suspend (void) {
+ /* Performed by Hardware */
+}
+
+
+/*
+ * USB Resume Function
+ * Called automatically on USB Resume
+ * Return Value: None
+ */
+
+void USB_Resume (void) {
+ /* Performed by Hardware */
+}
+
+
+/*
+ * USB Remote Wakeup Function
+ * Called automatically on USB Remote Wakeup
+ * Return Value: None
+ */
+
+void USB_WakeUp (void) {
+
+ if (USB_DeviceStatus & USB_GETSTATUS_REMOTE_WAKEUP) {
+ WrCmdDat(CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));
+ }
+}
+
+
+/*
+ * USB Remote Wakeup Configuration Function
+ * Parameters: cfg: Enable/Disable
+ * Return Value: None
+ */
+
+void USB_WakeUpCfg (uint32_t cfg) {
+ /* Not needed */
+}
+
+
+/*
+ * USB Set Address Function
+ * Parameters: adr: USB Address
+ * Return Value: None
+ */
+
+void USB_SetAddress (uint32_t adr) {
+ WrCmdDat(CMD_SET_ADDR, DAT_WR_BYTE(DEV_EN | adr)); /* Don't wait for next */
+ WrCmdDat(CMD_SET_ADDR, DAT_WR_BYTE(DEV_EN | adr)); /* Setup Status Phase */
+}
+
+
+/*
+ * USB Configure Function
+ * Parameters: cfg: Configure/Deconfigure
+ * Return Value: None
+ */
+
+void USB_Configure (uint32_t cfg) {
+
+ WrCmdDat(CMD_CFG_DEV, DAT_WR_BYTE(cfg ? CONF_DVICE : 0));
+
+ USB->USBReEp = 0x00000003;
+ while ((USB->USBDevIntSt & EP_RLZED_INT) == 0);
+ USB->USBDevIntClr = EP_RLZED_INT;
+}
+
+
+/*
+ * Configure USB Endpoint according to Descriptor
+ * Parameters: pEPD: Pointer to Endpoint Descriptor
+ * Return Value: None
+ */
+
+void USB_ConfigEP (USB_ENDPOINT_DESCRIPTOR *pEPD) {
+ uint32_t num;
+
+ num = EPAdr(pEPD->bEndpointAddress);
+ USB->USBReEp |= (1 << num);
+ USB->USBEpInd = num;
+ USB->USBMaxPSize = pEPD->wMaxPacketSize;
+ while ((USB->USBDevIntSt & EP_RLZED_INT) == 0);
+ USB->USBDevIntClr = EP_RLZED_INT;
+}
+
+
+/*
+ * Set Direction for USB Control Endpoint
+ * Parameters: dir: Out (dir == 0), In (dir <> 0)
+ * Return Value: None
+ */
+
+void USB_DirCtrlEP (uint32_t dir) {
+ /* Not needed */
+}
+
+
+/*
+ * Enable USB Endpoint
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USB_EnableEP (uint32_t EPNum) {
+ WrCmdDat(CMD_SET_EP_STAT(EPAdr(EPNum)), DAT_WR_BYTE(0));
+}
+
+
+/*
+ * Disable USB Endpoint
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USB_DisableEP (uint32_t EPNum) {
+ WrCmdDat(CMD_SET_EP_STAT(EPAdr(EPNum)), DAT_WR_BYTE(EP_STAT_DA));
+}
+
+
+/*
+ * Reset USB Endpoint
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USB_ResetEP (uint32_t EPNum) {
+ WrCmdDat(CMD_SET_EP_STAT(EPAdr(EPNum)), DAT_WR_BYTE(0));
+}
+
+
+/*
+ * Set Stall for USB Endpoint
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USB_SetStallEP (uint32_t EPNum) {
+ WrCmdDat(CMD_SET_EP_STAT(EPAdr(EPNum)), DAT_WR_BYTE(EP_STAT_ST));
+}
+
+
+/*
+ * Clear Stall for USB Endpoint
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USB_ClrStallEP (uint32_t EPNum) {
+ WrCmdDat(CMD_SET_EP_STAT(EPAdr(EPNum)), DAT_WR_BYTE(0));
+}
+
+
+/*
+ * Clear USB Endpoint Buffer
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USB_ClearEPBuf (uint32_t EPNum) {
+ WrCmdEP(EPNum, CMD_CLR_BUF);
+}
+
+
+/*
+ * Read USB Endpoint Data
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * Return Value: Number of bytes read
+ */
+
+uint32_t USB_ReadEP (uint32_t EPNum, uint8_t *pData) {
+ uint32_t cnt, n;
+
+ USB->USBCtrl = ((EPNum & 0x0F) << 2) | CTRL_RD_EN;
+
+ do {
+ cnt = USB->USBRxPLen;
+ } while ((cnt & PKT_RDY) == 0);
+ cnt &= PKT_LNGTH_MASK;
+
+ for (n = 0; n < (cnt + 3) / 4; n++) {
+ *((__packed uint32_t *)pData) = USB->USBRxData;
+ pData += 4;
+ }
+ USB->USBCtrl = 0;
+
+ if (((EP_MSK_ISO >> EPNum) & 1) == 0) { /* Non-Isochronous Endpoint */
+ WrCmdEP(EPNum, CMD_CLR_BUF);
+ }
+
+ return (cnt);
+}
+
+
+/*
+ * Write USB Endpoint Data
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * cnt: Number of bytes to write
+ * Return Value: Number of bytes written
+ */
+
+uint32_t USB_WriteEP (uint32_t EPNum, uint8_t *pData, uint32_t cnt) {
+ uint32_t n;
+
+ USB->USBCtrl = ((EPNum & 0x0F) << 2) | CTRL_WR_EN;
+
+ USB->USBTxPLen = cnt;
+
+ for (n = 0; n < (cnt + 3) / 4; n++) {
+ USB->USBTxData = *((__packed uint32_t *)pData);
+ pData += 4;
+ }
+ USB->USBCtrl = 0;
+ WrCmdEP(EPNum, CMD_VALID_BUF);
+ return (cnt);
+}
+
+#if USB_DMA
+
+/* DMA Descriptor Memory Layout */
+const uint32_t DDAdr[2] = { DD_NISO_ADR, DD_ISO_ADR };
+const uint32_t DDSz [2] = { 16, 20 };
+
+
+/*
+ * Setup USB DMA Transfer for selected Endpoint
+ * Parameters: EPNum: Endpoint Number
+ * pDD: Pointer to DMA Descriptor
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+uint32_t USB_DMA_Setup(uint32_t EPNum, USB_DMA_DESCRIPTOR *pDD) {
+ uint32_t num, ptr, nxt, iso, n;
+
+ iso = pDD->Cfg.Type.IsoEP; /* Iso or Non-Iso Descriptor */
+ num = EPAdr(EPNum); /* Endpoint's Physical Address */
+
+ ptr = 0; /* Current Descriptor */
+ nxt = udca[num]; /* Initial Descriptor */
+ while (nxt) { /* Go through Descriptor List */
+ ptr = nxt; /* Current Descriptor */
+ if (!pDD->Cfg.Type.Link) { /* Check for Linked Descriptors */
+ n = (ptr - DDAdr[iso]) / DDSz[iso]; /* Descriptor Index */
+ DDMemMap[iso] &= ~(1 << n); /* Unmark Memory Usage */
+ }
+ nxt = *((uint32_t *)ptr); /* Next Descriptor */
+ }
+
+ for (n = 0; n < 32; n++) { /* Search for available Memory */
+ if ((DDMemMap[iso] & (1 << n)) == 0) {
+ break; /* Memory found */
+ }
+ }
+ if (n == 32) return (FALSE); /* Memory not available */
+
+ DDMemMap[iso] |= 1 << n; /* Mark Memory Usage */
+ nxt = DDAdr[iso] + n * DDSz[iso]; /* Next Descriptor */
+
+ if (ptr && pDD->Cfg.Type.Link) {
+ *((uint32_t *)(ptr + 0)) = nxt; /* Link in new Descriptor */
+ *((uint32_t *)(ptr + 4)) |= 0x00000004; /* Next DD is Valid */
+ } else {
+ udca[num] = nxt; /* Save new Descriptor */
+ UDCA[num] = nxt; /* Update UDCA in USB */
+ }
+
+ /* Fill in DMA Descriptor */
+ *(((uint32_t *)nxt)++) = 0; /* Next DD Pointer */
+ *(((uint32_t *)nxt)++) = pDD->Cfg.Type.ATLE |
+ (pDD->Cfg.Type.IsoEP << 4) |
+ (pDD->MaxSize << 5) |
+ (pDD->BufLen << 16);
+ *(((uint32_t *)nxt)++) = pDD->BufAdr;
+ *(((uint32_t *)nxt)++) = pDD->Cfg.Type.LenPos << 8;
+ if (iso) {
+ *((uint32_t *)nxt) = pDD->InfoAdr;
+ }
+
+ return (TRUE); /* Success */
+}
+
+
+/*
+ * Enable USB DMA Endpoint
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USB_DMA_Enable (uint32_t EPNum) {
+ USB->USBEpDMAEn = 1 << EPAdr(EPNum);
+}
+
+
+/*
+ * Disable USB DMA Endpoint
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USB_DMA_Disable (uint32_t EPNum) {
+ USB->USBEpDMADis = 1 << EPAdr(EPNum);
+}
+
+
+/*
+ * Get USB DMA Endpoint Status
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: DMA Status
+ */
+
+uint32_t USB_DMA_Status (uint32_t EPNum) {
+ uint32_t ptr, val;
+
+ ptr = UDCA[EPAdr(EPNum)]; /* Current Descriptor */
+ if (ptr == 0)
+ return (USB_DMA_INVALID);
+
+ val = *((uint32_t *)(ptr + 3*4)); /* Status Information */
+ switch ((val >> 1) & 0x0F) {
+ case 0x00: /* Not serviced */
+ return (USB_DMA_IDLE);
+ case 0x01: /* Being serviced */
+ return (USB_DMA_BUSY);
+ case 0x02: /* Normal Completition */
+ return (USB_DMA_DONE);
+ case 0x03: /* Data Under Run */
+ return (USB_DMA_UNDER_RUN);
+ case 0x08: /* Data Over Run */
+ return (USB_DMA_OVER_RUN);
+ case 0x09: /* System Error */
+ return (USB_DMA_ERROR);
+ }
+
+ return (USB_DMA_UNKNOWN);
+}
+
+
+/*
+ * Get USB DMA Endpoint Current Buffer Address
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: DMA Address (or -1 when DMA is Invalid)
+ */
+
+uint32_t USB_DMA_BufAdr (uint32_t EPNum) {
+ uint32_t ptr, val;
+
+ ptr = UDCA[EPAdr(EPNum)]; /* Current Descriptor */
+ if (ptr == 0)
+ {
+ return ((uint32_t)(-1)); /* DMA Invalid */
+ }
+
+ val = *((uint32_t *)(ptr + 2*4)); /* Buffer Address */
+ return (val); /* Current Address */
+}
+
+
+/*
+ * Get USB DMA Endpoint Current Buffer Count
+ * Number of transfered Bytes or Iso Packets
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: DMA Count (or -1 when DMA is Invalid)
+ */
+
+uint32_t USB_DMA_BufCnt (uint32_t EPNum) {
+ uint32_t ptr, val;
+
+ ptr = UDCA[EPAdr(EPNum)]; /* Current Descriptor */
+ if (ptr == 0)
+ {
+ return ((uint32_t)(-1)); /* DMA Invalid */
+ }
+ val = *((uint32_t *)(ptr + 3*4)); /* Status Information */
+ return (val >> 16); /* Current Count */
+}
+
+
+#endif /* USB_DMA */
+
+
+/*
+ * Get USB Last Frame Number
+ * Parameters: None
+ * Return Value: Frame Number
+ */
+
+uint32_t USB_GetFrame (void) {
+ uint32_t val;
+
+ WrCmd(CMD_RD_FRAME);
+ val = RdCmdDat(DAT_RD_FRAME);
+ val = val | (RdCmdDat(DAT_RD_FRAME) << 8);
+
+ return (val);
+}
+
+
+/*
+ * USB Interrupt Service Routine
+ */
+
+void USB_IRQHandler (void) {
+ uint32_t disr, val, n, m;
+ uint32_t episr, episrCur;
+
+ disr = USB->USBDevIntSt; /* Device Interrupt Status */
+
+ /* Device Status Interrupt (Reset, Connect change, Suspend/Resume) */
+ if (disr & DEV_STAT_INT) {
+ USB->USBDevIntClr = DEV_STAT_INT;
+ WrCmd(CMD_GET_DEV_STAT);
+ val = RdCmdDat(DAT_GET_DEV_STAT); /* Device Status */
+ if (val & DEV_RST) { /* Reset */
+ USB_Reset();
+#if USB_RESET_EVENT
+ USB_Reset_Event();
+#endif
+ }
+ if (val & DEV_CON_CH) { /* Connect change */
+#if USB_POWER_EVENT
+ USB_Power_Event(val & DEV_CON);
+#endif
+ }
+ if (val & DEV_SUS_CH) { /* Suspend/Resume */
+ if (val & DEV_SUS) { /* Suspend */
+ USB_Suspend();
+#if USB_SUSPEND_EVENT
+ USB_Suspend_Event();
+#endif
+ } else { /* Resume */
+ USB_Resume();
+#if USB_RESUME_EVENT
+ USB_Resume_Event();
+#endif
+ }
+ }
+ goto isr_end;
+ }
+
+#if USB_SOF_EVENT
+ /* Start of Frame Interrupt */
+ if (disr & FRAME_INT) {
+ USB_SOF_Event();
+ }
+#endif
+
+#if USB_ERROR_EVENT
+ /* Error Interrupt */
+ if (disr & ERR_INT) {
+ WrCmd(CMD_RD_ERR_STAT);
+ val = RdCmdDat(DAT_RD_ERR_STAT);
+ USB_Error_Event(val);
+ }
+#endif
+
+ /* Endpoint's Slow Interrupt */
+ if (disr & EP_SLOW_INT) {
+ episrCur = 0;
+ episr = USB->USBEpIntSt;
+ for (n = 0; n < USB_EP_NUM; n++) { /* Check All Endpoints */
+ if (episr == episrCur) break; /* break if all EP interrupts handled */
+ if (episr & (1 << n)) {
+ episrCur |= (1 << n);
+ m = n >> 1;
+
+ USB->USBEpIntClr = (1 << n);
+ while ((USB->USBDevIntSt & CDFULL_INT) == 0);
+ val = USB->USBCmdData;
+
+ if ((n & 1) == 0) { /* OUT Endpoint */
+ if (n == 0) { /* Control OUT Endpoint */
+ if (val & EP_SEL_STP) { /* Setup Packet */
+ if (USB_P_EP[0]) {
+ USB_P_EP[0](USB_EVT_SETUP);
+ continue;
+ }
+ }
+ }
+ if (USB_P_EP[m]) {
+ USB_P_EP[m](USB_EVT_OUT);
+ }
+ } else { /* IN Endpoint */
+ if (USB_P_EP[m]) {
+ USB_P_EP[m](USB_EVT_IN);
+ }
+ }
+ }
+ }
+ USB->USBDevIntClr = EP_SLOW_INT;
+ }
+
+#if USB_DMA
+
+ if (USB->USBDMAIntSt & 0x00000001) { /* End of Transfer Interrupt */
+ val = USB->USBEoTIntSt;
+ for (n = 2; n < USB_EP_NUM; n++) { /* Check All Endpoints */
+ if (val & (1 << n)) {
+ m = n >> 1;
+ if ((n & 1) == 0) { /* OUT Endpoint */
+ if (USB_P_EP[m]) {
+ USB_P_EP[m](USB_EVT_OUT_DMA_EOT);
+ }
+ } else { /* IN Endpoint */
+ if (USB_P_EP[m]) {
+ USB_P_EP[m](USB_EVT_IN_DMA_EOT);
+ }
+ }
+ }
+ }
+ USB->USBEoTIntClr = val;
+ }
+
+ if (USB->USBDMAIntSt & 0x00000002) { /* New DD Request Interrupt */
+ val = USB->USBNDDRIntSt;
+ for (n = 2; n < USB_EP_NUM; n++) { /* Check All Endpoints */
+ if (val & (1 << n)) {
+ m = n >> 1;
+ if ((n & 1) == 0) { /* OUT Endpoint */
+ if (USB_P_EP[m]) {
+ USB_P_EP[m](USB_EVT_OUT_DMA_NDR);
+ }
+ } else { /* IN Endpoint */
+ if (USB_P_EP[m]) {
+ USB_P_EP[m](USB_EVT_IN_DMA_NDR);
+ }
+ }
+ }
+ }
+ USB->USBNDDRIntClr = val;
+ }
+
+ if (USB->USBDMAIntSt & 0x00000004) { /* System Error Interrupt */
+ val = USB->USBSysErrIntSt;
+ for (n = 2; n < USB_EP_NUM; n++) { /* Check All Endpoints */
+ if (val & (1 << n)) {
+ m = n >> 1;
+ if ((n & 1) == 0) { /* OUT Endpoint */
+ if (USB_P_EP[m]) {
+ USB_P_EP[m](USB_EVT_OUT_DMA_ERR);
+ }
+ } else { /* IN Endpoint */
+ if (USB_P_EP[m]) {
+ USB_P_EP[m](USB_EVT_IN_DMA_ERR);
+ }
+ }
+ }
+ }
+ USB->USBSysErrIntClr = val;
+ }
+
+#endif /* USB_DMA */
+
+isr_end:
+ return;
+}
-/*----------------------------------------------------------------------------\r
- * U S B - K e r n e l\r
- *----------------------------------------------------------------------------\r
- * Name: usbhw.h\r
- * Purpose: USB Hardware Layer Definitions\r
- * Version: V1.20\r
- *----------------------------------------------------------------------------\r
- * This software is supplied "AS IS" without any warranties, express,\r
- * implied or statutory, including but not limited to the implied\r
- * warranties of fitness for purpose, satisfactory quality and\r
- * noninfringement. Keil extends you a royalty-free right to reproduce\r
- * and distribute executable files created using this software for use\r
- * on NXP Semiconductors LPC family microcontroller devices only. Nothing\r
- * else gives you the right to use this software.\r
- *\r
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
- *----------------------------------------------------------------------------\r
- * History:\r
- * V1.20 Added USB_ClearEPBuf\r
- * V1.00 Initial Version\r
- *----------------------------------------------------------------------------*/\r
-\r
-#ifndef __USBHW_H__\r
-#define __USBHW_H__\r
-#include "lpc_types.h"\r
-\r
-/* USB RAM Definitions */\r
-#define USB_RAM_ADR 0x20080000 /* USB RAM Start Address */\r
-#define USB_RAM_SZ 0x00004000 /* USB RAM Size (4kB) */\r
-\r
-/* DMA Endpoint Descriptors */\r
-#define DD_NISO_CNT 16 /* Non-Iso EP DMA Descr. Count (max. 32) */\r
-#define DD_ISO_CNT 8 /* Iso EP DMA Descriptor Count (max. 32) */\r
-#define DD_NISO_SZ (DD_NISO_CNT * 16) /* Non-Iso DMA Descr. Size */\r
-#define DD_ISO_SZ (DD_ISO_CNT * 20) /* Iso DMA Descriptor Size */\r
-#define DD_NISO_ADR (USB_RAM_ADR + 128) /* Non-Iso DMA Descr. Address */\r
-#define DD_ISO_ADR (DD_NISO_ADR + DD_NISO_SZ) /* Iso DMA Descr. Address */\r
-#define DD_SZ (128 + DD_NISO_SZ + DD_ISO_SZ) /* Descr. Size */\r
-\r
-/* DMA Buffer Memory Definitions */\r
-#define DMA_BUF_ADR (USB_RAM_ADR + DD_SZ) /* DMA Buffer Start Address */\r
-#define DMA_BUF_SZ (USB_RAM_SZ - DD_SZ) /* DMA Buffer Size */\r
-\r
-/* USB Error Codes */\r
-#define USB_ERR_PID 0x0001 /* PID Error */\r
-#define USB_ERR_UEPKT 0x0002 /* Unexpected Packet */\r
-#define USB_ERR_DCRC 0x0004 /* Data CRC Error */\r
-#define USB_ERR_TIMOUT 0x0008 /* Bus Time-out Error */\r
-#define USB_ERR_EOP 0x0010 /* End of Packet Error */\r
-#define USB_ERR_B_OVRN 0x0020 /* Buffer Overrun */\r
-#define USB_ERR_BTSTF 0x0040 /* Bit Stuff Error */\r
-#define USB_ERR_TGL 0x0080 /* Toggle Bit Error */\r
-\r
-/* USB DMA Status Codes */\r
-#define USB_DMA_INVALID 0x0000 /* DMA Invalid - Not Configured */\r
-#define USB_DMA_IDLE 0x0001 /* DMA Idle - Waiting for Trigger */\r
-#define USB_DMA_BUSY 0x0002 /* DMA Busy - Transfer in progress */\r
-#define USB_DMA_DONE 0x0003 /* DMA Transfer Done (no Errors)*/\r
-#define USB_DMA_OVER_RUN 0x0004 /* Data Over Run */\r
-#define USB_DMA_UNDER_RUN 0x0005 /* Data Under Run (Short Packet) */\r
-#define USB_DMA_ERROR 0x0006 /* Error */\r
-#define USB_DMA_UNKNOWN 0xFFFF /* Unknown State */\r
-\r
-/* USB DMA Descriptor */\r
-typedef struct _USB_DMA_DESCRIPTOR {\r
- uint32_t BufAdr; /* DMA Buffer Address */\r
- uint16_t BufLen; /* DMA Buffer Length */\r
- uint16_t MaxSize; /* Maximum Packet Size */\r
- uint32_t InfoAdr; /* Packet Info Memory Address */\r
- union { /* DMA Configuration */\r
- struct {\r
- uint32_t Link : 1; /* Link to existing Descriptors */\r
- uint32_t IsoEP : 1; /* Isonchronous Endpoint */\r
- uint32_t ATLE : 1; /* ATLE (Auto Transfer Length Extract) */\r
- uint32_t Rsrvd : 5; /* Reserved */\r
- uint32_t LenPos : 8; /* Length Position (ATLE) */\r
- } Type;\r
- uint32_t Val;\r
- } Cfg;\r
-} USB_DMA_DESCRIPTOR;\r
-\r
-/* USB Hardware Functions */\r
-extern void USB_Init (void);\r
-extern void USB_Connect (uint32_t con);\r
-extern void USB_Reset (void);\r
-extern void USB_Suspend (void);\r
-extern void USB_Resume (void);\r
-extern void USB_WakeUp (void);\r
-extern void USB_WakeUpCfg (uint32_t cfg);\r
-extern void USB_SetAddress (uint32_t adr);\r
-extern void USB_Configure (uint32_t cfg);\r
-extern void USB_ConfigEP (USB_ENDPOINT_DESCRIPTOR *pEPD);\r
-extern void USB_DirCtrlEP (uint32_t dir);\r
-extern void USB_EnableEP (uint32_t EPNum);\r
-extern void USB_DisableEP (uint32_t EPNum);\r
-extern void USB_ResetEP (uint32_t EPNum);\r
-extern void USB_SetStallEP (uint32_t EPNum);\r
-extern void USB_ClrStallEP (uint32_t EPNum);\r
-extern void USB_ClearEPBuf (uint32_t EPNum);\r
-extern uint32_t USB_ReadEP (uint32_t EPNum, uint8_t *pData);\r
-extern uint32_t USB_WriteEP (uint32_t EPNum, uint8_t *pData, uint32_t cnt);\r
-extern uint32_t USB_DMA_Setup (uint32_t EPNum, USB_DMA_DESCRIPTOR *pDD);\r
-extern void USB_DMA_Enable (uint32_t EPNum);\r
-extern void USB_DMA_Disable(uint32_t EPNum);\r
-extern uint32_t USB_DMA_Status (uint32_t EPNum);\r
-extern uint32_t USB_DMA_BufAdr (uint32_t EPNum);\r
-extern uint32_t USB_DMA_BufCnt (uint32_t EPNum);\r
-extern uint32_t USB_GetFrame (void);\r
-extern void USB_IRQHandler (void);\r
-\r
-\r
-#endif /* __USBHW_H__ */\r
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: usbhw.h
+ * Purpose: USB Hardware Layer Definitions
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC family microcontroller devices only. Nothing
+ * else gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *----------------------------------------------------------------------------
+ * History:
+ * V1.20 Added USB_ClearEPBuf
+ * V1.00 Initial Version
+ *----------------------------------------------------------------------------*/
+
+#ifndef __USBHW_H__
+#define __USBHW_H__
+#include "lpc_types.h"
+
+/* USB RAM Definitions */
+#define USB_RAM_ADR 0x20080000 /* USB RAM Start Address */
+#define USB_RAM_SZ 0x00004000 /* USB RAM Size (4kB) */
+
+/* DMA Endpoint Descriptors */
+#define DD_NISO_CNT 16 /* Non-Iso EP DMA Descr. Count (max. 32) */
+#define DD_ISO_CNT 8 /* Iso EP DMA Descriptor Count (max. 32) */
+#define DD_NISO_SZ (DD_NISO_CNT * 16) /* Non-Iso DMA Descr. Size */
+#define DD_ISO_SZ (DD_ISO_CNT * 20) /* Iso DMA Descriptor Size */
+#define DD_NISO_ADR (USB_RAM_ADR + 128) /* Non-Iso DMA Descr. Address */
+#define DD_ISO_ADR (DD_NISO_ADR + DD_NISO_SZ) /* Iso DMA Descr. Address */
+#define DD_SZ (128 + DD_NISO_SZ + DD_ISO_SZ) /* Descr. Size */
+
+/* DMA Buffer Memory Definitions */
+#define DMA_BUF_ADR (USB_RAM_ADR + DD_SZ) /* DMA Buffer Start Address */
+#define DMA_BUF_SZ (USB_RAM_SZ - DD_SZ) /* DMA Buffer Size */
+
+/* USB Error Codes */
+#define USB_ERR_PID 0x0001 /* PID Error */
+#define USB_ERR_UEPKT 0x0002 /* Unexpected Packet */
+#define USB_ERR_DCRC 0x0004 /* Data CRC Error */
+#define USB_ERR_TIMOUT 0x0008 /* Bus Time-out Error */
+#define USB_ERR_EOP 0x0010 /* End of Packet Error */
+#define USB_ERR_B_OVRN 0x0020 /* Buffer Overrun */
+#define USB_ERR_BTSTF 0x0040 /* Bit Stuff Error */
+#define USB_ERR_TGL 0x0080 /* Toggle Bit Error */
+
+/* USB DMA Status Codes */
+#define USB_DMA_INVALID 0x0000 /* DMA Invalid - Not Configured */
+#define USB_DMA_IDLE 0x0001 /* DMA Idle - Waiting for Trigger */
+#define USB_DMA_BUSY 0x0002 /* DMA Busy - Transfer in progress */
+#define USB_DMA_DONE 0x0003 /* DMA Transfer Done (no Errors)*/
+#define USB_DMA_OVER_RUN 0x0004 /* Data Over Run */
+#define USB_DMA_UNDER_RUN 0x0005 /* Data Under Run (Short Packet) */
+#define USB_DMA_ERROR 0x0006 /* Error */
+#define USB_DMA_UNKNOWN 0xFFFF /* Unknown State */
+
+/* USB DMA Descriptor */
+typedef struct _USB_DMA_DESCRIPTOR {
+ uint32_t BufAdr; /* DMA Buffer Address */
+ uint16_t BufLen; /* DMA Buffer Length */
+ uint16_t MaxSize; /* Maximum Packet Size */
+ uint32_t InfoAdr; /* Packet Info Memory Address */
+ union { /* DMA Configuration */
+ struct {
+ uint32_t Link : 1; /* Link to existing Descriptors */
+ uint32_t IsoEP : 1; /* Isonchronous Endpoint */
+ uint32_t ATLE : 1; /* ATLE (Auto Transfer Length Extract) */
+ uint32_t Rsrvd : 5; /* Reserved */
+ uint32_t LenPos : 8; /* Length Position (ATLE) */
+ } Type;
+ uint32_t Val;
+ } Cfg;
+} USB_DMA_DESCRIPTOR;
+
+/* USB Hardware Functions */
+extern void USB_Init (void);
+extern void USB_Connect (uint32_t con);
+extern void USB_Reset (void);
+extern void USB_Suspend (void);
+extern void USB_Resume (void);
+extern void USB_WakeUp (void);
+extern void USB_WakeUpCfg (uint32_t cfg);
+extern void USB_SetAddress (uint32_t adr);
+extern void USB_Configure (uint32_t cfg);
+extern void USB_ConfigEP (USB_ENDPOINT_DESCRIPTOR *pEPD);
+extern void USB_DirCtrlEP (uint32_t dir);
+extern void USB_EnableEP (uint32_t EPNum);
+extern void USB_DisableEP (uint32_t EPNum);
+extern void USB_ResetEP (uint32_t EPNum);
+extern void USB_SetStallEP (uint32_t EPNum);
+extern void USB_ClrStallEP (uint32_t EPNum);
+extern void USB_ClearEPBuf (uint32_t EPNum);
+extern uint32_t USB_ReadEP (uint32_t EPNum, uint8_t *pData);
+extern uint32_t USB_WriteEP (uint32_t EPNum, uint8_t *pData, uint32_t cnt);
+extern uint32_t USB_DMA_Setup (uint32_t EPNum, USB_DMA_DESCRIPTOR *pDD);
+extern void USB_DMA_Enable (uint32_t EPNum);
+extern void USB_DMA_Disable(uint32_t EPNum);
+extern uint32_t USB_DMA_Status (uint32_t EPNum);
+extern uint32_t USB_DMA_BufAdr (uint32_t EPNum);
+extern uint32_t USB_DMA_BufCnt (uint32_t EPNum);
+extern uint32_t USB_GetFrame (void);
+extern void USB_IRQHandler (void);
+
+
+#endif /* __USBHW_H__ */
+++ /dev/null
-; \r
-; Keil - An ARM Company Comunication Device Class driver installation file\r
-; (C)2007 Copyright \r
-;\r
-\r
-[Version] \r
-Signature="$Windows NT$" \r
-Class=Ports\r
-ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318} \r
-Provider=%Keil% \r
-;LayoutFile=layout.inf\r
-DriverVer=01/06/07\r
-\r
-[Manufacturer] \r
-%Keil%=DeviceList\r
-\r
-[DestinationDirs] \r
-DefaultDestDir=12 \r
-\r
-[SourceDisksFiles]\r
-\r
-[SourceDisksNames]\r
-\r
-[DeviceList] \r
-%DESCRIPTION%=LPC17xxUSB, USB\VID_1FC9&PID_2002 \r
-\r
-;------------------------------------------------------------------------------\r
-; Windows 2000/XP Sections\r
-;------------------------------------------------------------------------------\r
-\r
-[LPC17xxUSB.nt] \r
-include=mdmcpq.inf\r
-CopyFiles=DriverCopyFiles\r
-AddReg=LPC17xxUSB.nt.AddReg \r
-\r
-[DriverCopyFiles]\r
-usbser.sys,,,0x20\r
-\r
-[LPC17xxUSB.nt.AddReg] \r
-HKR,,DevLoader,,*ntkern \r
-HKR,,NTMPDriver,,usbser.sys \r
-HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" \r
-\r
-[LPC17xxUSB.nt.Services] \r
-include=mdmcpq.inf\r
-AddService=usbser, 0x00000002, DriverService\r
-\r
-\r
-[LPC17xxUSB.nt.HW]\r
-include=mdmcpq.inf\r
-\r
-[DriverService] \r
-DisplayName=%DESCRIPTION% \r
-ServiceType=1\r
-StartType=3\r
-ErrorControl=1\r
-ServiceBinary=%12%\usbser.sys \r
-\r
-;------------------------------------------------------------------------------\r
-; String Definitions\r
-;------------------------------------------------------------------------------\r
-\r
-[Strings] \r
-NXP="NXP - Founded by Philips"\r
-DESCRIPTION="LPC17xx USB VCom Port" \r
-/***********************************************************************//**\r
- * @file lpc17xx_libcfg.h\r
- * @purpose Library configuration file\r
- * @version 2.0\r
- * @date 21. May. 2010\r
- * @author NXP MCU SW Application Team\r
- **************************************************************************\r
- * Software that is described herein is for illustrative purposes only\r
- * which provides customers with programming information regarding the\r
- * products. This software is supplied "AS IS" without any warranties.\r
- * NXP Semiconductors assumes no responsibility or liability for the\r
- * use of the software, conveys no license or title under any patent,\r
- * copyright, or mask work right to the product. NXP Semiconductors\r
- * reserves the right to make changes in the software without\r
- * notification. NXP Semiconductors also make no representation or\r
- * warranty that such application will be suitable for the specified\r
- * use without further testing or modification.\r
- **************************************************************************/\r
-\r
-#ifndef LPC17XX_LIBCFG_H_\r
-#define LPC17XX_LIBCFG_H_\r
-\r
-#include "lpc_types.h"\r
-\r
-\r
-/************************** DEBUG MODE DEFINITIONS *********************************/\r
-/* Un-comment the line below to compile the library in DEBUG mode, this will expanse\r
- the "CHECK_PARAM" macro in the FW library code */\r
-\r
-#define DEBUG\r
-\r
-\r
-/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/\r
-\r
-/* Comment the line below to disable the specific peripheral inclusion */\r
-\r
-/* DEBUG_FRAMWORK -------------------- */\r
-///#define _DBGFWK\r
-\r
-/* GPIO ------------------------------- */\r
-//#define _GPIO\r
-\r
-/* EXTI ------------------------------- */\r
-//#define _EXTI\r
-\r
-/* UART ------------------------------- */\r
-//#define _UART\r
-//#define _UART0\r
-//#define _UART1\r
-//#define _UART2\r
-//#define _UART3\r
-\r
-/* SPI ------------------------------- */\r
-//#define _SPI\r
-\r
-/* SYSTICK --------------------------- */\r
-//#define _SYSTICK\r
-\r
-/* SSP ------------------------------- */\r
-//#define _SSP\r
-//#define _SSP0\r
-//#define _SSP1\r
-\r
-\r
-/* I2C ------------------------------- */\r
-//#define _I2C\r
-//#define _I2C0\r
-//#define _I2C1\r
-//#define _I2C2\r
-\r
-/* TIMER ------------------------------- */\r
-//#define _TIM\r
-\r
-/* WDT ------------------------------- */\r
-//#define _WDT\r
-\r
-\r
-/* GPDMA ------------------------------- */\r
-//#define _GPDMA\r
-\r
-\r
-/* DAC ------------------------------- */\r
-//#define _DAC\r
-\r
-/* DAC ------------------------------- */\r
-//#define _ADC\r
-\r
-\r
-/* PWM ------------------------------- */\r
-//#define _PWM\r
-//#define _PWM1\r
-\r
-/* RTC ------------------------------- */\r
-//#define _RTC\r
-\r
-/* I2S ------------------------------- */\r
-//#define _I2S\r
-\r
-/* USB device ------------------------------- */\r
-//#define _USBDEV\r
-//#define _USB_DMA\r
-\r
-/* QEI ------------------------------- */\r
-//#define _QEI\r
-\r
-/* MCPWM ------------------------------- */\r
-//#define _MCPWM\r
-\r
-/* CAN--------------------------------*/\r
-//#define _CAN\r
-\r
-/* RIT ------------------------------- */\r
-//#define _RIT\r
-\r
-/* EMAC ------------------------------ */\r
-//#define _EMAC\r
-\r
-/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/\r
-\r
-#ifdef DEBUG\r
-/*******************************************************************************\r
-* @brief The CHECK_PARAM macro is used for function's parameters check.\r
-* It is used only if the library is compiled in DEBUG mode.\r
-* @param[in] expr - If expr is false, it calls check_failed() function\r
-* which reports the name of the source file and the source\r
-* line number of the call that failed.\r
-* - If expr is true, it returns no value.\r
-* @return None\r
-*******************************************************************************/\r
-#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))\r
-#else\r
-#define CHECK_PARAM(expr)\r
-#endif /* DEBUG */\r
-\r
-\r
-\r
-/************************** GLOBAL/PUBLIC FUNCTION DECLARATION *********************************/\r
-\r
-#ifdef DEBUG\r
-void check_failed(uint8_t *file, uint32_t line);\r
-#endif\r
-\r
-\r
-#endif /* LPC17XX_LIBCFG_H_ */\r
+/***********************************************************************//**
+ * @file lpc17xx_libcfg.h
+ * @purpose Library configuration file
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+#ifndef LPC17XX_LIBCFG_H_
+#define LPC17XX_LIBCFG_H_
+
+#include "lpc_types.h"
+
+
+/************************** DEBUG MODE DEFINITIONS *********************************/
+/* Un-comment the line below to compile the library in DEBUG mode, this will expanse
+ the "CHECK_PARAM" macro in the FW library code */
+
+#define DEBUG
+
+
+/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/
+
+/* Comment the line below to disable the specific peripheral inclusion */
+
+/* DEBUG_FRAMWORK -------------------- */
+///#define _DBGFWK
+
+/* GPIO ------------------------------- */
+//#define _GPIO
+
+/* EXTI ------------------------------- */
+//#define _EXTI
+
+/* UART ------------------------------- */
+//#define _UART
+//#define _UART0
+//#define _UART1
+//#define _UART2
+//#define _UART3
+
+/* SPI ------------------------------- */
+//#define _SPI
+
+/* SYSTICK --------------------------- */
+//#define _SYSTICK
+
+/* SSP ------------------------------- */
+//#define _SSP
+//#define _SSP0
+//#define _SSP1
+
+
+/* I2C ------------------------------- */
+//#define _I2C
+//#define _I2C0
+//#define _I2C1
+//#define _I2C2
+
+/* TIMER ------------------------------- */
+//#define _TIM
+
+/* WDT ------------------------------- */
+//#define _WDT
+
+
+/* GPDMA ------------------------------- */
+//#define _GPDMA
+
+
+/* DAC ------------------------------- */
+//#define _DAC
+
+/* DAC ------------------------------- */
+//#define _ADC
+
+
+/* PWM ------------------------------- */
+//#define _PWM
+//#define _PWM1
+
+/* RTC ------------------------------- */
+//#define _RTC
+
+/* I2S ------------------------------- */
+//#define _I2S
+
+/* USB device ------------------------------- */
+//#define _USBDEV
+//#define _USB_DMA
+
+/* QEI ------------------------------- */
+//#define _QEI
+
+/* MCPWM ------------------------------- */
+//#define _MCPWM
+
+/* CAN--------------------------------*/
+//#define _CAN
+
+/* RIT ------------------------------- */
+//#define _RIT
+
+/* EMAC ------------------------------ */
+//#define _EMAC
+
+/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/
+
+#ifdef DEBUG
+/*******************************************************************************
+* @brief The CHECK_PARAM macro is used for function's parameters check.
+* It is used only if the library is compiled in DEBUG mode.
+* @param[in] expr - If expr is false, it calls check_failed() function
+* which reports the name of the source file and the source
+* line number of the call that failed.
+* - If expr is true, it returns no value.
+* @return None
+*******************************************************************************/
+#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))
+#else
+#define CHECK_PARAM(expr)
+#endif /* DEBUG */
+
+
+
+/************************** GLOBAL/PUBLIC FUNCTION DECLARATION *********************************/
+
+#ifdef DEBUG
+void check_failed(uint8_t *file, uint32_t line);
+#endif
+
+
+#endif /* LPC17XX_LIBCFG_H_ */
-/***********************************************************************//**\r
- * @file lpc_types.h\r
- * @brief Contains the NXP ABL typedefs for C standard types.\r
- * It is intended to be used in ISO C conforming development\r
- * environments and checks for this insofar as it is possible\r
- * to do so.\r
- * @version 1.0\r
- * @date 27 Jul. 2008\r
- * @author wellsk\r
- **************************************************************************\r
- * Software that is described herein is for illustrative purposes only\r
- * which provides customers with programming information regarding the\r
- * products. This software is supplied "AS IS" without any warranties.\r
- * NXP Semiconductors assumes no responsibility or liability for the\r
- * use of the software, conveys no license or title under any patent,\r
- * copyright, or mask work right to the product. NXP Semiconductors\r
- * reserves the right to make changes in the software without\r
- * notification. NXP Semiconductors also make no representation or\r
- * warranty that such application will be suitable for the specified\r
- * use without further testing or modification.\r
- **************************************************************************/\r
-\r
-/* Type group ----------------------------------------------------------- */\r
-/** @defgroup LPC_Types LPC_Types\r
- * @ingroup LPC1700CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC_TYPES_H\r
-#define LPC_TYPES_H\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include <stdint.h>\r
-\r
-\r
-/* Public Types --------------------------------------------------------------- */\r
-/** @defgroup LPC_Types_Public_Types LPC_Types Public Types\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Boolean Type definition\r
- */\r
-typedef enum {FALSE = 0, TRUE = !FALSE} Bool;\r
-\r
-/**\r
- * @brief Flag Status and Interrupt Flag Status type definition\r
- */\r
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;\r
-#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))\r
-\r
-/**\r
- * @brief Functional State Definition\r
- */\r
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
-#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))\r
-\r
-/**\r
- * @ Status type definition\r
- */\r
-typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;\r
-\r
-\r
-/**\r
- * Read/Write transfer type mode (Block or non-block)\r
- */\r
-typedef enum\r
-{\r
- NONE_BLOCKING = 0, /**< None Blocking type */\r
- BLOCKING, /**< Blocking type */\r
-} TRANSFER_BLOCK_Type;\r
-\r
-\r
-/** Pointer to Function returning Void (any number of parameters) */\r
-typedef void (*PFV)();\r
-\r
-/** Pointer to Function returning int32_t (any number of parameters) */\r
-typedef int32_t(*PFI)();\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Macros -------------------------------------------------------------- */\r
-/** @defgroup LPC_Types_Public_Macros LPC_Types Public Macros\r
- * @{\r
- */\r
-\r
-/* _BIT(n) sets the bit at position "n"\r
- * _BIT(n) is intended to be used in "OR" and "AND" expressions:\r
- * e.g., "(_BIT(3) | _BIT(7))".\r
- */\r
-#undef _BIT\r
-/* Set bit macro */\r
-#define _BIT(n) (1<<n)\r
-\r
-/* _SBF(f,v) sets the bit field starting at position "f" to value "v".\r
- * _SBF(f,v) is intended to be used in "OR" and "AND" expressions:\r
- * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"\r
- */\r
-#undef _SBF\r
-/* Set bit field macro */\r
-#define _SBF(f,v) (v<<f)\r
-\r
-/* _BITMASK constructs a symbol with 'field_width' least significant\r
- * bits set.\r
- * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF\r
- * The symbol is intended to be used to limit the bit field width\r
- * thusly:\r
- * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.\r
- * If "any_expression" results in a value that is larger than can be\r
- * contained in 'x' bits, the bits above 'x - 1' are masked off. When\r
- * used with the _SBF example above, the example would be written:\r
- * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))\r
- * This ensures that the value written to a_reg is no wider than\r
- * 16 bits, and makes the code easier to read and understand.\r
- */\r
-#undef _BITMASK\r
-/* Bitmask creation macro */\r
-#define _BITMASK(field_width) ( _BIT(field_width) - 1)\r
-\r
-/* NULL pointer */\r
-#ifndef NULL\r
-#define NULL ((void*) 0)\r
-#endif\r
-\r
-/* Number of elements in an array */\r
-#define NELEMENTS(array) (sizeof (array) / sizeof (array[0]))\r
-\r
-/* Static data/function define */\r
-#define STATIC static\r
-/* External data/function define */\r
-#define EXTERN extern\r
-\r
-#define MAX(a, b) (((a) > (b)) ? (a) : (b))\r
-#define MIN(a, b) (((a) < (b)) ? (a) : (b))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Old Type Definition compatibility ------------------------------------------ */\r
-/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types\r
- * @{\r
- */\r
-\r
-/** SMA type for character type */\r
-typedef char CHAR;\r
-\r
-/** SMA type for 8 bit unsigned value */\r
-typedef uint8_t UNS_8;\r
-\r
-/** SMA type for 8 bit signed value */\r
-typedef int8_t INT_8;\r
-\r
-/** SMA type for 16 bit unsigned value */\r
-typedef uint16_t UNS_16;\r
-\r
-/** SMA type for 16 bit signed value */\r
-typedef int16_t INT_16;\r
-\r
-/** SMA type for 32 bit unsigned value */\r
-typedef uint32_t UNS_32;\r
-\r
-/** SMA type for 32 bit signed value */\r
-typedef int32_t INT_32;\r
-\r
-/** SMA type for 64 bit signed value */\r
-typedef int64_t INT_64;\r
-\r
-/** SMA type for 64 bit unsigned value */\r
-typedef uint64_t UNS_64;\r
-\r
-/** 32 bit boolean type */\r
-typedef Bool BOOL_32;\r
-\r
-/** 16 bit boolean type */\r
-typedef Bool BOOL_16;\r
-\r
-/** 8 bit boolean type */\r
-typedef Bool BOOL_8;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-#endif /* LPC_TYPES_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+/***********************************************************************//**
+ * @file lpc_types.h
+ * @brief Contains the NXP ABL typedefs for C standard types.
+ * It is intended to be used in ISO C conforming development
+ * environments and checks for this insofar as it is possible
+ * to do so.
+ * @version 1.0
+ * @date 27 Jul. 2008
+ * @author wellsk
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Type group ----------------------------------------------------------- */
+/** @defgroup LPC_Types LPC_Types
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC_TYPES_H
+#define LPC_TYPES_H
+
+/* Includes ------------------------------------------------------------------- */
+#include <stdint.h>
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup LPC_Types_Public_Types LPC_Types Public Types
+ * @{
+ */
+
+/**
+ * @brief Boolean Type definition
+ */
+typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
+
+/**
+ * @brief Flag Status and Interrupt Flag Status type definition
+ */
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
+#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))
+
+/**
+ * @brief Functional State Definition
+ */
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))
+
+/**
+ * @ Status type definition
+ */
+typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
+
+
+/**
+ * Read/Write transfer type mode (Block or non-block)
+ */
+typedef enum
+{
+ NONE_BLOCKING = 0, /**< None Blocking type */
+ BLOCKING, /**< Blocking type */
+} TRANSFER_BLOCK_Type;
+
+
+/** Pointer to Function returning Void (any number of parameters) */
+typedef void (*PFV)();
+
+/** Pointer to Function returning int32_t (any number of parameters) */
+typedef int32_t(*PFI)();
+
+/**
+ * @}
+ */
+
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup LPC_Types_Public_Macros LPC_Types Public Macros
+ * @{
+ */
+
+/* _BIT(n) sets the bit at position "n"
+ * _BIT(n) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "(_BIT(3) | _BIT(7))".
+ */
+#undef _BIT
+/* Set bit macro */
+#define _BIT(n) (1<<n)
+
+/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
+ * _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
+ */
+#undef _SBF
+/* Set bit field macro */
+#define _SBF(f,v) (v<<f)
+
+/* _BITMASK constructs a symbol with 'field_width' least significant
+ * bits set.
+ * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
+ * The symbol is intended to be used to limit the bit field width
+ * thusly:
+ * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
+ * If "any_expression" results in a value that is larger than can be
+ * contained in 'x' bits, the bits above 'x - 1' are masked off. When
+ * used with the _SBF example above, the example would be written:
+ * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
+ * This ensures that the value written to a_reg is no wider than
+ * 16 bits, and makes the code easier to read and understand.
+ */
+#undef _BITMASK
+/* Bitmask creation macro */
+#define _BITMASK(field_width) ( _BIT(field_width) - 1)
+
+/* NULL pointer */
+#ifndef NULL
+#define NULL ((void*) 0)
+#endif
+
+/* Number of elements in an array */
+#define NELEMENTS(array) (sizeof (array) / sizeof (array[0]))
+
+/* Static data/function define */
+#define STATIC static
+/* External data/function define */
+#define EXTERN extern
+
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+
+/**
+ * @}
+ */
+
+
+/* Old Type Definition compatibility ------------------------------------------ */
+/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types
+ * @{
+ */
+
+/** SMA type for character type */
+typedef char CHAR;
+
+/** SMA type for 8 bit unsigned value */
+typedef uint8_t UNS_8;
+
+/** SMA type for 8 bit signed value */
+typedef int8_t INT_8;
+
+/** SMA type for 16 bit unsigned value */
+typedef uint16_t UNS_16;
+
+/** SMA type for 16 bit signed value */
+typedef int16_t INT_16;
+
+/** SMA type for 32 bit unsigned value */
+typedef uint32_t UNS_32;
+
+/** SMA type for 32 bit signed value */
+typedef int32_t INT_32;
+
+/** SMA type for 64 bit signed value */
+typedef int64_t INT_64;
+
+/** SMA type for 64 bit unsigned value */
+typedef uint64_t UNS_64;
+
+/** 32 bit boolean type */
+typedef Bool BOOL_32;
+
+/** 16 bit boolean type */
+typedef Bool BOOL_16;
+
+/** 8 bit boolean type */
+typedef Bool BOOL_8;
+
+/**
+ * @}
+ */
+
+
+#endif /* LPC_TYPES_H */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
-/*----------------------------------------------------------------------------\r
- * U S B - K e r n e l\r
- *----------------------------------------------------------------------------\r
- * Name: usbreg.h\r
- * Purpose: USB Hardware Layer Definitions for NXP LPC Family MCUs\r
- * Version: V1.20\r
- *----------------------------------------------------------------------------\r
- * This software is supplied "AS IS" without any warranties, express,\r
- * implied or statutory, including but not limited to the implied\r
- * warranties of fitness for purpose, satisfactory quality and\r
- * noninfringement. Keil extends you a royalty-free right to reproduce\r
- * and distribute executable files created using this software for use\r
- * on NXP Semiconductors LPC family microcontroller devices only. Nothing \r
- * else gives you the right to use this software.\r
- *\r
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
- *---------------------------------------------------------------------------*/\r
-\r
-#ifndef __USBREG_H\r
-#define __USBREG_H\r
-\r
-/* Device Interrupt Bit Definitions */\r
-#define FRAME_INT 0x00000001\r
-#define EP_FAST_INT 0x00000002\r
-#define EP_SLOW_INT 0x00000004\r
-#define DEV_STAT_INT 0x00000008\r
-#define CCEMTY_INT 0x00000010\r
-#define CDFULL_INT 0x00000020\r
-#define RxENDPKT_INT 0x00000040\r
-#define TxENDPKT_INT 0x00000080\r
-#define EP_RLZED_INT 0x00000100\r
-#define ERR_INT 0x00000200\r
-\r
-/* Rx & Tx Packet Length Definitions */\r
-#define PKT_LNGTH_MASK 0x000003FF\r
-#define PKT_DV 0x00000400\r
-#define PKT_RDY 0x00000800\r
-\r
-/* USB Control Definitions */\r
-#define CTRL_RD_EN 0x00000001\r
-#define CTRL_WR_EN 0x00000002\r
-\r
-/* Command Codes */\r
-#define CMD_SET_ADDR 0x00D00500\r
-#define CMD_CFG_DEV 0x00D80500\r
-#define CMD_SET_MODE 0x00F30500\r
-#define CMD_RD_FRAME 0x00F50500\r
-#define DAT_RD_FRAME 0x00F50200\r
-#define CMD_RD_TEST 0x00FD0500\r
-#define DAT_RD_TEST 0x00FD0200\r
-#define CMD_SET_DEV_STAT 0x00FE0500\r
-#define CMD_GET_DEV_STAT 0x00FE0500\r
-#define DAT_GET_DEV_STAT 0x00FE0200\r
-#define CMD_GET_ERR_CODE 0x00FF0500\r
-#define DAT_GET_ERR_CODE 0x00FF0200\r
-#define CMD_RD_ERR_STAT 0x00FB0500\r
-#define DAT_RD_ERR_STAT 0x00FB0200\r
-#define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))\r
-#define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))\r
-#define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))\r
-#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))\r
-#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))\r
-#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))\r
-#define CMD_CLR_BUF 0x00F20500\r
-#define DAT_CLR_BUF 0x00F20200\r
-#define CMD_VALID_BUF 0x00FA0500\r
-\r
-/* Device Address Register Definitions */\r
-#define DEV_ADDR_MASK 0x7F\r
-#define DEV_EN 0x80\r
-\r
-/* Device Configure Register Definitions */\r
-#define CONF_DVICE 0x01\r
-\r
-/* Device Mode Register Definitions */\r
-#define AP_CLK 0x01\r
-#define INAK_CI 0x02\r
-#define INAK_CO 0x04\r
-#define INAK_II 0x08\r
-#define INAK_IO 0x10\r
-#define INAK_BI 0x20\r
-#define INAK_BO 0x40\r
-\r
-/* Device Status Register Definitions */\r
-#define DEV_CON 0x01\r
-#define DEV_CON_CH 0x02\r
-#define DEV_SUS 0x04\r
-#define DEV_SUS_CH 0x08\r
-#define DEV_RST 0x10\r
-\r
-/* Error Code Register Definitions */\r
-#define ERR_EC_MASK 0x0F\r
-#define ERR_EA 0x10\r
-\r
-/* Error Status Register Definitions */\r
-#define ERR_PID 0x01\r
-#define ERR_UEPKT 0x02\r
-#define ERR_DCRC 0x04\r
-#define ERR_TIMOUT 0x08\r
-#define ERR_EOP 0x10\r
-#define ERR_B_OVRN 0x20\r
-#define ERR_BTSTF 0x40\r
-#define ERR_TGL 0x80\r
-\r
-/* Endpoint Select Register Definitions */\r
-#define EP_SEL_F 0x01\r
-#define EP_SEL_ST 0x02\r
-#define EP_SEL_STP 0x04\r
-#define EP_SEL_PO 0x08\r
-#define EP_SEL_EPN 0x10\r
-#define EP_SEL_B_1_FULL 0x20\r
-#define EP_SEL_B_2_FULL 0x40\r
-\r
-/* Endpoint Status Register Definitions */\r
-#define EP_STAT_ST 0x01\r
-#define EP_STAT_DA 0x20\r
-#define EP_STAT_RF_MO 0x40\r
-#define EP_STAT_CND_ST 0x80\r
-\r
-/* Clear Buffer Register Definitions */\r
-#define CLR_BUF_PO 0x01\r
-\r
-\r
-/* DMA Interrupt Bit Definitions */\r
-#define EOT_INT 0x01\r
-#define NDD_REQ_INT 0x02\r
-#define SYS_ERR_INT 0x04\r
-\r
-\r
-#endif /* __USBREG_H */\r
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: usbreg.h
+ * Purpose: USB Hardware Layer Definitions for NXP LPC Family MCUs
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC family microcontroller devices only. Nothing
+ * else gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#ifndef __USBREG_H
+#define __USBREG_H
+
+/* Device Interrupt Bit Definitions */
+#define FRAME_INT 0x00000001
+#define EP_FAST_INT 0x00000002
+#define EP_SLOW_INT 0x00000004
+#define DEV_STAT_INT 0x00000008
+#define CCEMTY_INT 0x00000010
+#define CDFULL_INT 0x00000020
+#define RxENDPKT_INT 0x00000040
+#define TxENDPKT_INT 0x00000080
+#define EP_RLZED_INT 0x00000100
+#define ERR_INT 0x00000200
+
+/* Rx & Tx Packet Length Definitions */
+#define PKT_LNGTH_MASK 0x000003FF
+#define PKT_DV 0x00000400
+#define PKT_RDY 0x00000800
+
+/* USB Control Definitions */
+#define CTRL_RD_EN 0x00000001
+#define CTRL_WR_EN 0x00000002
+
+/* Command Codes */
+#define CMD_SET_ADDR 0x00D00500
+#define CMD_CFG_DEV 0x00D80500
+#define CMD_SET_MODE 0x00F30500
+#define CMD_RD_FRAME 0x00F50500
+#define DAT_RD_FRAME 0x00F50200
+#define CMD_RD_TEST 0x00FD0500
+#define DAT_RD_TEST 0x00FD0200
+#define CMD_SET_DEV_STAT 0x00FE0500
+#define CMD_GET_DEV_STAT 0x00FE0500
+#define DAT_GET_DEV_STAT 0x00FE0200
+#define CMD_GET_ERR_CODE 0x00FF0500
+#define DAT_GET_ERR_CODE 0x00FF0200
+#define CMD_RD_ERR_STAT 0x00FB0500
+#define DAT_RD_ERR_STAT 0x00FB0200
+#define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
+#define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
+#define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
+#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
+#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
+#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
+#define CMD_CLR_BUF 0x00F20500
+#define DAT_CLR_BUF 0x00F20200
+#define CMD_VALID_BUF 0x00FA0500
+
+/* Device Address Register Definitions */
+#define DEV_ADDR_MASK 0x7F
+#define DEV_EN 0x80
+
+/* Device Configure Register Definitions */
+#define CONF_DVICE 0x01
+
+/* Device Mode Register Definitions */
+#define AP_CLK 0x01
+#define INAK_CI 0x02
+#define INAK_CO 0x04
+#define INAK_II 0x08
+#define INAK_IO 0x10
+#define INAK_BI 0x20
+#define INAK_BO 0x40
+
+/* Device Status Register Definitions */
+#define DEV_CON 0x01
+#define DEV_CON_CH 0x02
+#define DEV_SUS 0x04
+#define DEV_SUS_CH 0x08
+#define DEV_RST 0x10
+
+/* Error Code Register Definitions */
+#define ERR_EC_MASK 0x0F
+#define ERR_EA 0x10
+
+/* Error Status Register Definitions */
+#define ERR_PID 0x01
+#define ERR_UEPKT 0x02
+#define ERR_DCRC 0x04
+#define ERR_TIMOUT 0x08
+#define ERR_EOP 0x10
+#define ERR_B_OVRN 0x20
+#define ERR_BTSTF 0x40
+#define ERR_TGL 0x80
+
+/* Endpoint Select Register Definitions */
+#define EP_SEL_F 0x01
+#define EP_SEL_ST 0x02
+#define EP_SEL_STP 0x04
+#define EP_SEL_PO 0x08
+#define EP_SEL_EPN 0x10
+#define EP_SEL_B_1_FULL 0x20
+#define EP_SEL_B_2_FULL 0x40
+
+/* Endpoint Status Register Definitions */
+#define EP_STAT_ST 0x01
+#define EP_STAT_DA 0x20
+#define EP_STAT_RF_MO 0x40
+#define EP_STAT_CND_ST 0x80
+
+/* Clear Buffer Register Definitions */
+#define CLR_BUF_PO 0x01
+
+
+/* DMA Interrupt Bit Definitions */
+#define EOT_INT 0x01
+#define NDD_REQ_INT 0x02
+#define SYS_ERR_INT 0x04
+
+
+#endif /* __USBREG_H */
-/*----------------------------------------------------------------------------\r
- * Name: serial.c\r
- * Purpose: serial port handling for LPC17xx\r
- * Version: V1.20\r
- *----------------------------------------------------------------------------\r
- * This software is supplied "AS IS" without any warranties, express,\r
- * implied or statutory, including but not limited to the implied\r
- * warranties of fitness for purpose, satisfactory quality and\r
- * noninfringement. Keil extends you a royalty-free right to reproduce\r
- * and distribute executable files created using this software for use\r
- * on NXP Semiconductors LPC microcontroller devices only. Nothing else\r
- * gives you the right to use this software.\r
- *\r
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
- *---------------------------------------------------------------------------*/\r
-#include "../LPC17xx.h" // LPC17xx definitions\r
-#include "lpc_types.h"\r
-#include "serial.h"\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- Defines for ring buffers\r
- *---------------------------------------------------------------------------*/\r
-#define SER_BUF_SIZE (128) // serial buffer in bytes (power 2)\r
-#define SER_BUF_MASK (SER_BUF_SIZE-1ul) // buffer size mask\r
-\r
-/* Buffer read / write macros */\r
-#define SER_BUF_RESET(serBuf) (serBuf.rdIdx = serBuf.wrIdx = 0)\r
-#define SER_BUF_WR(serBuf, dataIn) (serBuf.data[SER_BUF_MASK & serBuf.wrIdx++] = (dataIn))\r
-#define SER_BUF_RD(serBuf) (serBuf.data[SER_BUF_MASK & serBuf.rdIdx++])\r
-#define SER_BUF_EMPTY(serBuf) (serBuf.rdIdx == serBuf.wrIdx)\r
-#define SER_BUF_FULL(serBuf) (serBuf.rdIdx == serBuf.wrIdx+1)\r
-#define SER_BUF_COUNT(serBuf) (SER_BUF_MASK & (serBuf.wrIdx - serBuf.rdIdx))\r
-\r
-// buffer type\r
-typedef struct __SER_BUF_T {\r
- unsigned char data[SER_BUF_SIZE];\r
- unsigned int wrIdx;\r
- unsigned int rdIdx;\r
-} SER_BUF_T;\r
-\r
-unsigned long ser_txRestart; // NZ if TX restart is required\r
-unsigned short ser_lineState; // ((msr << 8) | (lsr))\r
-SER_BUF_T ser_out; // Serial data buffers\r
-SER_BUF_T ser_in;\r
-\r
-/*----------------------------------------------------------------------------\r
- open the serial port\r
- *---------------------------------------------------------------------------*/\r
-void ser_OpenPort (char portNum) {\r
-\r
- if ( portNum == 0 )\r
- {\r
- /* Port 0 */\r
- NVIC_DisableIRQ(UART0_IRQn);\r
- PINCON->PINSEL0 &= ~0x000000F0;\r
- PINCON->PINSEL0 |= 0x00000050; /* RxD0 is P0.3 and TxD0 is P0.2 */\r
- }\r
- else\r
- {\r
- /* Port 1 */\r
- NVIC_DisableIRQ(UART1_IRQn);\r
- PINCON->PINSEL4 &= ~0x0000000F;\r
- PINCON->PINSEL4 |= 0x0000000A; /* Enable RxD1 P2.1, TxD1 P2.0 */\r
- }\r
- return;\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
- close the serial port\r
- *---------------------------------------------------------------------------*/\r
-void ser_ClosePort (char portNum ) {\r
- if ( portNum == 0 )\r
- {\r
- /* POrt 0 */\r
- PINCON->PINSEL0 &= ~0x000000F0;\r
- /* Disable the interrupt in the VIC and UART controllers */\r
- UART0->IER = 0;\r
- NVIC_DisableIRQ(UART0_IRQn);\r
- }\r
- else\r
- {\r
- /* Port 1 */\r
- PINCON->PINSEL4 &= ~0x0000000F;\r
- /* Disable the interrupt in the VIC and UART controllers */\r
- UART1->IER = 0;\r
- NVIC_DisableIRQ(UART1_IRQn);\r
- }\r
- return;\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
- initialize the serial port\r
- *---------------------------------------------------------------------------*/\r
-void ser_InitPort0 (unsigned long baudrate, unsigned int databits,\r
- unsigned int parity, unsigned int stopbits) {\r
-\r
- unsigned char lcr_p, lcr_s, lcr_d;\r
- unsigned int dll;\r
- unsigned int pclkdiv, pclk;\r
-\r
- switch (databits) {\r
- case 5: // 5 Data bits\r
- lcr_d = 0x00;\r
- break;\r
- case 6: // 6 Data bits\r
- lcr_d = 0x01;\r
- break;\r
- case 7: // 7 Data bits\r
- lcr_d = 0x02;\r
- break;\r
- case 8: // 8 Data bits\r
- default:\r
- lcr_d = 0x03;\r
- break;\r
- }\r
-\r
- switch (stopbits) {\r
- case 1: // 1,5 Stop bits\r
- case 2: // 2 Stop bits\r
- lcr_s = 0x04;\r
- break;\r
- case 0: // 1 Stop bit\r
- default:\r
- lcr_s = 0x00;\r
- break;\r
- }\r
-\r
- switch (parity) {\r
- case 1: // Parity Odd\r
- lcr_p = 0x08;\r
- break;\r
- case 2: // Parity Even\r
- lcr_p = 0x18;\r
- break;\r
- case 3: // Parity Mark\r
- lcr_p = 0x28;\r
- break;\r
- case 4: // Parity Space\r
- lcr_p = 0x38;\r
- break;\r
- case 0: // Parity None\r
- default:\r
- lcr_p = 0x00;\r
- break;\r
- }\r
-\r
- SER_BUF_RESET(ser_out); // reset out buffer\r
- SER_BUF_RESET(ser_in); // reset in buffer\r
-\r
- /* Bit 6~7 is for UART0 */\r
- pclkdiv = (SC->PCLKSEL0 >> 6) & 0x03;\r
-\r
- switch ( pclkdiv )\r
- {\r
- case 0x00:\r
- default:\r
- pclk = SystemFrequency/4;\r
- break;\r
- case 0x01:\r
- pclk = SystemFrequency;\r
- break;\r
- case 0x02:\r
- pclk = SystemFrequency/2;\r
- break;\r
- case 0x03:\r
- pclk = SystemFrequency/8;\r
- break;\r
- }\r
-\r
- dll = (pclk/16)/baudrate ; /*baud rate */\r
- UART0->FDR = 0; // Fractional divider not used\r
- UART0->LCR = 0x80 | lcr_d | lcr_p | lcr_s; // Data bits, Parity, Stop bit\r
- UART0->DLL = dll; // Baud Rate depending on PCLK\r
- UART0->DLM = (dll >> 8); // High divisor latch\r
- UART0->LCR = 0x00 | lcr_d | lcr_p | lcr_s; // DLAB = 0\r
- UART0->IER = 0x03; // Enable TX/RX interrupts\r
-\r
- UART0->FCR = 0x07; /* Enable and reset TX and RX FIFO. */\r
- ser_txRestart = 1; // TX fifo is empty\r
-\r
- /* Enable the UART Interrupt */\r
- NVIC_EnableIRQ(UART0_IRQn);\r
- return;\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
- initialize the serial port\r
- *---------------------------------------------------------------------------*/\r
-void ser_InitPort1 (unsigned long baudrate, unsigned int databits,\r
- unsigned int parity, unsigned int stopbits) {\r
-\r
- unsigned char lcr_p, lcr_s, lcr_d;\r
- unsigned int dll;\r
- unsigned int pclkdiv, pclk;\r
-\r
- switch (databits) {\r
- case 5: // 5 Data bits\r
- lcr_d = 0x00;\r
- break;\r
- case 6: // 6 Data bits\r
- lcr_d = 0x01;\r
- break;\r
- case 7: // 7 Data bits\r
- lcr_d = 0x02;\r
- break;\r
- case 8: // 8 Data bits\r
- default:\r
- lcr_d = 0x03;\r
- break;\r
- }\r
-\r
- switch (stopbits) {\r
- case 1: // 1,5 Stop bits\r
- case 2: // 2 Stop bits\r
- lcr_s = 0x04;\r
- break;\r
- case 0: // 1 Stop bit\r
- default:\r
- lcr_s = 0x00;\r
- break;\r
- }\r
-\r
- switch (parity) {\r
- case 1: // Parity Odd\r
- lcr_p = 0x08;\r
- break;\r
- case 2: // Parity Even\r
- lcr_p = 0x18;\r
- break;\r
- case 3: // Parity Mark\r
- lcr_p = 0x28;\r
- break;\r
- case 4: // Parity Space\r
- lcr_p = 0x38;\r
- break;\r
- case 0: // Parity None\r
- default:\r
- lcr_p = 0x00;\r
- break;\r
- }\r
-\r
- SER_BUF_RESET(ser_out); // reset out buffer\r
- SER_BUF_RESET(ser_in); // reset in buffer\r
-\r
- /* Bit 8,9 are for UART1 */\r
- pclkdiv = (SC->PCLKSEL0 >> 8) & 0x03;\r
-\r
- switch ( pclkdiv )\r
- {\r
- case 0x00:\r
- default:\r
- pclk = SystemFrequency/4;\r
- break;\r
- case 0x01:\r
- pclk = SystemFrequency;\r
- break;\r
- case 0x02:\r
- pclk = SystemFrequency/2;\r
- break;\r
- case 0x03:\r
- pclk = SystemFrequency/8;\r
- break;\r
- }\r
-\r
- dll = (pclk/16)/baudrate ; /*baud rate */\r
- UART1->FDR = 0; // Fractional divider not used\r
- UART1->LCR = 0x80 | lcr_d | lcr_p | lcr_s; // Data bits, Parity, Stop bit\r
- UART1->DLL = dll; // Baud Rate depending on PCLK\r
- UART1->DLM = (dll >> 8); // High divisor latch\r
- UART1->LCR = 0x00 | lcr_d | lcr_p | lcr_s; // DLAB = 0\r
- UART1->IER = 0x03; // Enable TX/RX interrupts\r
-\r
- UART1->FCR = 0x07; /* Enable and reset TX and RX FIFO. */\r
- ser_txRestart = 1; // TX fifo is empty\r
-\r
- /* Enable the UART Interrupt */\r
- NVIC_EnableIRQ(UART1_IRQn);\r
- return;\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
- read data from serial port\r
- *---------------------------------------------------------------------------*/\r
-int ser_Read (char *buffer, const int *length) {\r
- int bytesToRead, bytesRead;\r
-\r
- /* Read *length bytes, block if *bytes are not avaialable */\r
- bytesToRead = *length;\r
- bytesToRead = (bytesToRead < (*length)) ? bytesToRead : (*length);\r
- bytesRead = bytesToRead;\r
-\r
- while (bytesToRead--) {\r
- while (SER_BUF_EMPTY(ser_in)); // Block until data is available if none\r
- *buffer++ = SER_BUF_RD(ser_in);\r
- }\r
- return (bytesRead);\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
- write data to the serial port\r
- *---------------------------------------------------------------------------*/\r
-int ser_Write (char portNum, const char *buffer, int *length) {\r
- int bytesToWrite, bytesWritten;\r
-\r
- // Write *length bytes\r
- bytesToWrite = *length;\r
- bytesWritten = bytesToWrite;\r
-\r
- while (!SER_BUF_EMPTY(ser_out)); // Block until space is available if none\r
- while (bytesToWrite) {\r
- SER_BUF_WR(ser_out, *buffer++); // Read Rx FIFO to buffer\r
- bytesToWrite--;\r
- }\r
-\r
- if (ser_txRestart) {\r
- ser_txRestart = 0;\r
- if ( portNum == 0 )\r
- {\r
- UART0->THR = SER_BUF_RD(ser_out); // Write to the Tx Register\r
- }\r
- else\r
- {\r
- UART1->THR = SER_BUF_RD(ser_out); // Write to the Tx Register\r
- }\r
- }\r
-\r
- return (bytesWritten);\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
- check if character(s) are available at the serial interface\r
- *---------------------------------------------------------------------------*/\r
-void ser_AvailChar (int *availChar) {\r
-\r
- *availChar = SER_BUF_COUNT(ser_in);\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
- read the line state of the serial port\r
- *---------------------------------------------------------------------------*/\r
-void ser_LineState (unsigned short *lineState) {\r
-\r
- *lineState = ser_lineState;\r
- ser_lineState = 0;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
- serial port 0 interrupt\r
- *---------------------------------------------------------------------------*/\r
-void UART0_IRQHandler(void)\r
-{\r
- volatile unsigned long iir;\r
-\r
- iir = UART0->IIR;\r
-\r
- if ((iir & 0x4) || (iir & 0xC)) { // RDA or CTI pending\r
- while (UART0->LSR & 0x01) { // Rx FIFO is not empty\r
- SER_BUF_WR(ser_in, UART0->RBR); // Read Rx FIFO to buffer\r
- }\r
- }\r
- if ((iir & 0x2)) { // TXMIS pending\r
- if (SER_BUF_COUNT(ser_out) != 0) {\r
- UART0->THR = SER_BUF_RD(ser_out); // Write to the Tx FIFO\r
- ser_txRestart = 0;\r
- }\r
- else {\r
- ser_txRestart = 1;\r
- }\r
- }\r
- ser_lineState = UART0->LSR & 0x1E; // update linestate\r
- return;\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
- serial port 1 interrupt\r
- *---------------------------------------------------------------------------*/\r
-void UART1_IRQHandler(void)\r
-{\r
- volatile unsigned long iir;\r
-\r
- iir = UART1->IIR;\r
-\r
- if ((iir & 0x4) || (iir & 0xC)) { // RDA or CTI pending\r
- while (UART1->LSR & 0x01) { // Rx FIFO is not empty\r
- SER_BUF_WR(ser_in, UART1->RBR); // Read Rx FIFO to buffer\r
- }\r
- }\r
- if ((iir & 0x2)) { // TXMIS pending\r
- if (SER_BUF_COUNT(ser_out) != 0) {\r
- UART1->THR = SER_BUF_RD(ser_out); // Write to the Tx FIFO\r
- ser_txRestart = 0;\r
- }\r
- else {\r
- ser_txRestart = 1;\r
- }\r
- }\r
- ser_lineState = ((UART1->MSR<<8)|UART1->LSR) & 0xE01E; // update linestate\r
- return;\r
-}\r
-\r
-\r
+/*----------------------------------------------------------------------------
+ * Name: serial.c
+ * Purpose: serial port handling for LPC17xx
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC microcontroller devices only. Nothing else
+ * gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+#include <board.h> // LPC17xx definitions
+#include "lpc_types.h"
+#include "serial.h"
+
+
+/*----------------------------------------------------------------------------
+ Defines for ring buffers
+ *---------------------------------------------------------------------------*/
+#define SER_BUF_SIZE (128) // serial buffer in bytes (power 2)
+#define SER_BUF_MASK (SER_BUF_SIZE-1ul) // buffer size mask
+
+/* Buffer read / write macros */
+#define SER_BUF_RESET(serBuf) (serBuf.rdIdx = serBuf.wrIdx = 0)
+#define SER_BUF_WR(serBuf, dataIn) (serBuf.data[SER_BUF_MASK & serBuf.wrIdx++] = (dataIn))
+#define SER_BUF_RD(serBuf) (serBuf.data[SER_BUF_MASK & serBuf.rdIdx++])
+#define SER_BUF_EMPTY(serBuf) (serBuf.rdIdx == serBuf.wrIdx)
+#define SER_BUF_FULL(serBuf) (serBuf.rdIdx == serBuf.wrIdx+1)
+#define SER_BUF_COUNT(serBuf) (SER_BUF_MASK & (serBuf.wrIdx - serBuf.rdIdx))
+
+// buffer type
+typedef struct __SER_BUF_T {
+ unsigned char data[SER_BUF_SIZE];
+ unsigned int wrIdx;
+ unsigned int rdIdx;
+} SER_BUF_T;
+
+unsigned long ser_txRestart; // NZ if TX restart is required
+unsigned short ser_lineState; // ((msr << 8) | (lsr))
+SER_BUF_T ser_out; // Serial data buffers
+SER_BUF_T ser_in;
+
+/*----------------------------------------------------------------------------
+ open the serial port
+ *---------------------------------------------------------------------------*/
+void ser_OpenPort (char portNum) {
+
+ if ( portNum == 0 )
+ {
+ /* Port 0 */
+ NVIC_DisableIRQ(UART0_IRQn);
+ PINCON->PINSEL0 &= ~0x000000F0;
+ PINCON->PINSEL0 |= 0x00000050; /* RxD0 is P0.3 and TxD0 is P0.2 */
+ }
+ else
+ {
+ /* Port 1 */
+ NVIC_DisableIRQ(UART1_IRQn);
+ PINCON->PINSEL4 &= ~0x0000000F;
+ PINCON->PINSEL4 |= 0x0000000A; /* Enable RxD1 P2.1, TxD1 P2.0 */
+ }
+ return;
+}
+
+/*----------------------------------------------------------------------------
+ close the serial port
+ *---------------------------------------------------------------------------*/
+void ser_ClosePort (char portNum ) {
+ if ( portNum == 0 )
+ {
+ /* POrt 0 */
+ PINCON->PINSEL0 &= ~0x000000F0;
+ /* Disable the interrupt in the VIC and UART controllers */
+ UART0->IER = 0;
+ NVIC_DisableIRQ(UART0_IRQn);
+ }
+ else
+ {
+ /* Port 1 */
+ PINCON->PINSEL4 &= ~0x0000000F;
+ /* Disable the interrupt in the VIC and UART controllers */
+ UART1->IER = 0;
+ NVIC_DisableIRQ(UART1_IRQn);
+ }
+ return;
+}
+
+/*----------------------------------------------------------------------------
+ initialize the serial port
+ *---------------------------------------------------------------------------*/
+void ser_InitPort0 (unsigned long baudrate, unsigned int databits,
+ unsigned int parity, unsigned int stopbits) {
+
+ unsigned char lcr_p, lcr_s, lcr_d;
+ unsigned int dll;
+ unsigned int pclkdiv, pclk;
+
+ switch (databits) {
+ case 5: // 5 Data bits
+ lcr_d = 0x00;
+ break;
+ case 6: // 6 Data bits
+ lcr_d = 0x01;
+ break;
+ case 7: // 7 Data bits
+ lcr_d = 0x02;
+ break;
+ case 8: // 8 Data bits
+ default:
+ lcr_d = 0x03;
+ break;
+ }
+
+ switch (stopbits) {
+ case 1: // 1,5 Stop bits
+ case 2: // 2 Stop bits
+ lcr_s = 0x04;
+ break;
+ case 0: // 1 Stop bit
+ default:
+ lcr_s = 0x00;
+ break;
+ }
+
+ switch (parity) {
+ case 1: // Parity Odd
+ lcr_p = 0x08;
+ break;
+ case 2: // Parity Even
+ lcr_p = 0x18;
+ break;
+ case 3: // Parity Mark
+ lcr_p = 0x28;
+ break;
+ case 4: // Parity Space
+ lcr_p = 0x38;
+ break;
+ case 0: // Parity None
+ default:
+ lcr_p = 0x00;
+ break;
+ }
+
+ SER_BUF_RESET(ser_out); // reset out buffer
+ SER_BUF_RESET(ser_in); // reset in buffer
+
+ /* Bit 6~7 is for UART0 */
+ pclkdiv = (SC->PCLKSEL0 >> 6) & 0x03;
+
+ switch ( pclkdiv )
+ {
+ case 0x00:
+ default:
+ pclk = SystemFrequency/4;
+ break;
+ case 0x01:
+ pclk = SystemFrequency;
+ break;
+ case 0x02:
+ pclk = SystemFrequency/2;
+ break;
+ case 0x03:
+ pclk = SystemFrequency/8;
+ break;
+ }
+
+ dll = (pclk/16)/baudrate ; /*baud rate */
+ UART0->FDR = 0; // Fractional divider not used
+ UART0->LCR = 0x80 | lcr_d | lcr_p | lcr_s; // Data bits, Parity, Stop bit
+ UART0->DLL = dll; // Baud Rate depending on PCLK
+ UART0->DLM = (dll >> 8); // High divisor latch
+ UART0->LCR = 0x00 | lcr_d | lcr_p | lcr_s; // DLAB = 0
+ UART0->IER = 0x03; // Enable TX/RX interrupts
+
+ UART0->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
+ ser_txRestart = 1; // TX fifo is empty
+
+ /* Enable the UART Interrupt */
+ NVIC_EnableIRQ(UART0_IRQn);
+ return;
+}
+
+/*----------------------------------------------------------------------------
+ initialize the serial port
+ *---------------------------------------------------------------------------*/
+void ser_InitPort1 (unsigned long baudrate, unsigned int databits,
+ unsigned int parity, unsigned int stopbits) {
+
+ unsigned char lcr_p, lcr_s, lcr_d;
+ unsigned int dll;
+ unsigned int pclkdiv, pclk;
+
+ switch (databits) {
+ case 5: // 5 Data bits
+ lcr_d = 0x00;
+ break;
+ case 6: // 6 Data bits
+ lcr_d = 0x01;
+ break;
+ case 7: // 7 Data bits
+ lcr_d = 0x02;
+ break;
+ case 8: // 8 Data bits
+ default:
+ lcr_d = 0x03;
+ break;
+ }
+
+ switch (stopbits) {
+ case 1: // 1,5 Stop bits
+ case 2: // 2 Stop bits
+ lcr_s = 0x04;
+ break;
+ case 0: // 1 Stop bit
+ default:
+ lcr_s = 0x00;
+ break;
+ }
+
+ switch (parity) {
+ case 1: // Parity Odd
+ lcr_p = 0x08;
+ break;
+ case 2: // Parity Even
+ lcr_p = 0x18;
+ break;
+ case 3: // Parity Mark
+ lcr_p = 0x28;
+ break;
+ case 4: // Parity Space
+ lcr_p = 0x38;
+ break;
+ case 0: // Parity None
+ default:
+ lcr_p = 0x00;
+ break;
+ }
+
+ SER_BUF_RESET(ser_out); // reset out buffer
+ SER_BUF_RESET(ser_in); // reset in buffer
+
+ /* Bit 8,9 are for UART1 */
+ pclkdiv = (SC->PCLKSEL0 >> 8) & 0x03;
+
+ switch ( pclkdiv )
+ {
+ case 0x00:
+ default:
+ pclk = SystemFrequency/4;
+ break;
+ case 0x01:
+ pclk = SystemFrequency;
+ break;
+ case 0x02:
+ pclk = SystemFrequency/2;
+ break;
+ case 0x03:
+ pclk = SystemFrequency/8;
+ break;
+ }
+
+ dll = (pclk/16)/baudrate ; /*baud rate */
+ UART1->FDR = 0; // Fractional divider not used
+ UART1->LCR = 0x80 | lcr_d | lcr_p | lcr_s; // Data bits, Parity, Stop bit
+ UART1->DLL = dll; // Baud Rate depending on PCLK
+ UART1->DLM = (dll >> 8); // High divisor latch
+ UART1->LCR = 0x00 | lcr_d | lcr_p | lcr_s; // DLAB = 0
+ UART1->IER = 0x03; // Enable TX/RX interrupts
+
+ UART1->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
+ ser_txRestart = 1; // TX fifo is empty
+
+ /* Enable the UART Interrupt */
+ NVIC_EnableIRQ(UART1_IRQn);
+ return;
+}
+
+/*----------------------------------------------------------------------------
+ read data from serial port
+ *---------------------------------------------------------------------------*/
+int ser_Read (char *buffer, const int *length) {
+ int bytesToRead, bytesRead;
+
+ /* Read *length bytes, block if *bytes are not avaialable */
+ bytesToRead = *length;
+ bytesToRead = (bytesToRead < (*length)) ? bytesToRead : (*length);
+ bytesRead = bytesToRead;
+
+ while (bytesToRead--) {
+ while (SER_BUF_EMPTY(ser_in)); // Block until data is available if none
+ *buffer++ = SER_BUF_RD(ser_in);
+ }
+ return (bytesRead);
+}
+
+/*----------------------------------------------------------------------------
+ write data to the serial port
+ *---------------------------------------------------------------------------*/
+int ser_Write (char portNum, const char *buffer, int *length) {
+ int bytesToWrite, bytesWritten;
+
+ // Write *length bytes
+ bytesToWrite = *length;
+ bytesWritten = bytesToWrite;
+
+ while (!SER_BUF_EMPTY(ser_out)); // Block until space is available if none
+ while (bytesToWrite) {
+ SER_BUF_WR(ser_out, *buffer++); // Read Rx FIFO to buffer
+ bytesToWrite--;
+ }
+
+ if (ser_txRestart) {
+ ser_txRestart = 0;
+ if ( portNum == 0 )
+ {
+ UART0->THR = SER_BUF_RD(ser_out); // Write to the Tx Register
+ }
+ else
+ {
+ UART1->THR = SER_BUF_RD(ser_out); // Write to the Tx Register
+ }
+ }
+
+ return (bytesWritten);
+}
+
+/*----------------------------------------------------------------------------
+ check if character(s) are available at the serial interface
+ *---------------------------------------------------------------------------*/
+void ser_AvailChar (int *availChar) {
+
+ *availChar = SER_BUF_COUNT(ser_in);
+
+}
+
+/*----------------------------------------------------------------------------
+ read the line state of the serial port
+ *---------------------------------------------------------------------------*/
+void ser_LineState (unsigned short *lineState) {
+
+ *lineState = ser_lineState;
+ ser_lineState = 0;
+
+}
+
+/*----------------------------------------------------------------------------
+ serial port 0 interrupt
+ *---------------------------------------------------------------------------*/
+void UART0_IRQHandler(void)
+{
+ volatile unsigned long iir;
+
+ iir = UART0->IIR;
+
+ if ((iir & 0x4) || (iir & 0xC)) { // RDA or CTI pending
+ while (UART0->LSR & 0x01) { // Rx FIFO is not empty
+ SER_BUF_WR(ser_in, UART0->RBR); // Read Rx FIFO to buffer
+ }
+ }
+ if ((iir & 0x2)) { // TXMIS pending
+ if (SER_BUF_COUNT(ser_out) != 0) {
+ UART0->THR = SER_BUF_RD(ser_out); // Write to the Tx FIFO
+ ser_txRestart = 0;
+ }
+ else {
+ ser_txRestart = 1;
+ }
+ }
+ ser_lineState = UART0->LSR & 0x1E; // update linestate
+ return;
+}
+
+/*----------------------------------------------------------------------------
+ serial port 1 interrupt
+ *---------------------------------------------------------------------------*/
+void UART1_IRQHandler(void)
+{
+ volatile unsigned long iir;
+
+ iir = UART1->IIR;
+
+ if ((iir & 0x4) || (iir & 0xC)) { // RDA or CTI pending
+ while (UART1->LSR & 0x01) { // Rx FIFO is not empty
+ SER_BUF_WR(ser_in, UART1->RBR); // Read Rx FIFO to buffer
+ }
+ }
+ if ((iir & 0x2)) { // TXMIS pending
+ if (SER_BUF_COUNT(ser_out) != 0) {
+ UART1->THR = SER_BUF_RD(ser_out); // Write to the Tx FIFO
+ ser_txRestart = 0;
+ }
+ else {
+ ser_txRestart = 1;
+ }
+ }
+ ser_lineState = ((UART1->MSR<<8)|UART1->LSR) & 0xE01E; // update linestate
+ return;
+}
+
+
-/*----------------------------------------------------------------------------\r
- * Name: serial.h\r
- * Purpose: serial port handling\r
- * Version: V1.10\r
- *----------------------------------------------------------------------------\r
- * This software is supplied "AS IS" without any warranties, express,\r
- * implied or statutory, including but not limited to the implied\r
- * warranties of fitness for purpose, satisfactory quality and\r
- * noninfringement. Keil extends you a royalty-free right to reproduce\r
- * and distribute executable files created using this software for use\r
- * on NXP Semiconductors LPC microcontroller devices only. Nothing else\r
- * gives you the right to use this software.\r
- *\r
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
- *---------------------------------------------------------------------------*/\r
-\r
-#define PORT_NUM 1\r
-\r
-/*----------------------------------------------------------------------------\r
- Serial interface related prototypes\r
- *---------------------------------------------------------------------------*/\r
-extern void ser_OpenPort (char portNum);\r
-extern void ser_ClosePort (char portNum);\r
-extern void ser_InitPort0 (unsigned long baudrate, unsigned int databits, unsigned int parity, unsigned int stopbits);\r
-extern void ser_InitPort1 (unsigned long baudrate, unsigned int databits, unsigned int parity, unsigned int stopbits);\r
-extern void ser_AvailChar (int *availChar);\r
-extern int ser_Write (char portNum, const char *buffer, int *length);\r
-extern int ser_Read (char *buffer, const int *length);\r
-extern void ser_LineState (unsigned short *lineState);\r
-\r
+/*----------------------------------------------------------------------------
+ * Name: serial.h
+ * Purpose: serial port handling
+ * Version: V1.10
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC microcontroller devices only. Nothing else
+ * gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#define PORT_NUM 1
+
+/*----------------------------------------------------------------------------
+ Serial interface related prototypes
+ *---------------------------------------------------------------------------*/
+extern void ser_OpenPort (char portNum);
+extern void ser_ClosePort (char portNum);
+extern void ser_InitPort0 (unsigned long baudrate, unsigned int databits, unsigned int parity, unsigned int stopbits);
+extern void ser_InitPort1 (unsigned long baudrate, unsigned int databits, unsigned int parity, unsigned int stopbits);
+extern void ser_AvailChar (int *availChar);
+extern int ser_Write (char portNum, const char *buffer, int *length);
+extern int ser_Read (char *buffer, const int *length);
+extern void ser_LineState (unsigned short *lineState);
+
+++ /dev/null
-//*****************************************************************************\r
-//\r
-// startup_gcc.c - Startup code for use with GNU tools.\r
-//\r
-// Copyright (c) 2009 Luminary Micro, Inc. All rights reserved.\r
-// Software License Agreement\r
-// \r
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
-// exclusively on LMI's microcontroller products.\r
-// \r
-// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. You may not combine\r
-// this software with "viral" open-source software in order to form a larger\r
-// program. Any use in violation of the foregoing restrictions may subject\r
-// the user to criminal sanctions under applicable laws, as well as to civil\r
-// liability for the breach of the terms and conditions of this license.\r
-// \r
-// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
-// \r
-// This is part of revision 32 of the Stellaris CMSIS Package.\r
-//\r
-//*****************************************************************************\r
-\r
-#define WEAK __attribute__ ((weak))\r
-\r
-//*****************************************************************************\r
-//\r
-// Forward declaration of the default fault handlers.\r
-//\r
-//*****************************************************************************\r
-void WEAK Reset_Handler(void);\r
-static void Default_Handler(void);\r
-void WEAK NMI_Handler(void);\r
-void WEAK HardFault_Handler(void);\r
-void WEAK MemManage_Handler(void);\r
-void WEAK BusFault_Handler(void);\r
-void WEAK UsageFault_Handler(void);\r
-void WEAK MemManage_Handler(void);\r
-void WEAK SVC_Handler(void);\r
-void WEAK DebugMon_Handler(void);\r
-void WEAK PendSV_Handler(void);\r
-void WEAK SysTick_Handler(void);\r
-void WEAK GPIOPortA_IRQHandler(void);\r
-void WEAK GPIOPortB_IRQHandler(void);\r
-void WEAK GPIOPortC_IRQHandler(void);\r
-void WEAK GPIOPortD_IRQHandler(void);\r
-void WEAK GPIOPortE_IRQHandler(void);\r
-void WEAK UART0_IRQHandler(void);\r
-void WEAK UART1_IRQHandler(void);\r
-void WEAK SSI0_IRQHandler(void);\r
-void WEAK I2C0_IRQHandler(void);\r
-void WEAK PWMFault_IRQHandler(void);\r
-void WEAK PWMGen0_IRQHandler(void);\r
-void WEAK PWMGen1_IRQHandler(void);\r
-void WEAK PWMGen2_IRQHandler(void);\r
-void WEAK QEI0_IRQHandler(void);\r
-void WEAK ADCSeq0_IRQHandler(void);\r
-void WEAK ADCSeq1_IRQHandler(void);\r
-void WEAK ADCSeq2_IRQHandler(void);\r
-void WEAK ADCSeq3_IRQHandler(void);\r
-void WEAK Watchdog_IRQHandler(void);\r
-void WEAK Timer0A_IRQHandler(void);\r
-void WEAK Timer0B_IRQHandler(void);\r
-void WEAK Timer1A_IRQHandler(void);\r
-void WEAK Timer1B_IRQHandler(void);\r
-void WEAK Timer2A_IRQHandler(void);\r
-void WEAK Timer2B_IRQHandler(void);\r
-void WEAK Comp0_IRQHandler(void);\r
-void WEAK Comp1_IRQHandler(void);\r
-void WEAK Comp2_IRQHandler(void);\r
-void WEAK SysCtrl_IRQHandler(void);\r
-void WEAK FlashCtrl_IRQHandler(void);\r
-void WEAK GPIOPortF_IRQHandler(void);\r
-void WEAK GPIOPortG_IRQHandler(void);\r
-void WEAK GPIOPortH_IRQHandler(void);\r
-void WEAK UART2_IRQHandler(void);\r
-void WEAK SSI1_IRQHandler(void);\r
-void WEAK Timer3A_IRQHandler(void);\r
-void WEAK Timer3B_IRQHandler(void);\r
-void WEAK I2C1_IRQHandler(void);\r
-void WEAK QEI1_IRQHandler(void);\r
-void WEAK CAN0_IRQHandler(void);\r
-void WEAK CAN1_IRQHandler(void);\r
-void WEAK CAN2_IRQHandler(void);\r
-void WEAK Ethernet_IRQHandler(void);\r
-void WEAK Hibernate_IRQHandler(void);\r
-\r
-//*****************************************************************************\r
-//\r
-// The entry point for the application.\r
-//\r
-//*****************************************************************************\r
-extern int main(void);\r
-\r
-//*****************************************************************************\r
-//\r
-// Reserve space for the system stack.\r
-//\r
-//*****************************************************************************\r
-static unsigned long pulStack[64];\r
-\r
-//*****************************************************************************\r
-//\r
-// The vector table. Note that the proper constructs must be placed on this to\r
-// ensure that it ends up at physical address 0x0000.0000.\r
-//\r
-//*****************************************************************************\r
-__attribute__ ((section(".isr_vector")))\r
-void (* const g_pfnVectors[])(void) =\r
-{\r
- (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)),\r
- // The initial stack pointer\r
- Reset_Handler, // The reset handler\r
- NMI_Handler, // The NMI handler\r
- HardFault_Handler, // The hard fault handler\r
- MemManage_Handler, // The MPU fault handler\r
- BusFault_Handler, // The bus fault handler\r
- UsageFault_Handler, // The usage fault handler\r
- 0xefff9d6e, // Reserved\r
- 0, // Reserved\r
- 0, // Reserved\r
- 0, // Reserved\r
- SVC_Handler, // SVCall handler\r
- DebugMon_Handler, // Debug monitor handler\r
- 0, // Reserved\r
- PendSV_Handler, // The PendSV handler\r
- SysTick_Handler, // The SysTick handler\r
-\r
- //\r
- // External Interrupts\r
- //\r
- GPIOPortA_IRQHandler, // GPIO Port A\r
- GPIOPortB_IRQHandler, // GPIO Port B\r
- GPIOPortC_IRQHandler, // GPIO Port C\r
- GPIOPortD_IRQHandler, // GPIO Port D\r
- GPIOPortE_IRQHandler, // GPIO Port E\r
- UART0_IRQHandler, // UART0 Rx and Tx\r
- UART1_IRQHandler, // UART1 Rx and Tx\r
- SSI0_IRQHandler, // SSI0 Rx and Tx\r
- I2C0_IRQHandler, // I2C0 Master and Slave\r
- PWMFault_IRQHandler, // PWM Fault\r
- PWMGen0_IRQHandler, // PWM Generator 0\r
- PWMGen1_IRQHandler, // PWM Generator 1\r
- PWMGen2_IRQHandler, // PWM Generator 2\r
- QEI0_IRQHandler, // Quadrature Encoder 0\r
- ADCSeq0_IRQHandler, // ADC Sequence 0\r
- ADCSeq1_IRQHandler, // ADC Sequence 1\r
- ADCSeq2_IRQHandler, // ADC Sequence 2\r
- ADCSeq3_IRQHandler, // ADC Sequence 3\r
- Watchdog_IRQHandler, // Watchdog timer\r
- Timer0A_IRQHandler, // Timer 0 subtimer A\r
- Timer0B_IRQHandler, // Timer 0 subtimer B\r
- Timer1A_IRQHandler, // Timer 1 subtimer A\r
- Timer1B_IRQHandler, // Timer 1 subtimer B\r
- Timer2A_IRQHandler, // Timer 2 subtimer A\r
- Timer2B_IRQHandler, // Timer 2 subtimer B\r
- Comp0_IRQHandler, // Analog Comparator 0\r
- Comp1_IRQHandler, // Analog Comparator 1\r
- Comp2_IRQHandler, // Analog Comparator 2\r
- SysCtrl_IRQHandler, // System Control (PLL, OSC, BO)\r
- FlashCtrl_IRQHandler, // FLASH Control\r
- GPIOPortF_IRQHandler, // GPIO Port F\r
- GPIOPortG_IRQHandler, // GPIO Port G\r
- GPIOPortH_IRQHandler, // GPIO Port H\r
- UART2_IRQHandler, // UART2 Rx and Tx\r
- SSI1_IRQHandler, // SSI1 Rx and Tx\r
- Timer3A_IRQHandler, // Timer 3 subtimer A\r
- Timer3B_IRQHandler, // Timer 3 subtimer B\r
- I2C1_IRQHandler, // I2C1 Master and Slave\r
- QEI1_IRQHandler, // Quadrature Encoder 1\r
- CAN0_IRQHandler, // CAN0\r
- CAN1_IRQHandler, // CAN1\r
- CAN2_IRQHandler, // CAN2\r
- Ethernet_IRQHandler, // Ethernet\r
- Hibernate_IRQHandler // Hibernate\r
-};\r
-\r
-//*****************************************************************************\r
-//\r
-// The following are constructs created by the linker, indicating where the\r
-// the "data" and "bss" segments reside in memory. The initializers for the\r
-// for the "data" segment resides immediately following the "text" segment.\r
-//\r
-//*****************************************************************************\r
-extern unsigned long _etext;\r
-extern unsigned long _sdata;\r
-extern unsigned long _edata;\r
-extern unsigned long _sbss;\r
-extern unsigned long _ebss;\r
-\r
-//*****************************************************************************\r
-//\r
-// This is the code that gets called when the processor first starts execution\r
-// following a reset event. Only the absolutely necessary set is performed,\r
-// after which the application supplied entry() routine is called. Any fancy\r
-// actions (such as making decisions based on the reset cause register, and\r
-// resetting the bits in that register) are left solely in the hands of the\r
-// application.\r
-//\r
-//*****************************************************************************\r
-void\r
-Reset_Handler(void)\r
-{\r
- unsigned long *pulSrc, *pulDest;\r
-\r
- //\r
- // Copy the data segment initializers from flash to SRAM.\r
- //\r
- pulSrc = &_etext;\r
- for(pulDest = &_sdata; pulDest < &_edata; )\r
- {\r
- *pulDest++ = *pulSrc++;\r
- }\r
-\r
- //\r
- // Zero fill the bss segment. This is done with inline assembly since this\r
- // will clear the value of pulDest if it is not kept in a register.\r
- //\r
- __asm(" ldr r0, =_sbss\n"\r
- " ldr r1, =_ebss\n"\r
- " mov r2, #0\n"\r
- " .thumb_func\n"\r
- "zero_loop:\n"\r
- " cmp r0, r1\n"\r
- " it lt\n"\r
- " strlt r2, [r0], #4\n"\r
- " blt zero_loop");\r
-\r
- //\r
- // Call the application's entry point.\r
- //\r
- main();\r
-}\r
-\r
-//*****************************************************************************\r
-//\r
-// Provide weak aliases for each Exception handler to the Default_Handler.\r
-// As they are weak aliases, any function with the same name will override\r
-// this definition.\r
-//\r
-//*****************************************************************************\r
-#pragma weak NMI_Handler = Default_Handler\r
-#pragma weak HardFault_Handler = Default_Handler\r
-#pragma weak MemManage_Handler = Default_Handler\r
-#pragma weak BusFault_Handler = Default_Handler\r
-#pragma weak UsageFault_Handler = Default_Handler\r
-#pragma weak SVC_Handler = Default_Handler\r
-#pragma weak DebugMon_Handler = Default_Handler\r
-#pragma weak PendSV_Handler = Default_Handler\r
-#pragma weak SysTick_Handler = Default_Handler\r
-#pragma weak GPIOPortA_IRQHandler = Default_Handler\r
-#pragma weak GPIOPortB_IRQHandler = Default_Handler\r
-#pragma weak GPIOPortC_IRQHandler = Default_Handler\r
-#pragma weak GPIOPortD_IRQHandler = Default_Handler\r
-#pragma weak GPIOPortE_IRQHandler = Default_Handler\r
-#pragma weak UART0_IRQHandler = Default_Handler\r
-#pragma weak UART1_IRQHandler = Default_Handler\r
-#pragma weak SSI0_IRQHandler = Default_Handler\r
-#pragma weak I2C0_IRQHandler = Default_Handler\r
-#pragma weak PWMFault_IRQHandler = Default_Handler\r
-#pragma weak PWMGen0_IRQHandler = Default_Handler\r
-#pragma weak PWMGen1_IRQHandler = Default_Handler\r
-#pragma weak PWMGen2_IRQHandler = Default_Handler\r
-#pragma weak QEI0_IRQHandler = Default_Handler\r
-#pragma weak ADCSeq0_IRQHandler = Default_Handler\r
-#pragma weak ADCSeq1_IRQHandler = Default_Handler\r
-#pragma weak ADCSeq2_IRQHandler = Default_Handler\r
-#pragma weak ADCSeq3_IRQHandler = Default_Handler\r
-#pragma weak Watchdog_IRQHandler = Default_Handler\r
-#pragma weak Timer0A_IRQHandler = Default_Handler\r
-#pragma weak Timer0B_IRQHandler = Default_Handler\r
-#pragma weak Timer1A_IRQHandler = Default_Handler\r
-#pragma weak Timer1B_IRQHandler = Default_Handler\r
-#pragma weak Timer2A_IRQHandler = Default_Handler\r
-#pragma weak Timer2B_IRQHandler = Default_Handler\r
-#pragma weak Comp0_IRQHandler = Default_Handler\r
-#pragma weak Comp1_IRQHandler = Default_Handler\r
-#pragma weak Comp2_IRQHandler = Default_Handler\r
-#pragma weak SysCtrl_IRQHandler = Default_Handler\r
-#pragma weak FlashCtrl_IRQHandler = Default_Handler\r
-#pragma weak GPIOPortF_IRQHandler = Default_Handler\r
-#pragma weak GPIOPortG_IRQHandler = Default_Handler\r
-#pragma weak GPIOPortH_IRQHandler = Default_Handler\r
-#pragma weak UART2_IRQHandler = Default_Handler\r
-#pragma weak SSI1_IRQHandler = Default_Handler\r
-#pragma weak Timer3A_IRQHandler = Default_Handler\r
-#pragma weak Timer3B_IRQHandler = Default_Handler\r
-#pragma weak I2C1_IRQHandler = Default_Handler\r
-#pragma weak QEI1_IRQHandler = Default_Handler\r
-#pragma weak CAN0_IRQHandler = Default_Handler\r
-#pragma weak CAN1_IRQHandler = Default_Handler\r
-#pragma weak CAN2_IRQHandler = Default_Handler\r
-#pragma weak Ethernet_IRQHandler = Default_Handler\r
-#pragma weak Hibernate_IRQHandler = Default_Handler\r
-\r
-//*****************************************************************************\r
-//\r
-// This is the code that gets called when the processor receives an unexpected\r
-// interrupt. This simply enters an infinite loop, preserving the system state\r
-// for examination by a debugger.\r
-//\r
-//*****************************************************************************\r
-static void\r
-Default_Handler(void)\r
-{\r
- //\r
- // Go into an infinite loop.\r
- //\r
- while(1)\r
- {\r
- }\r
-}\r
-/*----------------------------------------------------------------------------\r
- * U S B - K e r n e l\r
- *----------------------------------------------------------------------------\r
- * Name: usb.h\r
- * Purpose: USB Definitions\r
- * Version: V1.20\r
- *----------------------------------------------------------------------------\r
- * This software is supplied "AS IS" without any warranties, express,\r
- * implied or statutory, including but not limited to the implied\r
- * warranties of fitness for purpose, satisfactory quality and\r
- * noninfringement. Keil extends you a royalty-free right to reproduce\r
- * and distribute executable files created using this software for use\r
- * on NXP Semiconductors LPC family microcontroller devices only. Nothing\r
- * else gives you the right to use this software.\r
- *\r
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
- *---------------------------------------------------------------------------*/\r
-\r
-#ifndef __USB_H__\r
-#define __USB_H__\r
-#include "lpc_types.h"\r
-\r
-#if defined ( __GNUC__ )\r
-#define __packed __attribute__((__packed__))\r
-#endif\r
-\r
-#if defined ( __CC_ARM )\r
-typedef __packed union {\r
-#elif defined ( __GNUC__ )\r
-typedef union __packed {\r
-#elif defined ( __IAR_SYSTEMS_ICC__ )\r
-#pragma pack(1)\r
-typedef union {\r
-#endif\r
- uint16_t W;\r
-#if defined ( __CC_ARM )\r
- __packed struct {\r
-#elif defined ( __GNUC__ )\r
- struct __packed {\r
-#elif defined ( __IAR_SYSTEMS_ICC__ )\r
-#pragma pack(1)\r
- struct {\r
-#endif\r
- uint8_t L;\r
- uint8_t H;\r
- } WB;\r
-#ifdef __IAR_SYSTEMS_ICC__\r
-#pragma pack()\r
-#endif\r
-} WORD_BYTE;\r
-#ifdef __IAR_SYSTEMS_ICC__\r
-#pragma pack()\r
-#endif\r
-\r
-\r
-/* bmRequestType.Dir */\r
-#define REQUEST_HOST_TO_DEVICE 0\r
-#define REQUEST_DEVICE_TO_HOST 1\r
-\r
-/* bmRequestType.Type */\r
-#define REQUEST_STANDARD 0\r
-#define REQUEST_CLASS 1\r
-#define REQUEST_VENDOR 2\r
-#define REQUEST_RESERVED 3\r
-\r
-/* bmRequestType.Recipient */\r
-#define REQUEST_TO_DEVICE 0\r
-#define REQUEST_TO_INTERFACE 1\r
-#define REQUEST_TO_ENDPOINT 2\r
-#define REQUEST_TO_OTHER 3\r
-\r
-/* bmRequestType Definition */\r
-#if defined ( __CC_ARM )\r
-typedef __packed union _REQUEST_TYPE {\r
-#elif defined ( __GNUC__ )\r
-typedef union __packed _REQUEST_TYPE {\r
-#elif defined ( __IAR_SYSTEMS_ICC__ )\r
-#pragma pack(1)\r
-typedef union _REQUEST_TYPE {\r
-#endif\r
-#if defined ( __CC_ARM )\r
- __packed struct _BM {\r
-#elif defined ( __GNUC__ )\r
- struct __packed _BM {\r
-#elif defined ( __IAR_SYSTEMS_ICC__ )\r
-#pragma pack(1)\r
- struct _BM {\r
-#endif\r
- uint8_t Recipient : 5;\r
- uint8_t Type : 2;\r
- uint8_t Dir : 1;\r
- } BM;\r
-#ifdef __IAR_SYSTEMS_ICC__\r
-#pragma pack()\r
-#endif\r
- uint8_t B;\r
-} REQUEST_TYPE;\r
-#ifdef __IAR_SYSTEMS_ICC__\r
-#pragma pack()\r
-#endif\r
-\r
-/* USB Standard Request Codes */\r
-#define USB_REQUEST_GET_STATUS 0\r
-#define USB_REQUEST_CLEAR_FEATURE 1\r
-#define USB_REQUEST_SET_FEATURE 3\r
-#define USB_REQUEST_SET_ADDRESS 5\r
-#define USB_REQUEST_GET_DESCRIPTOR 6\r
-#define USB_REQUEST_SET_DESCRIPTOR 7\r
-#define USB_REQUEST_GET_CONFIGURATION 8\r
-#define USB_REQUEST_SET_CONFIGURATION 9\r
-#define USB_REQUEST_GET_INTERFACE 10\r
-#define USB_REQUEST_SET_INTERFACE 11\r
-#define USB_REQUEST_SYNC_FRAME 12\r
-\r
-/* USB GET_STATUS Bit Values */\r
-#define USB_GETSTATUS_SELF_POWERED 0x01\r
-#define USB_GETSTATUS_REMOTE_WAKEUP 0x02\r
-#define USB_GETSTATUS_ENDPOINT_STALL 0x01\r
-\r
-/* USB Standard Feature selectors */\r
-#define USB_FEATURE_ENDPOINT_STALL 0\r
-#define USB_FEATURE_REMOTE_WAKEUP 1\r
-\r
-/* USB Default Control Pipe Setup Packet */\r
-#if defined ( __CC_ARM )\r
-typedef __packed struct _USB_SETUP_PACKET {\r
-#elif defined ( __GNUC__ )\r
-typedef struct __packed _USB_SETUP_PACKET {\r
-#elif defined ( __IAR_SYSTEMS_ICC__ )\r
-#pragma pack(1)\r
-typedef struct _USB_SETUP_PACKET {\r
-#endif\r
- REQUEST_TYPE bmRequestType;\r
- uint8_t bRequest;\r
- WORD_BYTE wValue;\r
- WORD_BYTE wIndex;\r
- uint16_t wLength;\r
-} USB_SETUP_PACKET;\r
-#ifdef __IAR_SYSTEMS_ICC__\r
-#pragma pack()\r
-#endif\r
-\r
-\r
-/* USB Descriptor Types */\r
-#define USB_DEVICE_DESCRIPTOR_TYPE 1\r
-#define USB_CONFIGURATION_DESCRIPTOR_TYPE 2\r
-#define USB_STRING_DESCRIPTOR_TYPE 3\r
-#define USB_INTERFACE_DESCRIPTOR_TYPE 4\r
-#define USB_ENDPOINT_DESCRIPTOR_TYPE 5\r
-#define USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE 6\r
-#define USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE 7\r
-#define USB_INTERFACE_POWER_DESCRIPTOR_TYPE 8\r
-#define USB_OTG_DESCRIPTOR_TYPE 9\r
-#define USB_DEBUG_DESCRIPTOR_TYPE 10\r
-#define USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE 11\r
-\r
-/* USB Device Classes */\r
-#define USB_DEVICE_CLASS_RESERVED 0x00\r
-#define USB_DEVICE_CLASS_AUDIO 0x01\r
-#define USB_DEVICE_CLASS_COMMUNICATIONS 0x02\r
-#define USB_DEVICE_CLASS_HUMAN_INTERFACE 0x03\r
-#define USB_DEVICE_CLASS_MONITOR 0x04\r
-#define USB_DEVICE_CLASS_PHYSICAL_INTERFACE 0x05\r
-#define USB_DEVICE_CLASS_POWER 0x06\r
-#define USB_DEVICE_CLASS_PRINTER 0x07\r
-#define USB_DEVICE_CLASS_STORAGE 0x08\r
-#define USB_DEVICE_CLASS_HUB 0x09\r
-#define USB_DEVICE_CLASS_MISCELLANEOUS 0xEF\r
-#define USB_DEVICE_CLASS_VENDOR_SPECIFIC 0xFF\r
-\r
-/* bmAttributes in Configuration Descriptor */\r
-#define USB_CONFIG_POWERED_MASK 0x40\r
-#define USB_CONFIG_BUS_POWERED 0x80\r
-#define USB_CONFIG_SELF_POWERED 0xC0\r
-#define USB_CONFIG_REMOTE_WAKEUP 0x20\r
-\r
-/* bMaxPower in Configuration Descriptor */\r
-#define USB_CONFIG_POWER_MA(mA) ((mA)/2)\r
-\r
-/* bEndpointAddress in Endpoint Descriptor */\r
-#define USB_ENDPOINT_DIRECTION_MASK 0x80\r
-#define USB_ENDPOINT_OUT(addr) ((addr) | 0x00)\r
-#define USB_ENDPOINT_IN(addr) ((addr) | 0x80)\r
-\r
-/* bmAttributes in Endpoint Descriptor */\r
-#define USB_ENDPOINT_TYPE_MASK 0x03\r
-#define USB_ENDPOINT_TYPE_CONTROL 0x00\r
-#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01\r
-#define USB_ENDPOINT_TYPE_BULK 0x02\r
-#define USB_ENDPOINT_TYPE_INTERRUPT 0x03\r
-#define USB_ENDPOINT_SYNC_MASK 0x0C\r
-#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION 0x00\r
-#define USB_ENDPOINT_SYNC_ASYNCHRONOUS 0x04\r
-#define USB_ENDPOINT_SYNC_ADAPTIVE 0x08\r
-#define USB_ENDPOINT_SYNC_SYNCHRONOUS 0x0C\r
-#define USB_ENDPOINT_USAGE_MASK 0x30\r
-#define USB_ENDPOINT_USAGE_DATA 0x00\r
-#define USB_ENDPOINT_USAGE_FEEDBACK 0x10\r
-#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK 0x20\r
-#define USB_ENDPOINT_USAGE_RESERVED 0x30\r
-\r
-/* USB Standard Device Descriptor */\r
-#if defined ( __CC_ARM )\r
-typedef __packed struct _USB_DEVICE_DESCRIPTOR {\r
-#elif defined ( __GNUC__ )\r
-typedef struct __packed _USB_DEVICE_DESCRIPTOR {\r
-#elif defined ( __IAR_SYSTEMS_ICC__ )\r
-#pragma pack(1)\r
-typedef struct _USB_DEVICE_DESCRIPTOR {\r
-#endif\r
- uint8_t bLength;\r
- uint8_t bDescriptorType;\r
- uint16_t bcdUSB;\r
- uint8_t bDeviceClass;\r
- uint8_t bDeviceSubClass;\r
- uint8_t bDeviceProtocol;\r
- uint8_t bMaxPacketSize0;\r
- uint16_t idVendor;\r
- uint16_t idProduct;\r
- uint16_t bcdDevice;\r
- uint8_t iManufacturer;\r
- uint8_t iProduct;\r
- uint8_t iSerialNumber;\r
- uint8_t bNumConfigurations;\r
-} USB_DEVICE_DESCRIPTOR;\r
-#ifdef __IAR_SYSTEMS_ICC__\r
-#pragma pack()\r
-#endif\r
-\r
-/* USB 2.0 Device Qualifier Descriptor */\r
-#if defined ( __CC_ARM )\r
-typedef __packed struct _USB_DEVICE_QUALIFIER_DESCRIPTOR {\r
-#elif defined ( __GNUC__ )\r
-typedef struct __packed _USB_DEVICE_QUALIFIER_DESCRIPTOR {\r
-#elif defined ( __IAR_SYSTEMS_ICC__ )\r
-#pragma pack(1)\r
-typedef struct _USB_DEVICE_QUALIFIER_DESCRIPTOR {\r
-#endif\r
- uint8_t bLength;\r
- uint8_t bDescriptorType;\r
- uint16_t bcdUSB;\r
- uint8_t bDeviceClass;\r
- uint8_t bDeviceSubClass;\r
- uint8_t bDeviceProtocol;\r
- uint8_t bMaxPacketSize0;\r
- uint8_t bNumConfigurations;\r
- uint8_t bReserved;\r
-} USB_DEVICE_QUALIFIER_DESCRIPTOR;\r
-#ifdef __IAR_SYSTEMS_ICC__\r
-#pragma pack()\r
-#endif\r
-\r
-#if defined ( __CC_ARM )\r
-typedef __packed struct _USB_CONFIGURATION_DESCRIPTOR {\r
-#elif defined ( __GNUC__ )\r
-typedef struct __packed _USB_CONFIGURATION_DESCRIPTOR {\r
-#elif defined ( __IAR_SYSTEMS_ICC__ )\r
-#pragma pack(1)\r
-typedef struct _USB_CONFIGURATION_DESCRIPTOR {\r
-#endif\r
- uint8_t bLength;\r
- uint8_t bDescriptorType;\r
- uint16_t wTotalLength;\r
- uint8_t bNumInterfaces;\r
- uint8_t bConfigurationValue;\r
- uint8_t iConfiguration;\r
- uint8_t bmAttributes;\r
- uint8_t bMaxPower;\r
-} USB_CONFIGURATION_DESCRIPTOR;\r
-#ifdef __IAR_SYSTEMS_ICC__\r
-#pragma pack()\r
-#endif\r
-\r
-/* USB Standard Interface Descriptor */\r
-#if defined ( __CC_ARM )\r
-typedef __packed struct _USB_INTERFACE_DESCRIPTOR {\r
-#elif defined ( __GNUC__ )\r
-typedef struct __packed _USB_INTERFACE_DESCRIPTOR {\r
-#elif defined ( __IAR_SYSTEMS_ICC__ )\r
-#pragma pack(1)\r
-typedef struct _USB_INTERFACE_DESCRIPTOR {\r
-#endif\r
- uint8_t bLength;\r
- uint8_t bDescriptorType;\r
- uint8_t bInterfaceNumber;\r
- uint8_t bAlternateSetting;\r
- uint8_t bNumEndpoints;\r
- uint8_t bInterfaceClass;\r
- uint8_t bInterfaceSubClass;\r
- uint8_t bInterfaceProtocol;\r
- uint8_t iInterface;\r
-} USB_INTERFACE_DESCRIPTOR;\r
-#ifdef __IAR_SYSTEMS_ICC__\r
-#pragma pack()\r
-#endif\r
-\r
-/* USB Standard Endpoint Descriptor */\r
-#if defined ( __CC_ARM )\r
-typedef __packed struct _USB_ENDPOINT_DESCRIPTOR {\r
-#elif defined ( __GNUC__ )\r
-typedef struct __packed _USB_ENDPOINT_DESCRIPTOR {\r
-#elif defined ( __IAR_SYSTEMS_ICC__ )\r
-#pragma pack(1)\r
-typedef struct _USB_ENDPOINT_DESCRIPTOR {\r
-#endif\r
- uint8_t bLength;\r
- uint8_t bDescriptorType;\r
- uint8_t bEndpointAddress;\r
- uint8_t bmAttributes;\r
- uint16_t wMaxPacketSize;\r
- uint8_t bInterval;\r
-} USB_ENDPOINT_DESCRIPTOR;\r
-#ifdef __IAR_SYSTEMS_ICC__\r
-#pragma pack()\r
-#endif\r
-\r
-/* USB String Descriptor */\r
-#if defined ( __CC_ARM )\r
-typedef __packed struct _USB_STRING_DESCRIPTOR {\r
-#elif defined ( __GNUC__ )\r
-typedef struct __packed _USB_STRING_DESCRIPTOR {\r
-#elif defined ( __IAR_SYSTEMS_ICC__ )\r
-#pragma pack(1)\r
-typedef struct _USB_STRING_DESCRIPTOR {\r
-#endif\r
- uint8_t bLength;\r
- uint8_t bDescriptorType;\r
- uint16_t bString/*[]*/;\r
-} USB_STRING_DESCRIPTOR;\r
-#ifdef __IAR_SYSTEMS_ICC__\r
-#pragma pack()\r
-#endif\r
-\r
-/* USB Common Descriptor */\r
-#if defined ( __CC_ARM )\r
-typedef __packed struct _USB_COMMON_DESCRIPTOR {\r
-#elif defined ( __GNUC__ )\r
-typedef struct __packed _USB_COMMON_DESCRIPTOR {\r
-#elif defined ( __IAR_SYSTEMS_ICC__ )\r
-#pragma pack(1)\r
-typedef struct _USB_COMMON_DESCRIPTOR {\r
-#endif\r
- uint8_t bLength;\r
- uint8_t bDescriptorType;\r
-} USB_COMMON_DESCRIPTOR;\r
-#ifdef __IAR_SYSTEMS_ICC__\r
-#pragma pack()\r
-#endif\r
-\r
-\r
-\r
-#endif /* __USB_H__ */\r
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: usb.h
+ * Purpose: USB Definitions
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC family microcontroller devices only. Nothing
+ * else gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#ifndef __USB_H__
+#define __USB_H__
+#include "lpc_types.h"
+
+#if defined ( __GNUC__ )
+#define __packed __attribute__((__packed__))
+#endif
+
+#if defined ( __CC_ARM )
+typedef __packed union {
+#elif defined ( __GNUC__ )
+typedef union __packed {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef union {
+#endif
+ uint16_t W;
+#if defined ( __CC_ARM )
+ __packed struct {
+#elif defined ( __GNUC__ )
+ struct __packed {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+ struct {
+#endif
+ uint8_t L;
+ uint8_t H;
+ } WB;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+} WORD_BYTE;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+
+
+/* bmRequestType.Dir */
+#define REQUEST_HOST_TO_DEVICE 0
+#define REQUEST_DEVICE_TO_HOST 1
+
+/* bmRequestType.Type */
+#define REQUEST_STANDARD 0
+#define REQUEST_CLASS 1
+#define REQUEST_VENDOR 2
+#define REQUEST_RESERVED 3
+
+/* bmRequestType.Recipient */
+#define REQUEST_TO_DEVICE 0
+#define REQUEST_TO_INTERFACE 1
+#define REQUEST_TO_ENDPOINT 2
+#define REQUEST_TO_OTHER 3
+
+/* bmRequestType Definition */
+#if defined ( __CC_ARM )
+typedef __packed union _REQUEST_TYPE {
+#elif defined ( __GNUC__ )
+typedef union __packed _REQUEST_TYPE {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef union _REQUEST_TYPE {
+#endif
+#if defined ( __CC_ARM )
+ __packed struct _BM {
+#elif defined ( __GNUC__ )
+ struct __packed _BM {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+ struct _BM {
+#endif
+ uint8_t Recipient : 5;
+ uint8_t Type : 2;
+ uint8_t Dir : 1;
+ } BM;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+ uint8_t B;
+} REQUEST_TYPE;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+
+/* USB Standard Request Codes */
+#define USB_REQUEST_GET_STATUS 0
+#define USB_REQUEST_CLEAR_FEATURE 1
+#define USB_REQUEST_SET_FEATURE 3
+#define USB_REQUEST_SET_ADDRESS 5
+#define USB_REQUEST_GET_DESCRIPTOR 6
+#define USB_REQUEST_SET_DESCRIPTOR 7
+#define USB_REQUEST_GET_CONFIGURATION 8
+#define USB_REQUEST_SET_CONFIGURATION 9
+#define USB_REQUEST_GET_INTERFACE 10
+#define USB_REQUEST_SET_INTERFACE 11
+#define USB_REQUEST_SYNC_FRAME 12
+
+/* USB GET_STATUS Bit Values */
+#define USB_GETSTATUS_SELF_POWERED 0x01
+#define USB_GETSTATUS_REMOTE_WAKEUP 0x02
+#define USB_GETSTATUS_ENDPOINT_STALL 0x01
+
+/* USB Standard Feature selectors */
+#define USB_FEATURE_ENDPOINT_STALL 0
+#define USB_FEATURE_REMOTE_WAKEUP 1
+
+/* USB Default Control Pipe Setup Packet */
+#if defined ( __CC_ARM )
+typedef __packed struct _USB_SETUP_PACKET {
+#elif defined ( __GNUC__ )
+typedef struct __packed _USB_SETUP_PACKET {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _USB_SETUP_PACKET {
+#endif
+ REQUEST_TYPE bmRequestType;
+ uint8_t bRequest;
+ WORD_BYTE wValue;
+ WORD_BYTE wIndex;
+ uint16_t wLength;
+} USB_SETUP_PACKET;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+
+
+/* USB Descriptor Types */
+#define USB_DEVICE_DESCRIPTOR_TYPE 1
+#define USB_CONFIGURATION_DESCRIPTOR_TYPE 2
+#define USB_STRING_DESCRIPTOR_TYPE 3
+#define USB_INTERFACE_DESCRIPTOR_TYPE 4
+#define USB_ENDPOINT_DESCRIPTOR_TYPE 5
+#define USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE 6
+#define USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE 7
+#define USB_INTERFACE_POWER_DESCRIPTOR_TYPE 8
+#define USB_OTG_DESCRIPTOR_TYPE 9
+#define USB_DEBUG_DESCRIPTOR_TYPE 10
+#define USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE 11
+
+/* USB Device Classes */
+#define USB_DEVICE_CLASS_RESERVED 0x00
+#define USB_DEVICE_CLASS_AUDIO 0x01
+#define USB_DEVICE_CLASS_COMMUNICATIONS 0x02
+#define USB_DEVICE_CLASS_HUMAN_INTERFACE 0x03
+#define USB_DEVICE_CLASS_MONITOR 0x04
+#define USB_DEVICE_CLASS_PHYSICAL_INTERFACE 0x05
+#define USB_DEVICE_CLASS_POWER 0x06
+#define USB_DEVICE_CLASS_PRINTER 0x07
+#define USB_DEVICE_CLASS_STORAGE 0x08
+#define USB_DEVICE_CLASS_HUB 0x09
+#define USB_DEVICE_CLASS_MISCELLANEOUS 0xEF
+#define USB_DEVICE_CLASS_VENDOR_SPECIFIC 0xFF
+
+/* bmAttributes in Configuration Descriptor */
+#define USB_CONFIG_POWERED_MASK 0x40
+#define USB_CONFIG_BUS_POWERED 0x80
+#define USB_CONFIG_SELF_POWERED 0xC0
+#define USB_CONFIG_REMOTE_WAKEUP 0x20
+
+/* bMaxPower in Configuration Descriptor */
+#define USB_CONFIG_POWER_MA(mA) ((mA)/2)
+
+/* bEndpointAddress in Endpoint Descriptor */
+#define USB_ENDPOINT_DIRECTION_MASK 0x80
+#define USB_ENDPOINT_OUT(addr) ((addr) | 0x00)
+#define USB_ENDPOINT_IN(addr) ((addr) | 0x80)
+
+/* bmAttributes in Endpoint Descriptor */
+#define USB_ENDPOINT_TYPE_MASK 0x03
+#define USB_ENDPOINT_TYPE_CONTROL 0x00
+#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01
+#define USB_ENDPOINT_TYPE_BULK 0x02
+#define USB_ENDPOINT_TYPE_INTERRUPT 0x03
+#define USB_ENDPOINT_SYNC_MASK 0x0C
+#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION 0x00
+#define USB_ENDPOINT_SYNC_ASYNCHRONOUS 0x04
+#define USB_ENDPOINT_SYNC_ADAPTIVE 0x08
+#define USB_ENDPOINT_SYNC_SYNCHRONOUS 0x0C
+#define USB_ENDPOINT_USAGE_MASK 0x30
+#define USB_ENDPOINT_USAGE_DATA 0x00
+#define USB_ENDPOINT_USAGE_FEEDBACK 0x10
+#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK 0x20
+#define USB_ENDPOINT_USAGE_RESERVED 0x30
+
+/* USB Standard Device Descriptor */
+#if defined ( __CC_ARM )
+typedef __packed struct _USB_DEVICE_DESCRIPTOR {
+#elif defined ( __GNUC__ )
+typedef struct __packed _USB_DEVICE_DESCRIPTOR {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _USB_DEVICE_DESCRIPTOR {
+#endif
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint16_t bcdUSB;
+ uint8_t bDeviceClass;
+ uint8_t bDeviceSubClass;
+ uint8_t bDeviceProtocol;
+ uint8_t bMaxPacketSize0;
+ uint16_t idVendor;
+ uint16_t idProduct;
+ uint16_t bcdDevice;
+ uint8_t iManufacturer;
+ uint8_t iProduct;
+ uint8_t iSerialNumber;
+ uint8_t bNumConfigurations;
+} USB_DEVICE_DESCRIPTOR;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+
+/* USB 2.0 Device Qualifier Descriptor */
+#if defined ( __CC_ARM )
+typedef __packed struct _USB_DEVICE_QUALIFIER_DESCRIPTOR {
+#elif defined ( __GNUC__ )
+typedef struct __packed _USB_DEVICE_QUALIFIER_DESCRIPTOR {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _USB_DEVICE_QUALIFIER_DESCRIPTOR {
+#endif
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint16_t bcdUSB;
+ uint8_t bDeviceClass;
+ uint8_t bDeviceSubClass;
+ uint8_t bDeviceProtocol;
+ uint8_t bMaxPacketSize0;
+ uint8_t bNumConfigurations;
+ uint8_t bReserved;
+} USB_DEVICE_QUALIFIER_DESCRIPTOR;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+
+#if defined ( __CC_ARM )
+typedef __packed struct _USB_CONFIGURATION_DESCRIPTOR {
+#elif defined ( __GNUC__ )
+typedef struct __packed _USB_CONFIGURATION_DESCRIPTOR {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _USB_CONFIGURATION_DESCRIPTOR {
+#endif
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint16_t wTotalLength;
+ uint8_t bNumInterfaces;
+ uint8_t bConfigurationValue;
+ uint8_t iConfiguration;
+ uint8_t bmAttributes;
+ uint8_t bMaxPower;
+} USB_CONFIGURATION_DESCRIPTOR;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+
+/* USB Standard Interface Descriptor */
+#if defined ( __CC_ARM )
+typedef __packed struct _USB_INTERFACE_DESCRIPTOR {
+#elif defined ( __GNUC__ )
+typedef struct __packed _USB_INTERFACE_DESCRIPTOR {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _USB_INTERFACE_DESCRIPTOR {
+#endif
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bInterfaceNumber;
+ uint8_t bAlternateSetting;
+ uint8_t bNumEndpoints;
+ uint8_t bInterfaceClass;
+ uint8_t bInterfaceSubClass;
+ uint8_t bInterfaceProtocol;
+ uint8_t iInterface;
+} USB_INTERFACE_DESCRIPTOR;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+
+/* USB Standard Endpoint Descriptor */
+#if defined ( __CC_ARM )
+typedef __packed struct _USB_ENDPOINT_DESCRIPTOR {
+#elif defined ( __GNUC__ )
+typedef struct __packed _USB_ENDPOINT_DESCRIPTOR {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _USB_ENDPOINT_DESCRIPTOR {
+#endif
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bEndpointAddress;
+ uint8_t bmAttributes;
+ uint16_t wMaxPacketSize;
+ uint8_t bInterval;
+} USB_ENDPOINT_DESCRIPTOR;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+
+/* USB String Descriptor */
+#if defined ( __CC_ARM )
+typedef __packed struct _USB_STRING_DESCRIPTOR {
+#elif defined ( __GNUC__ )
+typedef struct __packed _USB_STRING_DESCRIPTOR {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _USB_STRING_DESCRIPTOR {
+#endif
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint16_t bString/*[]*/;
+} USB_STRING_DESCRIPTOR;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+
+/* USB Common Descriptor */
+#if defined ( __CC_ARM )
+typedef __packed struct _USB_COMMON_DESCRIPTOR {
+#elif defined ( __GNUC__ )
+typedef struct __packed _USB_COMMON_DESCRIPTOR {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _USB_COMMON_DESCRIPTOR {
+#endif
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+} USB_COMMON_DESCRIPTOR;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+
+
+
+#endif /* __USB_H__ */
-/*----------------------------------------------------------------------------\r
- * U S B - K e r n e l\r
- *----------------------------------------------------------------------------\r
- * Name: usbuser.c\r
- * Purpose: USB Custom User Module\r
- * Version: V1.20\r
- *----------------------------------------------------------------------------\r
- * This software is supplied "AS IS" without any warranties, express,\r
- * implied or statutory, including but not limited to the implied\r
- * warranties of fitness for purpose, satisfactory quality and\r
- * noninfringement. Keil extends you a royalty-free right to reproduce\r
- * and distribute executable files created using this software for use\r
- * on NXP Semiconductors LPC family microcontroller devices only. Nothing\r
- * else gives you the right to use this software.\r
- *\r
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
- *---------------------------------------------------------------------------*/\r
-#include "lpc_types.h"\r
-\r
-#include "usb.h"\r
-#include "usbcfg.h"\r
-#include "usbhw.h"\r
-#include "usbcore.h"\r
-#include "usbuser.h"\r
-#include "cdcuser.h"\r
-\r
-\r
-/*\r
- * USB Power Event Callback\r
- * Called automatically on USB Power Event\r
- * Parameter: power: On(TRUE)/Off(FALSE)\r
- */\r
-\r
-#if USB_POWER_EVENT\r
-void USB_Power_Event (uint32_t power) {\r
-}\r
-#endif\r
-\r
-\r
-/*\r
- * USB Reset Event Callback\r
- * Called automatically on USB Reset Event\r
- */\r
-\r
-#if USB_RESET_EVENT\r
-void USB_Reset_Event (void) {\r
- USB_ResetCore();\r
-}\r
-#endif\r
-\r
-\r
-/*\r
- * USB Suspend Event Callback\r
- * Called automatically on USB Suspend Event\r
- */\r
-\r
-#if USB_SUSPEND_EVENT\r
-void USB_Suspend_Event (void) {\r
-}\r
-#endif\r
-\r
-\r
-/*\r
- * USB Resume Event Callback\r
- * Called automatically on USB Resume Event\r
- */\r
-\r
-#if USB_RESUME_EVENT\r
-void USB_Resume_Event (void) {\r
-}\r
-#endif\r
-\r
-\r
-/*\r
- * USB Remote Wakeup Event Callback\r
- * Called automatically on USB Remote Wakeup Event\r
- */\r
-\r
-#if USB_WAKEUP_EVENT\r
-void USB_WakeUp_Event (void) {\r
-}\r
-#endif\r
-\r
-\r
-/*\r
- * USB Start of Frame Event Callback\r
- * Called automatically on USB Start of Frame Event\r
- */\r
-\r
-#if USB_SOF_EVENT\r
-void USB_SOF_Event (void) {\r
-}\r
-#endif\r
-\r
-\r
-/*\r
- * USB Error Event Callback\r
- * Called automatically on USB Error Event\r
- * Parameter: error: Error Code\r
- */\r
-\r
-#if USB_ERROR_EVENT\r
-void USB_Error_Event (uint32_t error) {\r
-}\r
-#endif\r
-\r
-\r
-/*\r
- * USB Set Configuration Event Callback\r
- * Called automatically on USB Set Configuration Request\r
- */\r
-\r
-#if USB_CONFIGURE_EVENT\r
-void USB_Configure_Event (void) {\r
-\r
- if (USB_Configuration) { /* Check if USB is configured */\r
- /* add your code here */\r
- }\r
-}\r
-#endif\r
-\r
-\r
-/*\r
- * USB Set Interface Event Callback\r
- * Called automatically on USB Set Interface Request\r
- */\r
-\r
-#if USB_INTERFACE_EVENT\r
-void USB_Interface_Event (void) {\r
-}\r
-#endif\r
-\r
-\r
-/*\r
- * USB Set/Clear Feature Event Callback\r
- * Called automatically on USB Set/Clear Feature Request\r
- */\r
-\r
-#if USB_FEATURE_EVENT\r
-void USB_Feature_Event (void) {\r
-}\r
-#endif\r
-\r
-\r
-#define P_EP(n) ((USB_EP_EVENT & (1 << (n))) ? USB_EndPoint##n : NULL)\r
-\r
-/* USB Endpoint Events Callback Pointers */\r
-void (* const USB_P_EP[16]) (uint32_t event) = {\r
- P_EP(0),\r
- P_EP(1),\r
- P_EP(2),\r
- P_EP(3),\r
- P_EP(4),\r
- P_EP(5),\r
- P_EP(6),\r
- P_EP(7),\r
- P_EP(8),\r
- P_EP(9),\r
- P_EP(10),\r
- P_EP(11),\r
- P_EP(12),\r
- P_EP(13),\r
- P_EP(14),\r
- P_EP(15),\r
-};\r
-\r
-\r
-/*\r
- * USB Endpoint 1 Event Callback\r
- * Called automatically on USB Endpoint 1 Event\r
- * Parameter: event\r
- */\r
-\r
-void USB_EndPoint1 (uint32_t event) {\r
- uint16_t temp;\r
- static uint16_t serialState;\r
-\r
- switch (event) {\r
- case USB_EVT_IN:\r
- temp = CDC_GetSerialState();\r
- if (serialState != temp) {\r
- serialState = temp;\r
- CDC_NotificationIn(); /* send SERIAL_STATE notification */\r
- }\r
- break;\r
- }\r
-}\r
-\r
-\r
-/*\r
- * USB Endpoint 2 Event Callback\r
- * Called automatically on USB Endpoint 2 Event\r
- * Parameter: event\r
- */\r
-\r
-void USB_EndPoint2 (uint32_t event) {\r
-\r
- switch (event) {\r
- case USB_EVT_OUT:\r
- CDC_BulkOut (); /* data received from Host */\r
- break;\r
- case USB_EVT_IN:\r
- CDC_BulkIn (); /* data expected from Host */\r
- break;\r
- }\r
-}\r
-\r
-\r
-/*\r
- * USB Endpoint 3 Event Callback\r
- * Called automatically on USB Endpoint 3 Event\r
- * Parameter: event\r
- */\r
-\r
-void USB_EndPoint3 (uint32_t event) {\r
-}\r
-\r
-\r
-/*\r
- * USB Endpoint 4 Event Callback\r
- * Called automatically on USB Endpoint 4 Event\r
- * Parameter: event\r
- */\r
-\r
-void USB_EndPoint4 (uint32_t event) {\r
-}\r
-\r
-\r
-/*\r
- * USB Endpoint 5 Event Callback\r
- * Called automatically on USB Endpoint 5 Event\r
- * Parameter: event\r
- */\r
-\r
-void USB_EndPoint5 (uint32_t event) {\r
-}\r
-\r
-\r
-/*\r
- * USB Endpoint 6 Event Callback\r
- * Called automatically on USB Endpoint 6 Event\r
- * Parameter: event\r
- */\r
-\r
-void USB_EndPoint6 (uint32_t event) {\r
-}\r
-\r
-\r
-/*\r
- * USB Endpoint 7 Event Callback\r
- * Called automatically on USB Endpoint 7 Event\r
- * Parameter: event\r
- */\r
-\r
-void USB_EndPoint7 (uint32_t event) {\r
-}\r
-\r
-\r
-/*\r
- * USB Endpoint 8 Event Callback\r
- * Called automatically on USB Endpoint 8 Event\r
- * Parameter: event\r
- */\r
-\r
-void USB_EndPoint8 (uint32_t event) {\r
-}\r
-\r
-\r
-/*\r
- * USB Endpoint 9 Event Callback\r
- * Called automatically on USB Endpoint 9 Event\r
- * Parameter: event\r
- */\r
-\r
-void USB_EndPoint9 (uint32_t event) {\r
-}\r
-\r
-\r
-/*\r
- * USB Endpoint 10 Event Callback\r
- * Called automatically on USB Endpoint 10 Event\r
- * Parameter: event\r
- */\r
-\r
-void USB_EndPoint10 (uint32_t event) {\r
-}\r
-\r
-\r
-/*\r
- * USB Endpoint 11 Event Callback\r
- * Called automatically on USB Endpoint 11 Event\r
- * Parameter: event\r
- */\r
-\r
-void USB_EndPoint11 (uint32_t event) {\r
-}\r
-\r
-\r
-/*\r
- * USB Endpoint 12 Event Callback\r
- * Called automatically on USB Endpoint 12 Event\r
- * Parameter: event\r
- */\r
-\r
-void USB_EndPoint12 (uint32_t event) {\r
-}\r
-\r
-\r
-/*\r
- * USB Endpoint 13 Event Callback\r
- * Called automatically on USB Endpoint 13 Event\r
- * Parameter: event\r
- */\r
-\r
-void USB_EndPoint13 (uint32_t event) {\r
-}\r
-\r
-\r
-/*\r
- * USB Endpoint 14 Event Callback\r
- * Called automatically on USB Endpoint 14 Event\r
- * Parameter: event\r
- */\r
-\r
-void USB_EndPoint14 (uint32_t event) {\r
-}\r
-\r
-\r
-/*\r
- * USB Endpoint 15 Event Callback\r
- * Called automatically on USB Endpoint 15 Event\r
- * Parameter: event\r
- */\r
-\r
-void USB_EndPoint15 (uint32_t event) {\r
-}\r
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: usbuser.c
+ * Purpose: USB Custom User Module
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC family microcontroller devices only. Nothing
+ * else gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+#include "lpc_types.h"
+
+#include "usb.h"
+#include "cfg.h"
+#include "hw.h"
+#include "core.h"
+#include "user.h"
+#include "cdcuser.h"
+
+
+/*
+ * USB Power Event Callback
+ * Called automatically on USB Power Event
+ * Parameter: power: On(TRUE)/Off(FALSE)
+ */
+
+#if USB_POWER_EVENT
+void USB_Power_Event (uint32_t power) {
+}
+#endif
+
+
+/*
+ * USB Reset Event Callback
+ * Called automatically on USB Reset Event
+ */
+
+#if USB_RESET_EVENT
+void USB_Reset_Event (void) {
+ USB_ResetCore();
+}
+#endif
+
+
+/*
+ * USB Suspend Event Callback
+ * Called automatically on USB Suspend Event
+ */
+
+#if USB_SUSPEND_EVENT
+void USB_Suspend_Event (void) {
+}
+#endif
+
+
+/*
+ * USB Resume Event Callback
+ * Called automatically on USB Resume Event
+ */
+
+#if USB_RESUME_EVENT
+void USB_Resume_Event (void) {
+}
+#endif
+
+
+/*
+ * USB Remote Wakeup Event Callback
+ * Called automatically on USB Remote Wakeup Event
+ */
+
+#if USB_WAKEUP_EVENT
+void USB_WakeUp_Event (void) {
+}
+#endif
+
+
+/*
+ * USB Start of Frame Event Callback
+ * Called automatically on USB Start of Frame Event
+ */
+
+#if USB_SOF_EVENT
+void USB_SOF_Event (void) {
+}
+#endif
+
+
+/*
+ * USB Error Event Callback
+ * Called automatically on USB Error Event
+ * Parameter: error: Error Code
+ */
+
+#if USB_ERROR_EVENT
+void USB_Error_Event (uint32_t error) {
+}
+#endif
+
+
+/*
+ * USB Set Configuration Event Callback
+ * Called automatically on USB Set Configuration Request
+ */
+
+#if USB_CONFIGURE_EVENT
+void USB_Configure_Event (void) {
+
+ if (USB_Configuration) { /* Check if USB is configured */
+ /* add your code here */
+ }
+}
+#endif
+
+
+/*
+ * USB Set Interface Event Callback
+ * Called automatically on USB Set Interface Request
+ */
+
+#if USB_INTERFACE_EVENT
+void USB_Interface_Event (void) {
+}
+#endif
+
+
+/*
+ * USB Set/Clear Feature Event Callback
+ * Called automatically on USB Set/Clear Feature Request
+ */
+
+#if USB_FEATURE_EVENT
+void USB_Feature_Event (void) {
+}
+#endif
+
+
+#define P_EP(n) ((USB_EP_EVENT & (1 << (n))) ? USB_EndPoint##n : NULL)
+
+/* USB Endpoint Events Callback Pointers */
+void (* const USB_P_EP[16]) (uint32_t event) = {
+ P_EP(0),
+ P_EP(1),
+ P_EP(2),
+ P_EP(3),
+ P_EP(4),
+ P_EP(5),
+ P_EP(6),
+ P_EP(7),
+ P_EP(8),
+ P_EP(9),
+ P_EP(10),
+ P_EP(11),
+ P_EP(12),
+ P_EP(13),
+ P_EP(14),
+ P_EP(15),
+};
+
+
+/*
+ * USB Endpoint 1 Event Callback
+ * Called automatically on USB Endpoint 1 Event
+ * Parameter: event
+ */
+
+void USB_EndPoint1 (uint32_t event) {
+ uint16_t temp;
+ static uint16_t serialState;
+
+ switch (event) {
+ case USB_EVT_IN:
+ temp = CDC_GetSerialState();
+ if (serialState != temp) {
+ serialState = temp;
+ CDC_NotificationIn(); /* send SERIAL_STATE notification */
+ }
+ break;
+ }
+}
+
+
+/*
+ * USB Endpoint 2 Event Callback
+ * Called automatically on USB Endpoint 2 Event
+ * Parameter: event
+ */
+
+void USB_EndPoint2 (uint32_t event) {
+
+ switch (event) {
+ case USB_EVT_OUT:
+ CDC_BulkOut (); /* data received from Host */
+ break;
+ case USB_EVT_IN:
+ CDC_BulkIn (); /* data expected from Host */
+ break;
+ }
+}
+
+
+/*
+ * USB Endpoint 3 Event Callback
+ * Called automatically on USB Endpoint 3 Event
+ * Parameter: event
+ */
+
+void USB_EndPoint3 (uint32_t event) {
+}
+
+
+/*
+ * USB Endpoint 4 Event Callback
+ * Called automatically on USB Endpoint 4 Event
+ * Parameter: event
+ */
+
+void USB_EndPoint4 (uint32_t event) {
+}
+
+
+/*
+ * USB Endpoint 5 Event Callback
+ * Called automatically on USB Endpoint 5 Event
+ * Parameter: event
+ */
+
+void USB_EndPoint5 (uint32_t event) {
+}
+
+
+/*
+ * USB Endpoint 6 Event Callback
+ * Called automatically on USB Endpoint 6 Event
+ * Parameter: event
+ */
+
+void USB_EndPoint6 (uint32_t event) {
+}
+
+
+/*
+ * USB Endpoint 7 Event Callback
+ * Called automatically on USB Endpoint 7 Event
+ * Parameter: event
+ */
+
+void USB_EndPoint7 (uint32_t event) {
+}
+
+
+/*
+ * USB Endpoint 8 Event Callback
+ * Called automatically on USB Endpoint 8 Event
+ * Parameter: event
+ */
+
+void USB_EndPoint8 (uint32_t event) {
+}
+
+
+/*
+ * USB Endpoint 9 Event Callback
+ * Called automatically on USB Endpoint 9 Event
+ * Parameter: event
+ */
+
+void USB_EndPoint9 (uint32_t event) {
+}
+
+
+/*
+ * USB Endpoint 10 Event Callback
+ * Called automatically on USB Endpoint 10 Event
+ * Parameter: event
+ */
+
+void USB_EndPoint10 (uint32_t event) {
+}
+
+
+/*
+ * USB Endpoint 11 Event Callback
+ * Called automatically on USB Endpoint 11 Event
+ * Parameter: event
+ */
+
+void USB_EndPoint11 (uint32_t event) {
+}
+
+
+/*
+ * USB Endpoint 12 Event Callback
+ * Called automatically on USB Endpoint 12 Event
+ * Parameter: event
+ */
+
+void USB_EndPoint12 (uint32_t event) {
+}
+
+
+/*
+ * USB Endpoint 13 Event Callback
+ * Called automatically on USB Endpoint 13 Event
+ * Parameter: event
+ */
+
+void USB_EndPoint13 (uint32_t event) {
+}
+
+
+/*
+ * USB Endpoint 14 Event Callback
+ * Called automatically on USB Endpoint 14 Event
+ * Parameter: event
+ */
+
+void USB_EndPoint14 (uint32_t event) {
+}
+
+
+/*
+ * USB Endpoint 15 Event Callback
+ * Called automatically on USB Endpoint 15 Event
+ * Parameter: event
+ */
+
+void USB_EndPoint15 (uint32_t event) {
+}
-/*----------------------------------------------------------------------------\r
- * U S B - K e r n e l\r
- *----------------------------------------------------------------------------\r
- * Name: usbuser.h\r
- * Purpose: USB Custom User Definitions\r
- * Version: V1.20\r
- *----------------------------------------------------------------------------\r
- * This software is supplied "AS IS" without any warranties, express,\r
- * implied or statutory, including but not limited to the implied\r
- * warranties of fitness for purpose, satisfactory quality and\r
- * noninfringement. Keil extends you a royalty-free right to reproduce\r
- * and distribute executable files created using this software for use\r
- * on NXP Semiconductors LPC family microcontroller devices only. Nothing \r
- * else gives you the right to use this software.\r
- *\r
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
- *---------------------------------------------------------------------------*/\r
-\r
-#ifndef __USBUSER_H__\r
-#define __USBUSER_H__\r
-\r
-\r
-/* USB Device Events Callback Functions */\r
-extern void USB_Power_Event (uint32_t power);\r
-extern void USB_Reset_Event (void);\r
-extern void USB_Suspend_Event (void);\r
-extern void USB_Resume_Event (void);\r
-extern void USB_WakeUp_Event (void);\r
-extern void USB_SOF_Event (void);\r
-extern void USB_Error_Event (uint32_t error);\r
-\r
-/* USB Endpoint Callback Events */\r
-#define USB_EVT_SETUP 1 /* Setup Packet */\r
-#define USB_EVT_OUT 2 /* OUT Packet */\r
-#define USB_EVT_IN 3 /* IN Packet */\r
-#define USB_EVT_OUT_NAK 4 /* OUT Packet - Not Acknowledged */\r
-#define USB_EVT_IN_NAK 5 /* IN Packet - Not Acknowledged */\r
-#define USB_EVT_OUT_STALL 6 /* OUT Packet - Stalled */\r
-#define USB_EVT_IN_STALL 7 /* IN Packet - Stalled */\r
-#define USB_EVT_OUT_DMA_EOT 8 /* DMA OUT EP - End of Transfer */\r
-#define USB_EVT_IN_DMA_EOT 9 /* DMA IN EP - End of Transfer */\r
-#define USB_EVT_OUT_DMA_NDR 10 /* DMA OUT EP - New Descriptor Request */\r
-#define USB_EVT_IN_DMA_NDR 11 /* DMA IN EP - New Descriptor Request */\r
-#define USB_EVT_OUT_DMA_ERR 12 /* DMA OUT EP - Error */\r
-#define USB_EVT_IN_DMA_ERR 13 /* DMA IN EP - Error */\r
-\r
-/* USB Endpoint Events Callback Pointers */\r
-extern void (* const USB_P_EP[16])(uint32_t event);\r
-\r
-/* USB Endpoint Events Callback Functions */\r
-extern void USB_EndPoint0 (uint32_t event);\r
-extern void USB_EndPoint1 (uint32_t event);\r
-extern void USB_EndPoint2 (uint32_t event);\r
-extern void USB_EndPoint3 (uint32_t event);\r
-extern void USB_EndPoint4 (uint32_t event);\r
-extern void USB_EndPoint5 (uint32_t event);\r
-extern void USB_EndPoint6 (uint32_t event);\r
-extern void USB_EndPoint7 (uint32_t event);\r
-extern void USB_EndPoint8 (uint32_t event);\r
-extern void USB_EndPoint9 (uint32_t event);\r
-extern void USB_EndPoint10 (uint32_t event);\r
-extern void USB_EndPoint11 (uint32_t event);\r
-extern void USB_EndPoint12 (uint32_t event);\r
-extern void USB_EndPoint13 (uint32_t event);\r
-extern void USB_EndPoint14 (uint32_t event);\r
-extern void USB_EndPoint15 (uint32_t event);\r
-\r
-/* USB Core Events Callback Functions */\r
-extern void USB_Configure_Event (void);\r
-extern void USB_Interface_Event (void);\r
-extern void USB_Feature_Event (void);\r
-\r
-\r
-#endif /* __USBUSER_H__ */\r
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: usbuser.h
+ * Purpose: USB Custom User Definitions
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC family microcontroller devices only. Nothing
+ * else gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#ifndef __USBUSER_H__
+#define __USBUSER_H__
+
+
+/* USB Device Events Callback Functions */
+extern void USB_Power_Event (uint32_t power);
+extern void USB_Reset_Event (void);
+extern void USB_Suspend_Event (void);
+extern void USB_Resume_Event (void);
+extern void USB_WakeUp_Event (void);
+extern void USB_SOF_Event (void);
+extern void USB_Error_Event (uint32_t error);
+
+/* USB Endpoint Callback Events */
+#define USB_EVT_SETUP 1 /* Setup Packet */
+#define USB_EVT_OUT 2 /* OUT Packet */
+#define USB_EVT_IN 3 /* IN Packet */
+#define USB_EVT_OUT_NAK 4 /* OUT Packet - Not Acknowledged */
+#define USB_EVT_IN_NAK 5 /* IN Packet - Not Acknowledged */
+#define USB_EVT_OUT_STALL 6 /* OUT Packet - Stalled */
+#define USB_EVT_IN_STALL 7 /* IN Packet - Stalled */
+#define USB_EVT_OUT_DMA_EOT 8 /* DMA OUT EP - End of Transfer */
+#define USB_EVT_IN_DMA_EOT 9 /* DMA IN EP - End of Transfer */
+#define USB_EVT_OUT_DMA_NDR 10 /* DMA OUT EP - New Descriptor Request */
+#define USB_EVT_IN_DMA_NDR 11 /* DMA IN EP - New Descriptor Request */
+#define USB_EVT_OUT_DMA_ERR 12 /* DMA OUT EP - Error */
+#define USB_EVT_IN_DMA_ERR 13 /* DMA IN EP - Error */
+
+/* USB Endpoint Events Callback Pointers */
+extern void (* const USB_P_EP[16])(uint32_t event);
+
+/* USB Endpoint Events Callback Functions */
+extern void USB_EndPoint0 (uint32_t event);
+extern void USB_EndPoint1 (uint32_t event);
+extern void USB_EndPoint2 (uint32_t event);
+extern void USB_EndPoint3 (uint32_t event);
+extern void USB_EndPoint4 (uint32_t event);
+extern void USB_EndPoint5 (uint32_t event);
+extern void USB_EndPoint6 (uint32_t event);
+extern void USB_EndPoint7 (uint32_t event);
+extern void USB_EndPoint8 (uint32_t event);
+extern void USB_EndPoint9 (uint32_t event);
+extern void USB_EndPoint10 (uint32_t event);
+extern void USB_EndPoint11 (uint32_t event);
+extern void USB_EndPoint12 (uint32_t event);
+extern void USB_EndPoint13 (uint32_t event);
+extern void USB_EndPoint14 (uint32_t event);
+extern void USB_EndPoint15 (uint32_t event);
+
+/* USB Core Events Callback Functions */
+extern void USB_Configure_Event (void);
+extern void USB_Interface_Event (void);
+extern void USB_Feature_Event (void);
+
+
+#endif /* __USBUSER_H__ */
-/*----------------------------------------------------------------------------\r
- * Name: vcomdemo.c\r
- * Purpose: USB virtual COM port Demo\r
- * Version: V1.20\r
- *----------------------------------------------------------------------------\r
- * This software is supplied "AS IS" without any warranties, express,\r
- * implied or statutory, including but not limited to the implied\r
- * warranties of fitness for purpose, satisfactory quality and\r
- * noninfringement. Keil extends you a royalty-free right to reproduce\r
- * and distribute executable files created using this software for use\r
- * on NXP Semiconductors LPC microcontroller devices only. Nothing else\r
- * gives you the right to use this software.\r
- *\r
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
- *---------------------------------------------------------------------------*/\r
-\r
-#include "../LPC17xx.h"\r
-#include "lpc_types.h"\r
-\r
-#include "usb.h"\r
-#include "usbcfg.h"\r
-#include "usbhw.h"\r
-#include "usbcore.h"\r
-#include "cdc.h"\r
-#include "cdcuser.h"\r
-#include "serial.h"\r
-#include "vcomdemo.h"\r
-\r
-/* Example group ----------------------------------------------------------- */\r
-/** @defgroup USBDEV_USBCDC USBCDC\r
- * @ingroup USBDEV_Examples\r
- * @{\r
- */\r
-\r
-/*----------------------------------------------------------------------------\r
- Initialises the VCOM port.\r
- Call this function before using VCOM_putchar or VCOM_getchar\r
- *---------------------------------------------------------------------------*/\r
-void VCOM_Init(void) {\r
-#if PORT_NUM\r
- CDC_Init (1);\r
-#else\r
- CDC_Init (0);\r
-#endif\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- Reads character from serial port buffer and writes to USB buffer\r
- *---------------------------------------------------------------------------*/\r
-void VCOM_Serial2Usb(void) {\r
- static char serBuf [USB_CDC_BUFSIZE];\r
- int numBytesRead, numAvailByte;\r
-\r
- ser_AvailChar (&numAvailByte);\r
- if (numAvailByte > 0) {\r
- if (CDC_DepInEmpty) {\r
- numBytesRead = ser_Read (&serBuf[0], &numAvailByte);\r
-\r
- CDC_DepInEmpty = 0;\r
- USB_WriteEP (CDC_DEP_IN, (unsigned char *)&serBuf[0], numBytesRead);\r
- }\r
- }\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
- Reads character from USB buffer and writes to serial port buffer\r
- *---------------------------------------------------------------------------*/\r
-void VCOM_Usb2Serial(void) {\r
- static char serBuf [32];\r
- int numBytesToRead, numBytesRead, numAvailByte;\r
-\r
- CDC_OutBufAvailChar (&numAvailByte);\r
- if (numAvailByte > 0) {\r
- numBytesToRead = numAvailByte > 32 ? 32 : numAvailByte;\r
- numBytesRead = CDC_RdOutBuf (&serBuf[0], &numBytesToRead);\r
-#if PORT_NUM\r
- ser_Write (1, &serBuf[0], &numBytesRead);\r
-#else\r
- ser_Write (0, &serBuf[0], &numBytesRead);\r
-#endif\r
- }\r
-\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- checks the serial state and initiates notification\r
- *---------------------------------------------------------------------------*/\r
-void VCOM_CheckSerialState (void) {\r
- unsigned short temp;\r
- static unsigned short serialState;\r
-\r
- temp = CDC_GetSerialState();\r
- if (serialState != temp) {\r
- serialState = temp;\r
- CDC_NotificationIn(); // send SERIAL_STATE notification\r
- }\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
- Main Program\r
- *---------------------------------------------------------------------------*/\r
-int main (void) {\r
- SystemInit();\r
-\r
- VCOM_Init(); // VCOM Initialization\r
-\r
- USB_Init(); // USB Initialization\r
- USB_Connect(TRUE); // USB Connect\r
-\r
- while (!USB_Configuration) ; // wait until USB is configured\r
-\r
- while (1) { // Loop forever\r
- VCOM_Serial2Usb(); // read serial port and initiate USB event\r
- VCOM_CheckSerialState();\r
- VCOM_Usb2Serial();\r
- } // end while\r
-} // end main ()\r
-\r
-/*\r
- * @}\r
- */\r
+/*----------------------------------------------------------------------------
+ * Name: vcomdemo.c
+ * Purpose: USB virtual COM port Demo
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC microcontroller devices only. Nothing else
+ * gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#include <board.h>
+#include "lpc_types.h"
+
+#include "usb.h"
+#include "cfg.h"
+#include "hw.h"
+#include "core.h"
+#include "cdc.h"
+#include "cdcuser.h"
+#include "serial.h"
+#include "vcom.h"
+
+/* Example group ----------------------------------------------------------- */
+/** @defgroup USBDEV_USBCDC USBCDC
+ * @ingroup USBDEV_Examples
+ * @{
+ */
+
+/*----------------------------------------------------------------------------
+ Initialises the VCOM port.
+ Call this function before using VCOM_putchar or VCOM_getchar
+ *---------------------------------------------------------------------------*/
+void VCOM_Init(void) {
+#if PORT_NUM
+ CDC_Init (1);
+#else
+ CDC_Init (0);
+#endif
+}
+
+
+/*----------------------------------------------------------------------------
+ Reads character from serial port buffer and writes to USB buffer
+ *---------------------------------------------------------------------------*/
+void VCOM_Serial2Usb(void) {
+ static char serBuf [USB_CDC_BUFSIZE];
+ int numBytesRead, numAvailByte;
+
+ ser_AvailChar (&numAvailByte);
+ if (numAvailByte > 0) {
+ if (CDC_DepInEmpty) {
+ numBytesRead = ser_Read (&serBuf[0], &numAvailByte);
+
+ CDC_DepInEmpty = 0;
+ USB_WriteEP (CDC_DEP_IN, (unsigned char *)&serBuf[0], numBytesRead);
+ }
+ }
+
+}
+
+/*----------------------------------------------------------------------------
+ Reads character from USB buffer and writes to serial port buffer
+ *---------------------------------------------------------------------------*/
+void VCOM_Usb2Serial(void) {
+ static char serBuf [32];
+ int numBytesToRead, numBytesRead, numAvailByte;
+
+ CDC_OutBufAvailChar (&numAvailByte);
+ if (numAvailByte > 0) {
+ numBytesToRead = numAvailByte > 32 ? 32 : numAvailByte;
+ numBytesRead = CDC_RdOutBuf (&serBuf[0], &numBytesToRead);
+#if PORT_NUM
+ ser_Write (1, &serBuf[0], &numBytesRead);
+#else
+ ser_Write (0, &serBuf[0], &numBytesRead);
+#endif
+ }
+
+}
+
+
+/*----------------------------------------------------------------------------
+ checks the serial state and initiates notification
+ *---------------------------------------------------------------------------*/
+void VCOM_CheckSerialState (void) {
+ unsigned short temp;
+ static unsigned short serialState;
+
+ temp = CDC_GetSerialState();
+ if (serialState != temp) {
+ serialState = temp;
+ CDC_NotificationIn(); // send SERIAL_STATE notification
+ }
+}
+
+/*
+ * @}
+ */
-/*----------------------------------------------------------------------------\r
- * Name: vcomdemo.h\r
- * Purpose: USB virtual COM port Demo Definitions\r
- * Version: V1.02\r
- *----------------------------------------------------------------------------\r
- * This software is supplied "AS IS" without any warranties, express,\r
- * implied or statutory, including but not limited to the implied\r
- * warranties of fitness for purpose, satisfactory quality and\r
- * noninfringement. Keil extends you a royalty-free right to reproduce\r
- * and distribute executable files created using this software for use\r
- * on NXP Semiconductors LPC microcontroller devices only. Nothing else \r
- * gives you the right to use this software.\r
- *\r
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
- *---------------------------------------------------------------------------*/\r
-\r
-/* Push Button Definitions */\r
-#define S2 0x00000400 /* P2.10 */\r
-\r
-/* LED Definitions */\r
-#define LED1 0x00000001 /* P2.00 */\r
-#define LED2 0x00000002 /* P2.01 */\r
-#define LED3 0x00000004 /* P2.02 */\r
-#define LED4 0x00000008 /* P2.03 */\r
-#define LED5 0x00000010 /* P2.04 */\r
-#define LED6 0x00000020 /* P2.05 */\r
-#define LED7 0x00000040 /* P2.06 */\r
-#define LED8 0x00000080 /* P2.07 */\r
-\r
-#define LEDMSK 0x000000FF /* P2.0..7 */\r
-\r
+/*----------------------------------------------------------------------------
+ * Name: vcomdemo.h
+ * Purpose: USB virtual COM port Demo Definitions
+ * Version: V1.02
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC microcontroller devices only. Nothing else
+ * gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+/* Push Button Definitions */
+#define S2 0x00000400 /* P2.10 */
+
+/* LED Definitions */
+#define LED1 0x00000001 /* P2.00 */
+#define LED2 0x00000002 /* P2.01 */
+#define LED3 0x00000004 /* P2.02 */
+#define LED4 0x00000008 /* P2.03 */
+#define LED5 0x00000010 /* P2.04 */
+#define LED6 0x00000020 /* P2.05 */
+#define LED7 0x00000040 /* P2.06 */
+#define LED8 0x00000080 /* P2.07 */
+
+#define LEDMSK 0x000000FF /* P2.0..7 */
+
+void VCOM_Init(void);
+void VCOM_Serial2Usb(void);
+void VCOM_Usb2Serial(void);
+void VCOM_CheckSerialState (void);
git.asbjorn.biz / rapper.git / commitdiff